Single-stage boost class-d amplifier

Abstract

A single-stage boost class-D amplifier is disclosed. The boost class-D amplifier includes a pulse width modulator, a boost controller coupled to the pulse width modulator, a driver coupled to the pulse width modulator and the boost controller, a system voltage source, an inductor coupled to the system voltage source, a first switch, a second switch, a third switch, a fourth switch, a first diode coupled between the third switch and a ground terminal, a second diode coupled between the fourth switch and the ground terminal, and a capacitor coupled between the first switch and the fourth switch. The pulse width modulator is configured to receive an input signal and generate a first modulated signal in response thereto. The boost controller is configured to receive the first modulated signal and generate a second modulated signal in response thereto. The driver is configured to receive the first modulated signal and the second modulated signal and generate a control signal in response thereto.

Description

Technical Field

[0001] This invention relates to a Class D amplifier, and more particularly to a Class D amplifier that incorporates the functionality of a boost converter to increase the output voltage and improve the power conversion efficiency through a single-stage structure. Background Technology

[0002] Audio circuits in mobile phones and portable devices require key characteristics such as low power consumption, small size, and low heat dissipation requirements. However, audio amplifiers are often inefficient heat sources, requiring space-consuming heat sinks. Class D or digital amplifiers offer excellent solutions for reducing size and power requirements. Amplifiers are classified based on specific operating characteristics. Class D amplifiers use transistor switching modes to control power delivery. Class D amplifiers are better suited for various applications because the fully "on" and fully "off" gate signal keeps the power supply to the drive section of the circuit highly efficient. Due to their high efficiency and low heat dissipation, Class D amplifiers are commonly used as low-frequency amplifiers. The advantages of Class D amplifiers for audio playback are similar to the advantages of switching power supplies for power supplies. With Class D amplifiers, the audio input is encoded as a pulse-width modulation (PWM) signal, which drives the power supply to switch on and off, dissipating power only during switching. These "digital" amplifiers can significantly improve the energy efficiency of audio amplifiers, thereby reducing heat dissipation requirements and physical size. Furthermore, recent technological advancements have changed the modulation mechanism, eliminating the need for a low-pass filter at the output, further reducing size and complexity.

[0003] A boost converter is a DC-DC converter that boosts voltage, resulting in an output (load) voltage that is higher than the input (supply) voltage. A boost converter is a switching power supply with at least two semiconductor elements (a diode and a transistor) and at least one energy storage element (inductor). To reduce voltage ripple, filters using capacitors and / or inductors are added at both the input and output terminals.

[0004] One drawback of existing technologies is that using a separate boost converter to generate high voltage to drive a Class D amplifier results in significant power loss. Therefore, this invention proposes a novel driver architecture that combines the boost converter stage and the Class D amplifier into a single stage to improve power conversion efficiency. Summary of the Invention

[0005] An embodiment provides a boost Class-D amplifier. The boost Class-D amplifier includes a pulse width modulator, a boost controller, a driver, a system voltage source, an inductor, a first switch, a second switch, a third switch, a fourth switch, a first diode, a second diode, and a capacitor. The pulse width modulator receives an input signal and generates a first modulated signal accordingly. The boost controller is coupled to the pulse width modulator and receives the first modulated signal and generates a second modulated signal accordingly. The driver is coupled to the pulse width modulator and the boost controller and receives the first and second modulated signals and generates a first control signal, a second control signal, a third control signal, and a fourth control signal accordingly. The system voltage source provides a system voltage. The first diode is coupled between the third switch and ground, the second diode is coupled between the fourth switch and ground, and the capacitor is coupled between the first switch and the fourth switch. The first switch includes a first terminal and a second terminal coupled to the inductor, and a control terminal coupled to the driver, for receiving the first control signal. The second switch includes a first terminal and a second terminal coupled to the inductor, and a control terminal coupled to the driver, for receiving the second control signal. The third switch includes a first terminal coupled to a second terminal of the first switch, a second terminal coupled to a control terminal coupled to a driver, for receiving a third control signal. The fourth switch includes a first terminal coupled to a second terminal of the second switch, a second terminal coupled to a control terminal coupled to a driver, for receiving a fourth control signal.

[0006] The embodiment also provides a boost Class-D amplifier. The boost Class-D amplifier includes a pulse width modulator, a boost controller, a driver, a system voltage source, an inductor, a first switch, a second switch, a third switch, a fourth switch, a first diode, a second diode, a capacitor, and feedback circuitry. The pulse width modulator receives an input signal and generates a first modulated signal accordingly. The boost controller is coupled to the pulse width modulator and receives the first modulated signal and generates a second modulated signal accordingly. The driver is coupled to the pulse width modulator and the boost controller and receives the first and second modulated signals and generates a first control signal, a second control signal, a third control signal, and a fourth control signal accordingly. The system voltage source provides a system voltage. The first diode is coupled between the third switch and ground, the second diode is coupled between the fourth switch and ground, and the capacitor is coupled between the first and fourth switches. The first switch includes a first terminal and a second terminal coupled to the inductor and a control terminal coupled to the driver for receiving the first control signal. The second switch includes a first terminal and a second terminal coupled to the inductor and a control terminal coupled to the driver for receiving the second control signal. The third switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the second terminal, and a control terminal coupled to the driver, for receiving a third control signal. The fourth switch includes a first terminal coupled to the second terminal of the second switch, a second terminal coupled to the second terminal, and a control terminal coupled to the driver, for receiving a fourth control signal. The feedback circuit is coupled across the two ends of the capacitor, the boost controller, and the pulse width modulator to stabilize the first modulation signal and the second modulation signal. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a boost Class D amplifier in the embodiment.

[0008] Figure 2 for Figure 1 A schematic diagram of the switch control signal.

[0009] Figure 3 This is a schematic diagram of the operating current of a boost Class D amplifier.

[0010] Figure 4 Another schematic diagram of the operating current of a boost Class D amplifier.

[0011] Figure 5 This is a schematic diagram of the input and output signals of a boost Class D amplifier with a 99% duty cycle for a high-frequency pulse width modulation signal.

[0012] Figure 6 This is a schematic diagram of the input and output signals of a boost Class D amplifier with a 40% duty cycle for a high-frequency pulse width modulation signal.

[0013] Figure 7This is a schematic diagram of the input and output signals of a boost Class D amplifier with a 10% duty cycle for a high-frequency pulse width modulation signal.

[0014] Figure 8 This is a schematic diagram of a boost Class D amplifier in another embodiment.

[0015] [Symbol Explanation]

[0016] 100, 200: Class D amplifiers

[0017] 110: Pulse Width Modulator

[0018] 120: Boost Controller

[0019] 130: Driver

[0020] 140: System voltage source

[0021] 150: Feedback Circuit

[0022] L: Inductance

[0023] S1~S4: Switches

[0024] D1, D2: Diodes

[0025] GND: Ground terminal

[0026] Co: Capacitor

[0027] SPK: Speaker

[0028] SS1~SS4: Control signals

[0029] IN: Input signal

[0030] SPKS: Output signal

[0031] I1, I2: Current

[0032] PVDD: System voltage Detailed Implementation

[0033] Figure 1 This is a schematic diagram of a boost Class D amplifier 100 in an embodiment. The boost Class D amplifier 100 includes a pulse width modulator 110, a boost controller 120 coupled to the pulse width modulator 110, a driver 130 coupled to the pulse width modulator 110 and the boost controller 120, a system voltage source 140, an inductor L coupled to the system voltage source 140, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first diode D1 coupled between the third switch S3 and ground GND, a second diode D2 coupled between the fourth switch S4 and ground GND, and a capacitor Co coupled between the first switch S1 and the fourth switch S4.

[0034] Pulse width modulator 110 receives the input signal IN and generates a first modulated signal. Boost controller 120 receives the first modulated signal and generates a second modulated signal accordingly. Driver 130 receives the first and second modulated signals and generates a first control signal SS1, a second control signal SS2, a third control signal SS3, and a fourth control signal SS4 accordingly. System voltage source 140 provides the system voltage PVDD.

[0035] The first switch S1 includes a first terminal and a second terminal coupled to the inductor L, and a control terminal coupled to the driver 130, for receiving a first control signal SS1. The second switch S2 includes a first terminal and a second terminal coupled to the inductor L, and a control terminal coupled to the driver 130, for receiving a second control signal SS2. The third switch S3 includes a first terminal and a second terminal coupled to the second terminal of the first switch S1, and a control terminal coupled to the driver 130, for receiving a third control signal SS3. The fourth switch S4 includes a first terminal and a second terminal coupled to the second terminal of the second switch S2, and a control terminal coupled to the driver 130, for receiving a fourth control signal SS4.

[0036] The speaker SPK acts as a load, coupled between the second terminal of the first switch S1 and the first terminal of the fourth switch S4. Capacitor Co and inductor L form a filter to reduce voltage ripple. First diode D1 and second diode D2 are used to prevent reverse current from damaging the circuit.

[0037] Figure 2 for Figure 1 A schematic diagram of the switch control signal. (See diagram below.) Figure 2 As shown, control signal SS1 is a square wave signal with a frequency of 300kHz that controls the first switch S1. Control signal SS2, complementary to control signal SS1, is a square wave signal that controls the second switch S2. Control signal SS3 is a mixed signal of pulse width modulation (PWM) and square wave signals with a frequency of 2MHz that controls the third switch S3. Control signal SS4 is a mixed signal of PWM and square wave signals with a frequency of 2MHz that controls the fourth switch S4. When the first control signal SS1 has a high voltage, the third control signal SS3 has a high-frequency PWM signal, and the fourth control signal SS4 has a high voltage. When the first control signal SS1 has a low voltage, the third control signal SS3 has a high voltage, and the fourth control signal SS4 has a high-frequency PWM signal.

[0038] Figure 3This is a schematic diagram of the operating current of the boost Class D amplifier 100 between time t0 and time t1. Between time t0 and time t1, control signal SS1 has a high voltage, control signal SS2 has a low voltage, SS4 has a high voltage, and control signal SS3 has a pulse width modulation signal, causing the third switch S3 to switch at a frequency of 2MHz. When the third switch S3 is off, current I1 can flow from the system voltage source 140 through inductor L, first switch S1, capacitor Co, speaker SPK, fourth switch S4, second diode D2, and finally to ground GND. When the third switch S3 is on, another current I2 can flow from the system voltage source 140 through inductor L, first switch S1, third switch S3, and first diode D1 to ground GND. During this period, inductor L will be charged by generating a magnetic field. Then, when the third switch S3 is off, the previously generated magnetic field will release current I1 towards speaker SPK.

[0039] Figure 4 This is a schematic diagram of the operating current of the boost Class D amplifier 100 between time t1 and time t2. Between time t1 and time t2, control signal SS1 has a low voltage, control signal SS2 has a high voltage, SS3 has a high voltage, and control signal SS4 has a pulse width modulation signal, enabling the fourth switch S4 to switch at a frequency of 2MHz. When the fourth switch S4 is off, current I1 flows from the system voltage source 140 through inductor L, second switch S2, capacitor Co, speaker SPK, third switch S3, first diode D1, and finally to ground GND. When the fourth switch S4 is on, another current I2 flows from the system voltage source 140 through inductor L, second switch S2, fourth switch S4, and second diode D2 to ground GND. During this period, inductor L will be charged by generating a magnetic field, and then, when the fourth switch S4 is off, the previously generated magnetic field will be released towards speaker SPK into current I1.

[0040] The boost function of the circuit can be represented by the following equation:

[0041] V o =PVDD×k×(1-d) 2 )

[0042] In the equation, Vo represents the output voltage, PVDD represents the system voltage, k represents the boost ratio of the boost converter, and d represents the duty cycle of the high-frequency pulse width modulation signal. Therefore, as described above, the high-frequency switching of the third switch S3 and the fourth switch S4 can increase the voltage of the output signal SPKS.

[0043] Figure 5This is a schematic diagram of the input and output signals of a boost Class-D amplifier 100 with a 99% duty cycle for a high-frequency pulse-width modulated signal. In this embodiment, the input signal IN is a sine wave with an amplitude of 1V. The output signal SPKS can be measured at the speaker SPK. Figure 5 As shown, when the duty cycle of the high-frequency pulse width modulation signal is 99%, the input signal IN and the output signal SPKS can almost overlap each other. This indicates that the circuit architecture of the boost Class D amplifier 100 can at least minimize harmonic distortion.

[0044] Figure 6 This is a schematic diagram of the input and output signals of a boost Class-D amplifier 100 with a 40% duty cycle for a high-frequency pulse-width modulated signal. In this embodiment, the input signal IN is a sine wave with an amplitude of 1V. The output signal SPKS can be measured at the speaker SPK. Figure 6 As shown, when the duty cycle of the high-frequency pulse width modulation signal is 40%, the output signal SPKS can be amplified to 3V. This demonstrates that the circuit architecture of the boost Class D amplifier 100 can amplify the input signal IN according to the duty cycle of the high-frequency pulse width modulation signal. Therefore, the embodiment effectively combines a Class D amplifier and a boost converter while maintaining signal integrity.

[0045] Figure 7 This diagram illustrates the input and output signals of a boost Class-D amplifier 100 with a 10% duty cycle for a high-frequency pulse-width modulated signal. In this embodiment, the input signal IN is a sine wave with an amplitude of 1V. The output signal SPKS can be measured at the speaker SPK. Figure 7 As shown, when the duty cycle of the high-frequency pulse width modulation signal is 10%, the output signal SPKS can be amplified to 3.6V. This demonstrates that the circuit architecture of the boost Class D amplifier 100 can amplify the input signal IN according to the duty cycle of the high-frequency pulse width modulation signal. A lower duty cycle increases the power boost factor. Therefore, this embodiment effectively combines a Class D amplifier and a boost converter while maintaining signal integrity.

[0046] Figure 8 This is a schematic diagram of a boost Class D amplifier 200 in another embodiment. The boost Class D amplifier 200 includes a pulse width modulator 110, a boost controller 120 coupled to the pulse width modulator 110, a driver 130 coupled to the pulse width modulator 110 and the boost controller 120, a system voltage source 140, an inductor L coupled to the system voltage source 140, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first diode D1 coupled between the third switch S3 and ground GND, a second diode D2 coupled between the fourth switch S4 and ground GND, and a capacitor Co coupled between the first switch S1 and the fourth switch S4.

[0047] The difference between boost Class D amplifier 100 and boost Class D amplifier 200 is that boost Class D amplifier 200 also includes a feedback circuit 150. The feedback circuit 150 is coupled to the capacitor Co, the boost controller 120, and the pulse width modulator 110. The feedback circuit 150 returns a portion of the output signal SPKS to the boost controller 120 and the pulse width modulator 110 to stabilize the first and second modulated signals. The feedback circuit 150 generates a feedback error signal by comparing the output signal SPKS with the input signal IN, and this feedback error signal can be used to control signal distortion. The feedback circuit 150 can amplify the signal more uniformly over a certain frequency range and reduce the sensitivity of signal gain to component variations.

[0048] Therefore, the boost Class-D amplifier of this embodiment effectively combines a Class-D amplifier and a boost converter in a single-stage structure, maintaining signal integrity and eliminating the need for a separate boost converter to drive the Class-D amplifier. The boost Class-D amplifier in this embodiment can improve power conversion efficiency and output a high-quality signal with low total harmonic distortion.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A boost Class-D amplifier, comprising: A pulse-width modulation (PWM) circuit is used to receive an input signal and generate a first modulation signal accordingly. A boost controller, coupled to the pulse width modulator, is used to receive the first modulation signal and generate a second modulation signal accordingly; A driver, coupled to the pulse width modulator and the boost controller, is used to receive the first modulation signal and the second modulation signal, and generate a first control signal, a second control signal, a third control signal and a fourth control signal accordingly. System voltage source, used to provide system voltage; An inductor is coupled to the system voltage source; The first switch includes: The first end is coupled to the inductor; The second end; and The control terminal, coupled to the driver, is used to receive the first control signal; The second switch includes: The first end is coupled to the inductor; The second end; and The control terminal is coupled to the driver to receive the second control signal; The third switch includes: The first terminal is coupled to the second terminal of the first switch; The second end; and The control terminal is coupled to the driver to receive the third control signal; The fourth switch includes: The first terminal is coupled to the second terminal of the second switch; The second end; and The control terminal is coupled to the driver to receive the fourth control signal; The first diode is coupled between the second terminal of the third switch and the ground terminal; The second diode is coupled between the second terminal of the fourth switch and the ground terminal; and A capacitor is coupled between the second terminal of the first switch and the first terminal of the fourth switch. The first control signal and the second control signal are complementary.

2. The boost Class D amplifier of claim 1 further includes a speaker coupled between the second terminal of the first switch and the first terminal of the fourth switch.

3. The boost Class D amplifier as claimed in claim 1, wherein the first switch, the second switch, the third switch and the fourth switch are bipolar junction transistors.

4. The boost Class D amplifier as claimed in claim 1, wherein the first switch, the second switch, the third switch and the fourth switch are metal-oxide-semiconductor field-effect transistors.

5. The boost Class D amplifier of claim 1, wherein when the first control signal has a high voltage, the second control signal has a low voltage, the third control signal has a high-frequency pulse width modulation signal, and the fourth control signal has a high voltage.

6. The boost Class D amplifier of claim 1, wherein when the first control signal has a low voltage, the second control signal has a high voltage, the fourth control signal has a high-frequency pulse width modulation signal, and the third control signal has a high voltage.

7. A boost Class-D amplifier, comprising: A pulse-width modulation (PWM) circuit is used to receive an input signal and generate a first modulation signal accordingly. A boost controller, coupled to the pulse width modulator, is used to receive the first modulation signal and generate a second modulation signal accordingly; A driver, coupled to the pulse width modulator and the boost controller, is used to receive the first modulation signal and the second modulation signal, and generate a first control signal, a second control signal, a third control signal and a fourth control signal accordingly. System voltage source, used to provide system voltage; An inductor is coupled to the system voltage source; The first switch includes: The first end is coupled to the inductor; The second end; and The control terminal, coupled to the driver, is used to receive the first control signal; The second switch includes: The first end is coupled to the inductor; The second end; and The control terminal is coupled to the driver to receive the second control signal; The third switch includes: The first terminal is coupled to the second terminal of the first switch; The second end; and The control terminal is coupled to the driver to receive the third control signal; The fourth switch includes: The first terminal is coupled to the second terminal of the second switch; The second end; and The control terminal is coupled to the driver to receive the fourth control signal; The first diode is coupled between the second terminal of the third switch and the ground terminal; The second diode is coupled between the second terminal of the fourth switch and the ground terminal; A capacitor is coupled between the second terminal of the first switch and the first terminal of the fourth switch; and A feedback circuit, coupled to both ends of the capacitor, the boost controller, and the pulse width modulator, is used to stabilize the first modulation signal and the second modulation signal. The first control signal and the second control signal are complementary.

8. The boost Class D amplifier of claim 7 further includes a speaker coupled between the second terminal of the first switch and the first terminal of the fourth switch.

9. The boost Class D amplifier of claim 7, wherein the first switch, the second switch, the third switch and the fourth switch are bipolar junction transistors.

10. The boost Class D amplifier of claim 7, wherein the first switch, the second switch, the third switch and the fourth switch are metal-oxide-semiconductor field-effect transistors.

11. The boost Class D amplifier of claim 7, wherein when the first control signal has a high voltage, the second control signal has a low voltage, the third control signal has a high-frequency pulse width modulation signal, and the fourth control signal has a high voltage.

12. The boost Class D amplifier of claim 7, wherein when the first control signal has a low voltage, the second control signal has a high voltage, the fourth control signal has a high-frequency pulse width modulation signal, and the third control signal has a high voltage.

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