A method, device, electronic device and medium for accessing a register

Abstract

The present application discloses a method, device, electronic device and medium for accessing registers, and relates to the field of electronic technology. It includes: setting registers according to standard PCIe specifications so that the CPU can access the registers through PCIe; dividing the data on each PCIe address into multiple bytes according to the data bit width of IIC; obtaining the base address and offset address of IIC so that the BMC can access the registers through the address of IIC, the base address is the address of PCIe, and the offset address is bytes. In this method, since the registers are set according to the standard PCIe specifications, the CPU can access the registers through PCIe; since the address of IIC is obtained according to the PCIe address, the BMC can access the information accessed by the CPU through PCIe through IIC, therefore, the CPU and BMC can access the same register together, and there is no need to add additional registers, thus reducing the waste of resources.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method, device, electronic device and medium for accessing a register. Background Art

[0002] Complex Programmable Logic Device (CPLD) / Field Programmable Gate Array (FPGA) is a semi-customized application-specific integrated circuit with a series of advantages such as flexible programming, fast response, and high integration. It is increasingly widely used in the field of early development verification and control applications. In the switch system, CPLD is mainly used for control layer management, such as switch system power-on and power-off timing control, dual basic input and output system (BIOS) switching control, universal asynchronous receiver / transmitter (UART) switching management control, register management, etc.; FPGA is mainly used for data communication management, such as IIC Devices management, PHY Devices management, register management, etc.

[0003] Register management is a problem that CPLD / FPGA will face in switch and other projects. To improve work efficiency, in FPGA design, the central processing unit (CPU) will access and manage FPGA registers through PCIe, and at the same time, the baseboard management controller (BMC) will access and manage FPGA registers based on the general integrated circuit bus (IIC) interface. FPGA registers need to meet the needs of CPU accessing FPGA registers through PCIe and BMC accessing FPGA registers through IIC. However, due to the different address bit widths and data bit widths of PCIe and IIC, registers can only be accessed by one of the CPU or BMC, which cannot meet the requirements of CPU / BMC using the same register; or two sets of registers need to be set, which requires the design of additional register synchronization logic, wasting FPGA logic resources.

[0004] It can be seen that how to enable a CPU based on PCIe and a BMC based on IIC to access the same register is a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The purpose of the present application is to provide a method, device, electronic device and medium for accessing a register, so as to enable both a CPU and a BMC to access the same register, thereby improving the performance of the register and improving the working efficiency of devices such as switches.

[0006] To solve the above technical problems, the present application provides a method for accessing registers compatible with PCIe and IIC, including:

[0007] Setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through the PCIe;

[0008] Dividing the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC;

[0009] The address of the IIC is obtained so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to a base address and an offset address, the base address is the address of the PCIe, and the offset address is the byte.

[0010] In order to solve the above technical problems, the present application also provides a device compatible with PCIe and IIC access registers, including a CPU, a BMC, an IIC slave device, a PCIe terminal device, and the registers, wherein the BMC includes an IIC master device, and the CPU includes a PCIe initiator device;

[0011] The IIC master device communicates with the IIC slave device via IIC; the IIC slave device accesses the register; the PCIe initiator device communicates with the PCIe terminal device via PCIe; the PCIe terminal device accesses the register so as to set the data bit width and address bit width of the register according to the standard PCIe specification, so as to facilitate the CPU to access the register via the PCIe; so as to divide the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC; obtain the address of the IIC, so as to facilitate the BMC to access the register via the address of the IIC, wherein the address of the IIC is obtained according to the base address and the offset address, the base address is the address of the PCIe, and the offset address is the byte.

[0012] Preferably, the registers include general registers and CPU registers; wherein the general registers are registers accessed by the CPU and the BMC.

[0013] Preferably, the address of the register is within a preset range, the address of the general register is located at a low position within the preset range; and the address of the CPU register is located at a high position within the preset range.

[0014] Preferably, the general register includes a register that allows the CPU to write or a register that allows the BMC to write.

[0015] Preferably, the IIC slave device and the PCIe terminal device use different reset signals.

[0016] Preferably, the PCIe terminal device adopts a hard core design, and the IIC slave device adopts an IIC timing design.

[0017] In order to solve the above technical problems, the present application also provides a device compatible with PCIe and IIC access registers, including:

[0018] A setting module, used for setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through the PCIe;

[0019] A division module, used for dividing the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC;

[0020] The acquisition module is used to acquire the address of the IIC so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to a base address and an offset address, the base address is the address of the PCIe, and the offset address is the byte.

[0021] In order to solve the above technical problems, the present application also provides an electronic device, including:

[0022] Memory for storing computer programs;

[0023] A processor is used to implement the steps of the above-mentioned method for accessing registers compatible with PCIe and IIC when executing the computer program.

[0024] In order to solve the above problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for accessing registers compatible with PCIe and IIC are implemented.

[0025] The method for accessing registers compatible with PCIe and IIC provided in the present application includes: setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through PCIe; dividing the data on each PCIe address into multiple bytes according to the data bit width of IIC; obtaining the address of IIC so that the BMC can access the register through the address of IIC, wherein the address of IIC is obtained according to the base address and the offset address, the base address is the address of PCIe, and the offset address is bytes. In this method, for the CPU, since the register is set according to the standard PCIe specification, the CPU can access the register through PCIe; for the BMC, since the address of IIC is obtained according to the PCIe address, the BMC can access the information accessed by the CPU through PCIe through IIC, thereby realizing that the CPU and BMC can access the same register together, and there is no need to add additional registers, thereby reducing the waste of resources.

[0026] In addition, the present application also provides a device, electronic device and computer-readable storage medium compatible with PCIe and IIC access registers, which have the same or corresponding technical features as the above-mentioned method compatible with PCIe and IIC access registers, and have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A flowchart of a method for accessing registers compatible with PCIe and IIC provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a device compatible with PCIe and IIC access registers provided in an embodiment of the present application;

[0030] Figure 3 A structural diagram of a device compatible with PCIe and IIC access registers provided in one embodiment of the present application;

[0031] Figure 4 A structural diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] The core of this application is to provide a method, device, electronic device and medium for accessing a register, which is used to enable a PCIe-based CPU and an IIC-based BMC to access the same register, thereby improving the performance of the register and improving the working efficiency of devices such as switches.

[0034] FPGA registers need to meet the requirements of CPU accessing FPGA registers through PCIe and BMC accessing FPGA registers through IIC at the same time. However, due to the different address widths and data widths of PCIe and IIC, the registers can only be accessed by one of the CPU or BMC, which cannot meet the requirement of CPU / BMC using the registers together; or two sets of registers are set, which requires the design of additional register synchronization logic, wasting FPGA logic resources. Therefore, this application uses the relationship between the data width of PCIe and the data width of IIC, and the address width of PCIe and the address width of IIC to realize that only one set of registers is needed to achieve that both CPU and BMC can access the register. It should be noted that the definition method of compatible PCIe and IIC register access interface provided in this embodiment is not only applicable to the field of switches, but also has certain reference significance for the simultaneous design of CPU accessing and managing FPGA registers through PCIe and BMC accessing through IIC.

[0035] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Figure 1 A flowchart of a method for accessing registers compatible with PCIe and IIC provided in an embodiment of the present application, such as Figure 1 As shown, the method includes:

[0036] S10: Setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through PCIe.

[0037] The address width and data width of standard PCIe are both 32 bits, while those of standard IIC are both 8 bits. Therefore, the address width and data width of standard PCIe and standard IIC are different. Therefore, a CPU based on PCIe and a BMC based on IIC cannot access the same set of registers.

[0038] Since the address width and data width of the standard PCIe are larger than those of the standard IIC, if the data width and address width of the register are set according to the standard IIC, PCIe cannot access the corresponding address. In addition, since the PCIe data width is 32 bits, the address information presents a four-bit arithmetic sequence: for example, 0X000-->0X004-->0X008-->0X0C0..., while the IIC data width is 8 bits, and the address is continuous: for example, 0X00-->0X01-->0X02-->0X03...; therefore, the data width and address width of the register can be formulated according to the standard PCIe specification, that is, the data width and address width are both 32 bits.

[0039] It should be noted that the registers are set according to the standard PCIe. In practice, the registers may not be set according to the standard PCIe. However, if the registers are not set according to the standard PCIe, since the data bit width and address bit width of PCIe may not be multiples of the data bit width and address bit width of IIC, the method of implementing the CPU and BMC to access the same set of registers together may become complicated. Therefore, this embodiment adopts the standard PCIe and the standard IIC, and sets the registers according to the standard PCIe specification.

[0040] When the CPU accesses the register through PCIe, since the register is set according to the standard PCIe specification, the CPU can directly access the register through PCIe. It is worth noting that the register accessed in this application is an FPGA register.

[0041] S11: Divide the data at each PCIe address into multiple bytes according to the data bit width of the IIC.

[0042] S12: Obtain the address of the IIC so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to the base address and the offset address, the base address is the address of the PCIe, and the offset address is a byte.

[0043] Since the data bit width and address bit width of standard PCIe are four times that of standard IIC, the multiple relationship between the two can be used to ensure that the CPU and BMC can access the same set of registers, thereby avoiding the definition of two sets of registers, saving FPGA hardware resources, and avoiding the complex logic problems caused by register interaction.

[0044] The data width of IIC is 8 bits, and the data width of PCIe is 32 bits. Therefore, the data at each address of PCIe can be divided into 4 bytes according to the data width of IIC. The address of IIC is the PCIe base address + address offset. For example, the 32-bit data at the address 0X000 accessed by the CPU can be divided into 0X00 corresponding to DATA[7:0] in 32-bit data, 0X01 corresponding to DATA[15:8] in 32-bit data, 0X02 corresponding to DATA[23:16] in 32-bit data, and 0X03 corresponding to DATA[31:24] in 32-bit data according to the definition of IIC; for the CPU side, the PCIe address is 0X004, and IIC can also be divided into four bytes according to the above rules; ... and so on, the address range of 0X00~0XFF can be divided according to this rule. Table 1 is the register design rule table. As shown in Table 1, taking Project 1 as an example, the CPU access register address is 0X00, the CPU access register bit width is [31:0], the BMC access register corresponding bytes are Byte0 to Byte3, and the BMC access register corresponding address is 8'h00 to 8'h03.

[0045] Table 1 Register design rules table

[0046]

[0047]

[0048] The method for accessing registers compatible with PCIe and IIC provided in this embodiment includes: setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through PCIe; dividing the data on each PCIe address into multiple bytes according to the data bit width of IIC; obtaining the address of IIC so that the BMC can access the register through the address of IIC, wherein the address of IIC is obtained according to the base address and the offset address, the base address is the address of PCIe, and the offset address is bytes. In this method, for the CPU, since the register is set according to the standard PCIe specification, the CPU can access the register through PCIe; for the BMC, since the address of IIC is obtained according to the PCIe address, the BMC can access the information accessed by the CPU through PCIe through IIC, thereby achieving that the CPU and BMC can access the same register together, and there is no need to add additional registers, thereby reducing the waste of resources.

[0049] On the basis of the above embodiment, this embodiment further provides a device compatible with PCIe and IIC access registers. Figure 2 A schematic diagram of a device compatible with PCIe and IIC access registers provided in an embodiment of the present application, such as Figure 2As shown, the entire device includes CPU 1, BMC 2, and FPGA 3. CPU 1 and BMC 2 jointly access FPGA 3. Specifically, CPU 1 includes a PCIe originating device (CPU Root); BMC 2 includes an IIC master device (IIC Master); FPGA 3 includes an IIC slave device (IICSlave), a PCIe terminal device (PCIe Endpoint), and a register.

[0050] The IIC master device communicates with the IIC slave device through the IIC; the IIC slave device accesses the register; the PCIe initiator device communicates with the PCIe terminal device through the PCIe; the PCIe terminal device accesses the register so as to set the data bit width and address bit width of the register according to the standard PCIe specification, so as to facilitate the CPU to access the register through the PCIe; so as to divide the data on each PCIe address into multiple bytes according to the data bit width of the IIC; obtain the address of the IIC so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to the base address and the offset address, the base address is the PCIe address, and the offset address is the byte.

[0051] FPGA realizes PCIe communication between CPU and FPGA through PCIe terminal device. This function depends on the IO support of FPGA itself, that is, to realize high-speed IO. There are many application occasions for realizing PCIe communication between CPU and FPGA, and its purpose is to realize high-speed PCIe communication between CPU and FPGA. Different hard-core configuration interfaces are provided for development tools of different manufacturers, but the basic configuration items are the same. This function also depends on whether FPGA supports it.

[0052] The IIC slave device is implemented inside the FPGA to achieve IIC communication between the BMC and the FPGA. The IIC slave device complies with the standard IIC timing and is designed using the Verilog hardware description language, which is divided into read and write processes. The IIC standard read and write processes will not be described here.

[0053] The PCIe data width is 32 bits, the IIC data width is 8 bits, and the PCIe address information is distributed in an arithmetic sequence every 4 bits. Therefore, the 32-bit data of PCIe can be divided into 4 bytes. At the same time, the PCIe address is used as the base address of IIC, and 4 bytes are used as the address offset of IIC. Based on this mechanism, the BMC can obtain the 32-bit information of a PCIe access by four reads and writes. After obtaining this information, the BMC splices it according to the actual situation. After splicing, logical operations and display are performed, and there are requirements for the BMC display design. For example, the information accessed by the CPU through PCIe is 10226709, and when the BMC accesses the register through IIC, the first access may access 10; the second access may access 22; the third access may access 67; the fourth access may access 09. So far, after four accesses, the information accessed by the CPU is obtained. The information of each access is combined according to the actual situation, and finally the information is the same as the information accessed by the CPU through PCIe.

[0054] Based on the above description, the design of the PCIe terminal device is implemented on the FPGA; the IIC slave device interface design is implemented on the FPGA; the register interface is designed according to the register design rules in Table 1; the image is generated and downloaded after comprehensive compilation, and the CPU accesses the FPGA register through PCIe and accesses the FPGA register through IIC through BMC under the operating system to verify the effectiveness of the mechanism.

[0055] The device compatible with PCIe and IIC access registers provided in this embodiment implements the CPU accessing FPGA registers through PCIe and the BMC accessing FPGA registers through IIC according to the register design rules. In this device, for the CPU, since the registers are set according to the standard PCIe specification, the CPU can access the registers through PCIe; for the BMC, since the address of IIC is obtained according to the PCIe address, the BMC can access the information accessed by the CPU through PCIe through IIC, thus implementing the PCIe-based CPU and the IIC-based BMC to access the same register together, without adding additional registers, reducing the waste of resources and avoiding the complex logic problems caused by register interactive communication.

[0056] In practice, since the frequency of accessing registers through the CPU is much greater than the frequency of accessing registers through the BMC, in order to improve the working efficiency of the switch, a preferred implementation is that the registers include general registers and CPU registers; wherein the general registers are registers for CPU and BMC access.

[0057] Registers are divided into general read / write registers and CPU-operated registers. General registers are registers that can be accessed by both the PCIe-based CPU and the IIC-based BMC. CPU-operated registers are registers that can only be accessed by the PCIe-based CPU. Figure 2 As shown, the registers include a general write register, a general read register, a CPU write register, and a CPU read register.

[0058] The registers provided in this embodiment include general registers and CPU registers. On the one hand, the general registers in the registers can be accessed by the CPU and the BMC together; on the other hand, in addition to the general registers, the CPU registers are added to improve the working efficiency of the switch.

[0059] Since the address bit width of standard PCIe is much larger than that of standard IIC, the BMC may not be able to access the high-order address. Therefore, the preferred implementation method is that the address of the register is within a preset range, the address of the general register is located at the low order within the preset range; and the address of the CPU register is located at the high-order address within the preset range.

[0060] At the same time, in order to avoid write conflicts between the CPU and the BMC, as a preferred implementation, the general registers include registers that only allow the CPU to write or registers that only allow the BMC to write. When determining whether only the CPU is allowed to write or only the BMC is allowed to write, a selection is made according to actual needs.

[0061] The preset range in this embodiment is 0X00~0XFF, and the general read-write register should be placed in the low address of 0X00~0XFF, but the CPU access management special register is placed in the high address. It should be noted that the standard IIC cannot access the registers above the address of 0XFF, and only the PCIe protocol is allowed to access in this application. If the IIC protocol also needs to be accessed, the IIC communication protocol needs to be modified, that is, the bit width of the IIC communication protocol is extended. Through the method of this embodiment, the BMC can access the general registers, and because the CPU can access the general registers and CPU registers, the working efficiency of the switch is improved.

[0062] In order to prevent the communication between the IIC slave device and the PCIe terminal device from affecting each other, a preferred implementation is that the IIC slave device and the PCIe terminal device use different reset signals.

[0063] Different reset signals are used to achieve decoupling design, thereby preventing mutual influence between the communication between the IIC slave device and the PCIe terminal device.

[0064] In addition, since the requirements for CPU access to registers are higher than those for BMC access to registers, a hard-core design is used for PCIe terminal devices, and an IIC timing design is used for IIC slave devices, so that the register design can be implemented according to the requirements.

[0065] In the above embodiments, the method for accessing registers compatible with PCIe and IIC is described in detail, and the present application also provides embodiments corresponding to the apparatus compatible with PCIe and IIC accessing registers. It should be noted that the present application describes the embodiments of the apparatus part from two perspectives, one is based on the perspective of functional modules, and the other is based on the perspective of hardware.

[0066] Figure 3 A structural diagram of a device compatible with PCIe and IIC access registers provided in one embodiment of the present application. This embodiment is based on the perspective of functional modules and includes:

[0067] A setting module 10, used to set the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through PCIe;

[0068] A division module 11 is used to divide the data at each PCIe address into multiple bytes according to the data bit width of the IIC;

[0069] The acquisition module 12 is used to acquire the address of the IIC so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to the base address and the offset address, the base address is the address of the PCIe, and the offset address is a byte.

[0070] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0071] The device compatible with PCIe and IIC access registers provided in this embodiment is used to set the data bit width and address bit width of the register according to the standard PCIe specification through a setting module so that the CPU can access the register through PCIe; the data on each PCIe address is divided into multiple bytes according to the data bit width of IIC through a division module; the address of IIC is obtained according to the base address and the offset address, the base address is the address of PCIe, and the offset address is bytes. In this device, for the CPU, since the register is set according to the standard PCIe specification, the CPU can access the register through PCIe; for the BMC, since the address of IIC is obtained according to the PCIe address, the BMC can access the information accessed by the CPU through PCIe through IIC, thereby achieving that the CPU and BMC can access the same register together, and there is no need to add additional registers, which reduces the waste of resources and avoids the complex logic problems caused by register interaction.

[0072] Figure 4 This is a structural diagram of an electronic device provided in another embodiment of the present application. This embodiment is based on the hardware perspective, such as Figure 4 As shown, the electronic equipment includes:

[0073] A memory 20, for storing computer programs;

[0074] The processor 21 is used to implement the steps of the method for accessing registers compatible with PCIe and IIC as mentioned in the above embodiment when executing a computer program.

[0075] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0076] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of a digital signal processor (DSP), an FPGA, and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU; the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0077] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the method for compatible PCIe and IIC access registers disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. Data 203 may include but is not limited to the data involved in the above-mentioned method for compatible PCIe and IIC access registers.

[0078] In some embodiments, the electronic device may further include a display screen 22 , an input / output interface 23 , a communication interface 24 , a power source 25 , and a communication bus 26 .

[0079] Those skilled in the art will understand that Figure 4 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0080] The electronic device provided in the embodiment of the present application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: a method compatible with PCIe and IIC access registers, with the same effect as above.

[0081] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

[0082] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0083] The computer-readable storage medium provided in the present application includes the above-mentioned method for accessing registers compatible with PCIe and IIC, and the effect is the same as above.

[0084] The above is a detailed introduction to a method, device, electronic device and medium for accessing a register provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0085] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method for accessing registers compatible with PCIe and IIC, characterized in that: include: Setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through the PCIe; Dividing the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC; The address of the IIC is obtained so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to a base address and an offset address, the base address is the address of the PCIe, and the offset address is the byte.

2. A device compatible with PCIe and IIC access registers, characterized in that: It includes a CPU, a BMC, an IIC slave device, a PCIe terminal device, and the register, wherein the BMC includes an IIC master device, and the CPU includes a PCIe initiator device; The IIC master device communicates with the IIC slave device via IIC; the IIC slave device accesses the register; the PCIe initiator device communicates with the PCIe terminal device via PCIe; the PCIe terminal device accesses the register so as to set the data bit width and address bit width of the register according to the standard PCIe specification, so as to facilitate the CPU to access the register via the PCIe; so as to divide the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC; obtain the address of the IIC, so as to facilitate the BMC to access the register via the address of the IIC, wherein the address of the IIC is obtained according to the base address and the offset address, the base address is the address of the PCIe, and the offset address is the byte.

3. The device compatible with PCIe and IIC access registers according to claim 2, characterized in that: The registers include general registers and CPU registers; wherein the general registers are registers used for access by the CPU and the BMC.

4. The device compatible with PCIe and IIC access registers according to claim 3, characterized in that: The address of the register is within a preset range, the address of the general register is at a low position within the preset range; and the address of the CPU register is at a high position within the preset range.

5. The device compatible with PCIe and IIC access registers according to claim 3 or 4, characterized in that: The general registers include registers that are allowed to be written by the CPU or registers that are allowed to be written by the BMC.

6. The device compatible with PCIe and IIC access registers according to claim 2, characterized in that: The IIC slave device and the PCIe terminal device use different reset signals.

7. The device compatible with PCIe and IIC access registers according to claim 2, characterized in that: The PCIe terminal device adopts a hard core design, and the IIC slave device adopts an IIC timing design.

8. A device compatible with PCIe and IIC access registers, characterized in that: include: A setting module, used for setting the data bit width and address bit width of the register according to the standard PCIe specification so that the CPU can access the register through the PCIe; A division module, used for dividing the data at each address of the PCIe into multiple bytes according to the data bit width of the IIC; The acquisition module is used to acquire the address of the IIC so that the BMC can access the register through the address of the IIC, wherein the address of the IIC is obtained according to a base address and an offset address, the base address is the address of the PCIe, and the offset address is the byte.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for accessing registers compatible with PCIe and IIC as claimed in claim 1 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for accessing registers compatible with PCIe and IIC as claimed in any one of claims 1 are implemented.

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