A branch prediction method and related device for branch instructions

Abstract

The present application provides a branch prediction method and related apparatus for branch instructions, wherein the method is applied to a TAGE branch predictor. The TAGE branch predictor determines a branch prediction table entry for the branch instruction based on the instruction address of the branch instruction to be predicted and global branch histories of varying lengths. The TAGE branch predictor determines, based on the branch prediction table entry, whether a saturated counter update value for the branch instruction exists in a preset IUM module. If the saturated counter update value exists in the IUM module, the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction. Embodiments of the present application are advantageous for improving the prediction accuracy of the TAGE branch predictor.

Description

Technical Field

[0001] The present application relates to the technical field of processor branch prediction, and in particular to a branch prediction method and related devices for branch instructions. Background Art

[0002] Currently, most processor architectures use an instruction pipeline to execute instructions in a pipelined manner. While this can increase the processor's instruction throughput, it requires timely determination of whether an instruction needs to jump and which instruction to jump to when encountering a branch instruction. Determining this information takes time, which interrupts the pipeline flow and causes performance loss for the processor. Therefore, a branch prediction mechanism is needed. Through certain algorithms, it is possible to predict in advance whether a branch instruction will jump and the target address of the jump, thereby ensuring the continuity of the instruction flow as much as possible and improving the overall performance of the processor. The TAGE (TAggedGEmoetric history length branch prediction) branch predictor is one of the branch prediction algorithms with a relatively high prediction accuracy. However, the accuracy of its branch prediction is highly dependent on training data. Therefore, improving the prediction accuracy of the TAGE branch predictor is an urgent problem that needs to be solved. Summary of the Invention

[0003] In response to the above problems, the present application provides a branch prediction method and related devices for branch instructions, which are beneficial to improving the prediction accuracy of the TAGE branch predictor.

[0004] To achieve the above objectives, a first aspect of an embodiment of the present application provides a branch prediction method for a branch instruction, which is applied to a TAGE branch predictor. The method includes:

[0005] The TAGE branch predictor determines the branch prediction table entry for the branch instruction based on the instruction address of the branch instruction to be predicted and the global branch history of different lengths;

[0006] The TAGE branch predictor determines whether there is a saturation counter update value of the branch instruction in the preset IUM module based on the branch prediction table entry;

[0007] When a saturated counter update value exists in the IUM module, the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction.

[0008] In conjunction with the first aspect, in one possible implementation, the TAGE branch predictor determines, based on a branch prediction table entry of the branch instruction, whether a saturation counter update value for the branch instruction exists in a preset IUM module, including:

[0009] The TAGE branch predictor inputs a branch prediction table entry to the IUM module through the Provider interface of the IUM module. The branch prediction table entry includes the first tag information of the branch instruction. The first tag information is used by the IUM module to determine whether the branch prediction table entry is hit in the IUM module.

[0010] The TAGE branch predictor obtains the Resp interface returned by the IUM module. If the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is hit in the IUM module, it is determined that a saturated counter update value exists in the IUM module; if the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is not hit in the IUM module, it is determined that no saturated counter update value exists in the IUM module.

[0011] In conjunction with the first aspect, in one possible implementation, before using the saturation counter update value to predict the direction of the branch instruction, the method further includes:

[0012] The TAGE branch predictor receives the saturation counter update value and the instruction fetch target queue pointer corresponding to the saturation counter update value returned by the IUM module through the Resp interface.

[0013] In conjunction with the first aspect, in one possible implementation, before using the saturation counter update value to predict the direction of the branch instruction, the method further includes:

[0014] The TAGE branch predictor obtains the second tag information of the branch instruction sent by the IUM module through the Resp_tag interface returned by the IUM module.

[0015] A second aspect of an embodiment of the present application provides a branch prediction method for a branch instruction, which is applied to an IUM module. The method includes:

[0016] The IUM module obtains the branch prediction table entry of the branch instruction to be predicted input by the TAGE branch predictor through the Provider interface, and the branch prediction table entry includes the first tag information of the branch instruction;

[0017] The IUM module determines whether the content addressable memory stores second tag information matching the first tag information through the enq_tag interface;

[0018] When the IUM module stores the second tag information in the content addressable memory, it determines that the branch prediction table entry is hit in the IUM module, and returns the saturated counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction.

[0019] In conjunction with the second aspect, in one possible implementation, before the IUM module obtains the branch prediction table entry of the branch instruction to be predicted input by the TAGE branch predictor through the Provider interface, the method further includes:

[0020] The IUM module receives the saturation counter value and the jump result of the branch instruction returned by the backend pipeline when the branch instruction was last executed. The saturation counter value is the saturation counter value of the branch instruction in the corresponding table entry of the TAGE branch predictor when it is determined that the branch instruction has a misprediction;

[0021] The IUM module calculates the saturation counter update value of the branch instruction based on the saturation counter value and the jump result;

[0022] The IUM module calculates the second tag information using the instruction address of the branch instruction and global branch histories of different lengths, and stores the saturation counter update value, the second tag information and the corresponding instruction fetch target queue pointer.

[0023] In conjunction with the second aspect, in one possible implementation, the IUM module includes a content-addressable memory and a register file, storing a saturation counter update value, second tag information, and a corresponding instruction fetch target queue pointer, including:

[0024] The IUM module stores the second tag information in the content addressable memory, and stores the saturation counter update value and the instruction fetch target queue pointer in the register file.

[0025] In conjunction with the second aspect, in one possible implementation, the method further includes:

[0026] When the second tag information is stored in the content-addressable memory, the IUM module returns the second tag information to the TAGE branch predictor through the Resp_tag interface.

[0027] In conjunction with the second aspect, in one possible implementation, the target queue pointer is retrieved to mark the saturation counter update value and the time when the second tag information is enqueued in the IUM module. The method further includes:

[0028] When a branch instruction is submitted, the IUM module dequeues entries whose enqueue time is earlier than the saturation counter update value and the enqueue time of the second tag information.

[0029] A third aspect of an embodiment of the present application provides a branch prediction device for a branch instruction, which is applied to a TAGE branch predictor. The device includes a first processing unit and a first transceiver unit;

[0030] A first processing unit is configured to determine a branch prediction table entry for a branch instruction according to an instruction address of the branch instruction to be predicted and global branch histories of different lengths;

[0031] The first transceiver unit is configured to determine whether a saturation counter update value of a branch instruction exists in a preset IUM module according to a branch prediction table entry;

[0032] The first processing unit is further configured to, when there is a saturated counter update value in the IUM module, use the saturated counter update value to perform direction prediction on the branch instruction.

[0033] A fourth aspect of an embodiment of the present application provides a branch prediction device for a branch instruction, which is applied to an IUM module. The device includes a second processing unit and a second transceiver unit;

[0034] The second transceiver unit is configured to obtain a branch prediction table entry of a branch instruction to be predicted input by a TAGE branch predictor through a Provider interface, wherein the branch prediction table entry includes first tag information of the branch instruction;

[0035] The second processing unit is configured to determine, through an enq_tag interface, whether second tag information matching the first tag information is stored in the content-addressable memory;

[0036] The second processing unit is further used to determine whether the branch prediction table entry is hit in the IUM module when the second tag information is stored in the content addressable memory, and to call the second transceiver unit to return the saturation counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturation counter update value to predict the direction of the branch instruction.

[0037] A fifth aspect of an embodiment of the present application provides an electronic device, which includes an input device and an output device, and also includes a processor suitable for implementing one or more instructions; and a computer storage medium, wherein the computer storage medium stores one or more instructions, and the one or more instructions are suitable for being loaded by the processor and executed as the method steps in any implementation of the first or second aspect above.

[0038] A sixth aspect of an embodiment of the present application provides a computer storage medium, which stores one or more instructions, and the one or more instructions are suitable for being loaded by a processor and executed by a method step as in any one of the implementations of the first or second aspect above.

[0039] The above-described solution of the present application includes at least the following beneficial effects: It should be understood that when a branch is mispredicted, the branch predictor clears the instructions on the incorrect path, but does not immediately update the saturation counter in the TAGE branch predictor. This results in the TAGE branch predictor's training data being out of date, which can reduce branch prediction accuracy to a certain extent. This application adds an IUM module to the TAGE branch predictor. For the previously executed branch instruction, if it is determined to have been mispredicted, the IUM module calculates the saturation counter update value for the branch instruction and saves the saturation counter update value. When the TAGE branch predictor predicts the branch instruction again, it can simultaneously check whether the relevant table entry for the branch instruction exists in the IUM module. If so, it directly uses the saturation counter update value stored in the IUM module to predict the direction of the branch instruction without waiting for the saturation counter in the TAGE branch predictor to be updated. This improves the efficiency of updating the TAGE branch predictor's training data. The TAGE branch predictor uses the updated data to predict the direction of the branch instruction, which is beneficial to improving the prediction accuracy of the TAGE branch predictor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A schematic diagram of a system architecture provided in an embodiment of the present application;

[0042] Figure 2 A schematic flow chart of a branch prediction method for a branch instruction provided in an embodiment of the present application;

[0043] Figure 3 A flow chart of another branch prediction method for branch instructions provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of an IUM table entry provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of the structure of a branch prediction device for a branch instruction provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the structure of another branch prediction device for branch instructions provided in an embodiment of the present application;

[0047] Figure 7A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0049] The terms "including" and "having," as used in the specification, claims, and drawings of this application, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus. In addition, the terms "first," "second," and "third," etc., are used to distinguish between different objects, not to describe a particular order.

[0050] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0051] The embodiment of the present application provides a branch prediction method for branch instructions. The method can be based on Figure 1 The system architecture shown is implemented as Figure 1As shown, the system architecture may include a branch prediction unit (BPU), a fetch target queue (FTQ), an instruction fetch unit (IFU), and a backend. The BPU includes a TAGE branch predictor and a plug-in for the TAGE branch predictor, namely the IUM (Immediate Update Mimicker) module. The FTQ is used to generate instruction fetch requests, and the IFU executes instruction fetches based on the FTQ's instruction fetch requests. During the instruction fetch phase, the BPU uses the TAGE branch predictor to predict the instruction's direction, determining whether the instruction will jump. It should be understood that the TAGE branch predictor does not provide the instruction's specific jump target address during branch prediction. During branch prediction, the TAGE branch predictor determines whether the branch instruction's table entry matches the IUM module. If so, it uses the branch instruction's saturation counter update value stored in the IUM module to predict the branch instruction's direction. The BPU then sends the branch prediction result to the FTQ. FTQ is also used to send an update signal to the BPU after the backend instruction is submitted, and transmit the updated data. For example: after the backend instruction is submitted, the BPU can update the relevant table entries of the branch prediction table in the TAGE branch predictor. Based on the branch prediction results stored in FTQ, the backend can determine whether the branch instruction has a misprediction when executing the branch instruction, and send a misprediction signal back to FTQ. It can be seen that based on Figure 1 In the system architecture shown, the branch prediction in the instruction fetch stage can check whether there is a relevant table entry for the branch instruction from the IUM module. If so, the saturation counter update value saved in the IUM module is directly used to predict the direction of the branch instruction without waiting for the update of the saturation counter in the TAGE branch predictor.

[0052] See Figure 2 , Figure 2 A flow chart of a branch prediction method for a branch instruction provided in an embodiment of the present application is provided, wherein the method is applied to a TAGE branch predictor, such as Figure 2 As shown, it includes steps 210-230:

[0053] 210: The TAGE branch predictor determines a branch prediction table entry for the branch instruction based on the instruction address of the branch instruction to be predicted and global branch histories of different lengths.

[0054] In an embodiment of the present application, the TAGE branch predictor uses the instruction address of the branch instruction and global branch histories of different lengths to calculate an index value (such as an XOR operation). Among them, global branch histories of different lengths correspond to different branch prediction tables of the branch instruction in the TAGE branch predictor, and the index value calculated using the global branch history with the longest length and the instruction address can index the branch prediction table with the longest global branch history. For example, the index value can hit the table entry of the branch prediction table with the longest global branch history, and the table entry includes the tag information of the branch instruction (i.e., the first tag information). Specifically, the TAGE branch predictor uses the calculated index value to match the tag information of the branch instruction in different branch prediction tables, determines the tag information in the branch prediction table with the longest and matching global branch history as the first tag information, and determines each table entry related to the first tag information as the above-mentioned branch prediction table entry. It should be understood that the branch prediction table entry usually includes the saturated counter value, tag information, and u-bit value of the branch instruction.

[0055] 220: The TAGE branch predictor determines whether there is a saturation counter update value of the branch instruction in the preset IUM module according to the branch prediction table entry.

[0056] In an embodiment of the present application, the TAGE branch predictor inputs a branch prediction table entry to the IUM module via its Provider interface. The Provider interface is an input interface and has a dedicated valid signal that indicates whether the input data is valid. The input to the Provider interface is an unsigned integer that indicates which branch prediction table and corresponding entry the branch instruction matches in the TAGE branch predictor. The IUM module matches the first tag information with its own stored tag information. If a matching tag information (i.e., the second tag information) is found, it indicates that the branch prediction table entry has been matched in the IUM module. The IUM module returns a Resp interface to the TAGE branch predictor. The Resp interface is an output interface and has a dedicated valid signal. If the valid signal is true, it indicates that the branch prediction table entry has been matched in the IUM module. If the valid signal is false, it indicates that the branch prediction table entry has not been matched in the IUM module. The IUM module outputs the stored saturation counter update value and instruction fetch target queue pointer of the branch instruction to the TAGE branch predictor via the Resp interface. The TAGE branch predictor uses the saturation counter update value and instruction fetch target queue pointer to update the data in the branch prediction table entry. The data types of the saturation counter update value and instruction fetch target queue pointer are unsigned integers.

[0057] Exemplarily, the TAGE branch predictor obtains the second tag information of the branch instruction sent by the IUM module through the Resp_tag interface returned by the IUM module. The Resp_tag interface is an output interface. Upon determining a branch prediction table entry hit, the IUM module returns the second tag information to the TAGE branch predictor through the Resp_tag interface. The TAGE branch predictor can store this second tag information. If the branch instruction is mispredicted, this second tag information can be used to determine whether the corresponding entry in the IUM module exists when performing a direction prediction for the branch instruction next time. The data type output by the Resp_tag interface is an unsigned integer.

[0058] 230: When a saturated counter update value exists in the IUM module, the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction.

[0059] In an embodiment of the present application, the TAGE branch predictor uses the saturated counter update value returned by the IUM module to calculate the direction prediction result of the branch instruction, that is, whether the branch instruction jumps. If the branch instruction jumps, the saturated counter value is +1; if the branch instruction does not jump, the saturated counter value is -1.

[0060] Exemplarily, when there is no saturation counter update value in the IUM module, the TAGE branch predictor uses the saturation counter value of the branch instruction stored in the TAGE branch predictor to predict the direction of the branch instruction.

[0061] See Figure 3 , Figure 3 A flow chart of another branch prediction method for branch instructions provided in an embodiment of the present application is applied to an IUM module, wherein the IUM module is a plug-in for a TAGE branch predictor. The method includes steps 310-330:

[0062] 310: The IUM module obtains a branch prediction table entry of the branch instruction to be predicted input by the TAGE branch predictor through a Provider interface. The branch prediction table entry includes the first tag information of the branch instruction.

[0063] In an embodiment of the present application, when predicting the direction of a branch instruction to be predicted, the TAGE branch predictor calculates an index value based on the instruction address of the branch instruction to be predicted and global branch histories of varying lengths. The predictor then uses this index value to locate the branch prediction table entry for the branch instruction. The predictor then sends this branch prediction table entry, which includes the first tag information of the branch instruction, to the IUM module via the IUM module's Provider interface. Exemplarily, the IUM module also includes a Req interface, which is an input interface and has a dedicated valid signal that indicates whether the request data from the TAGE branch predictor is valid.

[0064] 320: The IUM module determines whether second tag information matching the first tag information is stored in the content-addressable memory through the enq_tag interface.

[0065] In this embodiment of the present application, the enq_tag interface is an input interface with a dedicated valid signal. The data type of the enq_tag interface is an unsigned integer. The IUM module obtains the first tag information from the branch prediction table entry through the enq_tag interface and matches the first tag information with multiple tags stored in the content-addressable memory to determine whether the IUM module has second tag information that matches the first tag information.

[0066] 330: When the IUM module stores the second tag information in the content addressable memory, it determines that the branch prediction table entry is hit in the IUM module, and returns the saturated counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction.

[0067] In an embodiment of the present application, when the second tag information is stored in the content-addressable memory, the IUM module returns a Resp interface to the TAGE branch predictor. At this point, the valid signal dedicated to the Resp interface is true, indicating to the TAGE branch predictor that the branch instruction's branch prediction table entry has been hit in the IUM module. The IUM module returns the pre-stored saturation counter update value of the branch instruction and the instruction fetch target queue pointer of the branch instruction-related table entry to the TAGE branch predictor via the Resp interface. The instruction fetch target queue pointer is used to mark the saturation counter update value of the branch instruction and the time the second tag information was enqueued in the IUM module. Upon receiving the saturation counter update value returned by the IUM module, the TAGE branch predictor uses this saturation counter update value to calculate the direction prediction result of the branch instruction.

[0068] For example, the instructions executed by the processor are often executed again in the future, meaning the branch instruction to be predicted may have already been executed previously. When the backend pipeline last executed the branch instruction, if it determined that the branch instruction was mispredicted, it would return a signal indicating that the branch instruction was mispredicted. The IUM module can obtain the signal indicating that the branch instruction was mispredicted in the previous prediction via the enq_data interface. The enq_data interface is an input interface whose data type is an unsigned integer. For example, the IUM module can determine whether the branch instruction was mispredicted using the enq_data interface's dedicated valid signal. If the valid signal is true, it indicates that the branch instruction was mispredicted in the previous prediction. The IUM module receives the saturated counter value and the branch instruction's jump result returned by the backend pipeline when the branch instruction was last executed. The saturated counter value is the saturated counter value in the corresponding table entry of the TAGE branch predictor for the branch instruction when the branch instruction was determined to be mispredicted. The saturated counter value and branch instruction can be input via the FTQ. The IUM module uses the saturation counter value and the branch instruction's jump result to calculate the branch instruction's saturation counter update value. It also uses the same calculation logic as the TAGE branch predictor to calculate the branch instruction's second tag information. The saturation counter update value and second tag information are stored as the branch instruction's entry in the IUM. The IUM also stores the branch instruction's instruction fetch target queue pointer.

[0069] Exemplarily, the main storage structure of the IUM module includes a content-addressable memory (CAM), a register file (RF), and a set of valid registers. The IUM module stores the second tag information in the CAM and the saturation counter update value and instruction fetch target queue pointer in the RF. The second tag information consists of three parts: a prediction of whether it originates from the base table, the first table it originates from, and the entry number of the table it originates from. These three data points are concatenated into an unsigned integer to generate the second tag information. The valid register is used to indicate whether the branch instruction table entry in the IUM is valid.

[0070] Exemplarily, when the second tag information is stored in the content-addressable memory, the IUM module returns the second tag information to the TAGE branch predictor through the Resp_tag interface.

[0071] Exemplarily, when a branch instruction is submitted, the IUM module dequeues the table entries whose enqueue time is earlier than the saturation counter update value and the enqueue time of the second tag information. Branch instruction submission indicates the stage when the branch instruction exits the back-end pipeline. When the branch instruction is submitted, the FTQ sends an update signal to the BPU, and the IUM module obtains a bool value through the deq interface. The bool value is used to instruct the IUM module to perform a dequeue scan. Among them, the deq interface is an input interface. At the same time, the IUM module obtains the instruction fetch target queue pointer corresponding to the branch instruction through the deq_ftq_ptr interface. The IUM module compares the instruction fetch target queue pointer with the instruction fetch target queue pointer of each table entry in the IUM module, and dequeues the table entries whose enqueue time is earlier than the branch instruction. Specifically, the IUM module sets the valid register of the table entries whose enqueue time is earlier than the branch instruction to false, indicating that these table entries are no longer valid. Among them, the deq_ftq_ptr interface is an input interface. As Figure 4 In the table entries shown, ctr1 and tag1 represent the table entries associated with branch instruction 1, and ftq_ptr1 represents the instruction fetch target queue pointer for the table entries associated with branch instruction 1. ctr2 and tag2 represent the table entries associated with branch instruction 2, and ftq_ptr2 represents the instruction fetch target queue pointer for the table entries associated with branch instruction 2. If the entry associated with branch instruction 2 was enqueued earlier than the entry associated with branch instruction 1, the entry associated with branch instruction 2 will be dequeued.

[0072] Exemplarily, if there are multiple entries for a branch instruction in the IUM module, the enqueuing time of the latest entry among the multiple entries is used as the enqueuing time of the branch instruction.

[0073] As can be seen, this application adds an IUM module to the TAGE branch predictor. For the last executed branch instruction, if it is determined that it was mispredicted, the IUM module calculates the saturation counter update value of the branch instruction and saves the saturation counter update value. When the TAGE branch predictor predicts the branch instruction this time, it can simultaneously check whether there is a relevant table entry for the branch instruction in the IUM module. If so, it directly uses the saturation counter update value stored in the IUM module to predict the direction of the branch instruction without waiting for the saturation counter in the TAGE branch predictor to be updated. This improves the efficiency of updating the training data of the TAGE branch predictor. The TAGE branch predictor uses the updated data to predict the direction of the branch instruction, which is conducive to improving the prediction accuracy of the TAGE branch predictor.

[0074] Based on the description of the branch prediction method embodiment of the branch instruction, the present application also provides a branch prediction device for a branch instruction, and the branch prediction device for the branch instruction can be a computer program (including program code) running in a terminal. The branch prediction device for the branch instruction can execute Figure 2 The method shown in this paper is applied to the TAGE branch predictor, see Figure 5 The device includes a first processing unit 510 and a first transceiver unit 520, wherein:

[0075] A first processing unit 510 is configured to determine a branch prediction table entry for a branch instruction based on an instruction address of the branch instruction to be predicted and global branch histories of different lengths;

[0076] The first transceiver unit 520 is configured to determine whether a saturation counter update value of a branch instruction exists in a preset IUM module according to a branch prediction table entry;

[0077] The first processing unit 510 is further configured to, when there is a saturated counter update value in the IUM module, use the saturated counter update value to perform direction prediction on the branch instruction.

[0078] In one possible implementation, in terms of determining whether a saturation counter update value of a branch instruction exists in a preset IUM module according to a branch prediction table entry of the branch instruction, the first transceiver unit 520 is specifically configured to:

[0079] Inputting a branch prediction table entry into the IUM module through the Provider interface of the IUM module, the branch prediction table entry including the first tag information of the branch instruction; the first tag information is used by the IUM module to determine whether the branch prediction table entry is hit in the IUM module;

[0080] Obtain the Resp interface returned by the IUM module. If the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is hit in the IUM module, determine that a saturated counter update value exists in the IUM module. If the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is not hit in the IUM module, determine that no saturated counter update value exists in the IUM module.

[0081] In a possible implementation, the first transceiver unit 520 is further configured to:

[0082] The receiving IUM module returns the saturation counter update value and the corresponding fetch target queue pointer of the saturation counter update value through the Resp interface.

[0083] In a possible implementation, the first transceiver unit 520 is further configured to:

[0084] The second tag information of the branch instruction sent by the IUM module is obtained through the Resp_tag interface returned by the IUM module.

[0085] The present application also provides a branch prediction device for a branch instruction, which can execute Figure 3 The method shown in this figure is used in the IUM module. Figure 6 The device includes a second processing unit 610 and a second transceiver unit 620, wherein:

[0086] The second transceiver unit 620 is configured to obtain a branch prediction table entry of a branch instruction to be predicted input by a TAGE branch predictor through a Provider interface, wherein the branch prediction table entry includes first tag information of the branch instruction;

[0087] The second processing unit 610 is configured to determine whether second tag information matching the first tag information is stored in the content-addressable memory through the enq_tag interface;

[0088] The second processing unit 610 is further used to determine whether the branch prediction table entry is hit in the IUM module when the second tag information is stored in the content addressable memory, and to call the second transceiver unit 620 to return the saturation counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturation counter update value to predict the direction of the branch instruction.

[0089] In a possible implementation, the second processing unit 610 is further configured to:

[0090] receiving a saturation counter value and a jump result of the branch instruction returned by the back-end pipeline when the branch instruction was last executed, wherein the saturation counter value is the saturation counter value of the branch instruction in the corresponding table entry of the TAGE branch predictor when it is determined that the branch instruction has a misprediction;

[0091] Calculate the saturation counter update value of the branch instruction according to the saturation counter value and the jump result;

[0092] The second tag information is calculated using the instruction address of the branch instruction and global branch histories of different lengths, and the saturation counter update value, the second tag information and the corresponding instruction fetch target queue pointer are stored.

[0093] In one possible implementation, the IUM module includes a content-addressable memory and a register file. In terms of storing the saturation counter update value, the second tag information, and the corresponding instruction fetch target queue pointer, the second processing unit 610 is specifically configured to:

[0094] The second tag information is stored in a content addressable memory, and the saturation counter update value and the instruction fetch target queue pointer are stored in a register file.

[0095] In a possible implementation, the second transceiver unit 620 is further configured to:

[0096] In a case where the second tag information is stored in the content addressable memory, the second tag information is returned to the TAGE branch predictor through the Resp_tag interface.

[0097] In a possible implementation, the target queue pointer is used to mark the updated value of the saturation counter and the time when the second tag information is enqueued in the IUM module. The second processing unit 610 is further configured to:

[0098] When the branch instruction is committed, the entry whose enqueue time is earlier than the saturation counter update value and the enqueue time of the second tag information is dequeued.

[0099] According to one embodiment of the present application, Figure 5 or Figure 6 The various modules of the branch prediction device for the branch instruction shown can be individually or entirely combined into one or several other units to form a structure, or one (or some) of the modules can be further divided into multiple functionally smaller units to form a structure, which can achieve the same operation without affecting the realization of the technical effects of the embodiments of the present invention. The above-mentioned units are divided based on logical functions. In actual applications, the functions of one unit can also be implemented by multiple units, or the functions of multiple units can be implemented by one unit. In other embodiments of the present invention, the branch prediction device for the branch instruction can also include other units. In actual applications, these functions can also be implemented with the assistance of other units, and can be implemented by the collaboration of multiple units.

[0100] According to another embodiment of the present application, the program can be executed by running on a general computing device such as a computer including a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM) and other processing elements and storage elements. Figure 2 or Figure 3 A computer program (including program code) for each step involved in the corresponding method shown in Figure 5 or Figure 6 The branch prediction device of the branch instruction shown in the embodiment of the present application is provided, and the branch prediction method of the branch instruction of the branch instruction is implemented. The computer program can be recorded on a computer-readable recording medium, for example, and loaded into the above-mentioned computing device through the computer-readable recording medium and executed therein.

[0101] Based on the description of the above method embodiment and device embodiment, please refer to Figure 7 , Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the electronic device at least includes a processor 710, an input device 720, an output device 730, and a computer storage medium 740. The processor 710, input device 720, output device 730, and computer storage medium 740 in the electronic device may be connected via a bus or other means.

[0102] The computer storage medium 740 may be stored in the memory of the electronic device. The computer storage medium 740 is used to store a computer program, which includes program instructions. The processor 710 is used to execute the program instructions stored in the computer storage medium 740. The processor 710 (or CPU (Central Processing Unit)) is the computing core and control core of the electronic device. It is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to implement a corresponding method flow or corresponding function.

[0103] In one embodiment, the processor 710 of the electronic device provided in the embodiment of the present application can be used to perform branch prediction processing for a series of branch instructions:

[0104] Determine a branch prediction table entry for the branch instruction according to the instruction address of the branch instruction to be predicted and global branch histories of different lengths;

[0105] Determine, based on the branch prediction table entry, whether there is a saturation counter update value for the branch instruction in the preset IUM module;

[0106] In the case where there is a saturated counter update value in the IUM module, the saturated counter update value is used to predict the direction of the branch instruction.

[0107] In another embodiment, the processor 710 determines whether a saturation counter update value of a branch instruction exists in a preset IUM module based on a branch prediction table entry of the branch instruction, including:

[0108] Inputting a branch prediction table entry into the IUM module through the Provider interface of the IUM module, the branch prediction table entry including the first tag information of the branch instruction; the first tag information is used by the IUM module to determine whether the branch prediction table entry is hit in the IUM module;

[0109] Obtain the Resp interface returned by the IUM module. If the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is hit in the IUM module, determine that a saturated counter update value exists in the IUM module. If the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is not hit in the IUM module, determine that no saturated counter update value exists in the IUM module.

[0110] In yet another embodiment, before using the saturation counter update value to predict the direction of the branch instruction, the processor 710 is further configured to execute:

[0111] The receiving IUM module returns the saturation counter update value and the corresponding fetch target queue pointer of the saturation counter update value through the Resp interface.

[0112] In yet another embodiment, before using the saturation counter update value to predict the direction of the branch instruction, the processor 710 is further configured to execute:

[0113] The second tag information of the branch instruction sent by the IUM module is obtained through the Resp_tag interface returned by the IUM module.

[0114] In another embodiment, the processor 710 of the electronic device provided in the embodiment of the present application may also be used to perform branch prediction processing for another series of branch instructions:

[0115] Obtain the branch prediction table entry of the branch instruction to be predicted input by the TAGE branch predictor through the Provider interface, where the branch prediction table entry includes the first tag information of the branch instruction;

[0116] Determine whether the content-addressable memory stores second tag information that matches the first tag information through the enq_tag interface;

[0117] When the second tag information is stored in the content addressable memory, it is determined that the branch prediction table entry is hit in the IUM module, and the saturated counter update value of the branch instruction is returned to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction.

[0118] In another embodiment, before the IUM module obtains the branch prediction table entry of the to-be-predicted branch instruction input by the TAGE branch predictor through the Provider interface, the processor 710 is further configured to execute:

[0119] receiving a saturation counter value and a jump result of the branch instruction returned by the back-end pipeline when the branch instruction was last executed, wherein the saturation counter value is the saturation counter value of the branch instruction in the corresponding table entry of the TAGE branch predictor when it is determined that the branch instruction has a misprediction;

[0120] Calculate the saturation counter update value of the branch instruction according to the saturation counter value and the jump result;

[0121] The second tag information is calculated using the instruction address of the branch instruction and global branch histories of different lengths, and the saturation counter update value, the second tag information and the corresponding instruction fetch target queue pointer are stored.

[0122] In another embodiment, the IUM module includes a content-addressable memory and a register file, and the processor 710 performs the steps of storing the saturation counter update value, the second tag information, and the corresponding instruction fetch target queue pointer, including:

[0123] The IUM module stores the second tag information in the content addressable memory, and stores the saturation counter update value and the instruction fetch target queue pointer in the register file.

[0124] In another embodiment, the processor 710 is further configured to execute:

[0125] In a case where the second tag information is stored in the content addressable memory, the second tag information is returned to the TAGE branch predictor through the Resp_tag interface.

[0126] In another embodiment, the target queue pointer is fetched to mark the updated value of the saturation counter and the time when the second tag information is enqueued in the IUM module, and the processor 710 is further configured to execute:

[0127] When the branch instruction is committed, the entry whose enqueue time is earlier than the saturation counter update value and the enqueue time of the second tag information is dequeued.

[0128] Exemplarily, the electronic device may be a computer, a server, a terminal device, etc. The server may be an independent physical server, or a server cluster or a distributed system. The electronic device may include, but is not limited to, a processor 710, an input device 720, an output device 730, and a computer storage medium 740. It may also include a memory, a power supply, an application client module, etc. The input device 720 may be a keyboard, a touch screen, a radio frequency receiver, etc., and the output device 730 may be a speaker, a display, a radio frequency transmitter, etc. Those skilled in the art will understand that the schematic diagram is merely an example of an electronic device and does not constitute a limitation of the electronic device. It may include more or fewer components than shown in the figure, or combine certain components, or different components.

[0129] It should be noted that since the processor 710 of the electronic device implements the steps in the above-mentioned branch prediction method for branch instructions when executing a computer program, the embodiments of the above-mentioned branch prediction method for branch instructions are all applicable to the electronic device and can achieve the same or similar beneficial effects.

[0130] The embodiment of the present application also provides a computer storage medium (Memory), which is a memory device in an information processing device, an information sending device, or an information receiving device, for storing programs and data. It is understandable that the computer storage medium here can include both the built-in storage medium in the terminal and, of course, the extended storage medium supported by the terminal. The computer storage medium provides a storage space that stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space. These instructions can be one or more computer programs (including program codes). It should be noted that the computer storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage; optionally, it can also be at least one computer storage medium located away from the aforementioned processor. In one embodiment, the processor can load and execute one or more instructions stored in the computer storage medium to implement the corresponding steps in the branch prediction method for the above-mentioned branch instruction.

[0131] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A branch prediction method for a branch instruction, characterized in that: Applied to a TAGE branch predictor, the method comprises: The TAGE branch predictor determines a branch prediction table entry for the branch instruction according to the instruction address of the branch instruction to be predicted and global branch histories of different lengths; The TAGE branch predictor determines whether a saturation counter update value of the branch instruction exists in a preset IUM module according to the branch prediction table entry; the saturation counter update value is calculated by the IUM module when the branch instruction is mispredicted in the previous prediction; When the saturation counter update value exists in the IUM module, the TAGE branch predictor uses the saturation counter update value to predict the direction of the branch instruction.

2. The method according to claim 1, characterized in that The TAGE branch predictor determines, based on a branch prediction table entry of the branch instruction, whether a saturation counter update value of the branch instruction exists in a preset IUM module, including: The TAGE branch predictor inputs the branch prediction table entry to the IUM module through the Provider interface of the IUM module, wherein the branch prediction table entry includes the first tag information of the branch instruction; the first tag information is used by the IUM module to determine whether the branch prediction table entry is hit in the IUM module; The TAGE branch predictor obtains the Resp interface returned by the IUM module. If a valid signal corresponding to the Resp interface indicates that the branch prediction table entry is hit in the IUM module, it is determined that the saturation counter update value exists in the IUM module; if the valid signal corresponding to the Resp interface indicates that the branch prediction table entry is not hit in the IUM module, it is determined that the saturation counter update value does not exist in the IUM module.

3. The method according to claim 2, characterized in that Before using the saturation counter update value to predict the direction of the branch instruction, the method further includes: The TAGE branch predictor receives the saturation counter update value and the instruction fetch target queue pointer corresponding to the saturation counter update value, which are returned by the IUM module through the Resp interface.

4. The method according to any one of claims 1 to 3, characterized in that Before using the saturation counter update value to predict the direction of the branch instruction, the method further includes: The TAGE branch predictor obtains the second tag information of the branch instruction sent by the IUM module through the Resp_tag interface returned by the IUM module.

5. A branch prediction method for a branch instruction, characterized in that: Applied to the IUM module, the method includes: The IUM module obtains a branch prediction table entry of a branch instruction to be predicted input by a TAGE branch predictor through a Provider interface, wherein the branch prediction table entry includes first tag information of the branch instruction; The IUM module determines whether second tag information matching the first tag information is stored in the content addressable memory through the enq_tag interface; When the second tag information is stored in the content-addressable memory, the IUM module determines that the branch prediction table entry is hit in the IUM module, and returns the saturated counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturated counter update value to predict the direction of the branch instruction; the saturated counter update value is calculated by the IUM module when the branch instruction is mispredicted in the previous prediction.

6. The method according to claim 5, characterized in that Before the IUM module obtains the branch prediction table entry of the branch instruction to be predicted input by the TAGE branch predictor through the Provider interface, the method further includes: The IUM module receives a saturated counter value and a jump result of the branch instruction returned by the backend pipeline when the branch instruction was last executed, wherein the saturated counter value is the saturated counter value of the branch instruction in the corresponding table entry of the TAGE branch predictor when it is determined that the branch instruction has a misprediction; The IUM module calculates a saturation counter update value of the branch instruction according to the saturation counter value and the jump result; The IUM module calculates the second tag information using the instruction address of the branch instruction and global branch histories of different lengths, and stores the saturation counter update value, the second tag information and the corresponding instruction fetch target queue pointer.

7. The method according to claim 6, characterized in that The IUM module includes the content addressable memory and the register file, and the storage of the saturation counter update value, the second tag information, and the corresponding instruction fetch target queue pointer includes: The IUM module stores the second tag information in the content addressable memory, and stores the saturation counter update value and the instruction fetch target queue pointer in the register file.

8. The method according to any one of claims 5 to 7, characterized in that: The method further comprises: When the second tag information is stored in the content addressable memory, the IUM module returns the second tag information to the TAGE branch predictor through a Resp_tag interface.

9. The method according to claim 6, characterized in that The fetch target queue pointer is used to mark the updated value of the saturation counter and the time when the second tag information is queued in the IUM module. The method further includes: When the branch instruction is submitted, the IUM module dequeues entries whose enqueue time is earlier than the saturation counter update value and the enqueue time of the second tag information.

10. A branch prediction device for a branch instruction, characterized in that: Applied to a TAGE branch predictor, the device comprises a first processing unit and a first transceiver unit; The first processing unit is configured to determine a branch prediction table entry for a branch instruction to be predicted based on an instruction address of the branch instruction and global branch histories of different lengths; The first transceiver unit is configured to determine, based on the branch prediction table entry, whether a saturation counter update value of the branch instruction exists in a preset IUM module; The saturation counter update value is calculated by the IUM module when the branch instruction is mispredicted in the previous prediction; The first processing unit is further configured to, when the saturated counter update value exists in the IUM module, use the saturated counter update value to perform direction prediction on the branch instruction.

11. A branch prediction device for a branch instruction, characterized in that: Applied to an IUM module, the apparatus includes a second processing unit and a second transceiver unit; The second transceiver unit is configured to obtain a branch prediction table entry of a branch instruction to be predicted input by a TAGE branch predictor through a Provider interface, wherein the branch prediction table entry includes first tag information of the branch instruction; The second processing unit is configured to determine, through an enq_tag interface, whether second tag information matching the first tag information is stored in the content-addressable memory; The second processing unit is further configured to, when the second tag information is stored in the content-addressable memory, determine that the branch prediction table entry is hit in the IUM module, and call the second transceiver unit to return the saturation counter update value of the branch instruction to the TAGE branch predictor through the Resp interface, so that the TAGE branch predictor uses the saturation counter update value to predict the direction of the branch instruction; the saturation counter update value is calculated by the IUM module when the branch instruction is mispredicted in the previous prediction.

12. An electronic device comprising an input device and an output device, characterized in that: Also includes: a processor adapted to implement one or more instructions; as well as, A computer storage medium storing one or more instructions, wherein the one or more instructions are suitable for being loaded by the processor and executing the method according to any one of claims 1 to 4 or 5 to 9.

13. A computer storage medium, characterized in that The computer storage medium stores one or more instructions, and the one or more instructions are suitable for being loaded by a processor and executing the method according to any one of claims 1-4 or 5-9.

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