An interlayer hole modeling method, a single event effect resistance analysis method and device

Abstract

The application discloses a kind of interlayer hole modeling method, single particle effect analysis method and device, the three-dimensional monolithic integrated circuit includes: three-dimensional monolithic integrated circuit upper layer, three-dimensional monolithic integrated circuit lower layer, intermediate layer dielectric between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, interlayer hole is arranged in the intermediate layer dielectric, the method comprises: determining the size of the interlayer hole, the resistivity of the interlayer hole material and the attribute of the intermediate layer dielectric;Based on the size of the interlayer hole and the resistivity of the interlayer hole material, the parasitic resistance model of the interlayer hole is constructed;Based on the size of the interlayer hole and the attribute of the intermediate layer dielectric, the parasitic capacitance model corresponding to the interlayer hole is constructed.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of three-dimensional integrated circuits, and in particular to a method for modeling interlayer holes, a method and device for analyzing single particle effect resistance. BACKGROUND

[0002] Three-dimensional monolithic integration is a technology that can achieve higher integration density while reducing interconnection length and power consumption. With the continuous reduction of transistor size, the importance of three-dimensional monolithic integration technology cannot be ignored.

[0003] In a three-dimensional monolithic integrated circuit, the connection of transistors in each layer is realized through interlayer holes in the circuit. In the prior art, the modeling method of interlayer holes is mainly to model the interlayer holes by analogy to through silicon vias.

[0004] However, the present inventors found at least the following technical problems in the process of implementing the technical solutions of the embodiments of the present application:

[0005] The model established by the existing interlayer hole modeling method is not accurate enough, and there is a large difference compared with the actual situation. SUMMARY

[0006] The embodiments of the present application provide a method for modeling interlayer holes of a three-dimensional monolithic integrated circuit, which solves the technical problem that the interlayer hole modeling method in the prior art is not accurate enough and the model has a large difference compared with the actual situation.

[0007] In a first aspect, the present application provides a method for modeling interlayer holes of a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein the intermediate layer dielectric is provided with an interlayer hole, and the method comprises:

[0008] determining the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric;

[0009] constructing a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material;

[0010] constructing a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric.

[0011] Preferably, constructing the parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material comprises:

[0012] determining a parasitic resistance value of the interlayer hole based on a length, a width, a thickness of the interlayer hole, and a resistivity of the interlayer hole material;

[0013] constructing a parasitic resistance model of the interlayer hole based on the parasitic resistance value.

[0014] Preferably, a plurality of interlayer holes are arranged in the intermediate layer dielectric, and the constructing of the parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric comprises:

[0015] determining a capacitance value of a coupling capacitance based on a length, a width of the interlayer hole, and a width, a dielectric constant of the intermediate layer dielectric, the coupling capacitance being a capacitance generated between two adjacent interlayer holes;

[0016] constructing a coupling capacitance model based on the capacitance value of the coupling capacitance.

[0017] Preferably, the constructing of the parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric comprises:

[0018] determining a capacitance value of an edge capacitance based on a length, a width, a thickness of the interlayer hole, and a dielectric constant of the intermediate layer dielectric, the edge capacitance being a capacitance generated by uneven distribution of electric field;

[0019] constructing an edge capacitance model based on the capacitance value of the edge capacitance.

[0020] Preferably, the intermediate layer dielectric material is silicon dioxide.

[0021] In a second aspect, the present application provides an anti-single-particle effect analysis method based on a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, the intermediate layer dielectric being provided with an interlayer hole, the method comprising:

[0022] determining a preset size of the interlayer hole, a preset resistivity of the interlayer hole, and properties of the intermediate layer dielectric;

[0023] constructing a parasitic resistance model of the interlayer hole based on the preset size of the interlayer hole and the preset resistivity;

[0024] constructing a parasitic capacitance model corresponding to the interlayer hole based on the preset size of the interlayer hole and the properties of the intermediate layer dielectric;

[0025] The parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole are used to analyze the anti-single particle effect of the three-dimensional monolithic integrated circuit to obtain an analysis result.

[0026] In a third aspect, the present application provides an interlayer hole modeling device of a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein the intermediate layer dielectric is provided with an interlayer hole, and the device comprises:

[0027] A determination unit is configured to determine the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric.

[0028] A first construction unit is configured to construct a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material.

[0029] A second construction unit is configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric.

[0030] In a fourth aspect, the present application provides an anti-single particle effect analysis device based on a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein the intermediate layer dielectric is provided with an interlayer hole, and the device comprises:

[0031] A configuration unit is configured to determine a preset size of the interlayer hole, a preset resistivity of the interlayer hole, and properties of the intermediate layer dielectric.

[0032] A first model construction unit is configured to construct a parasitic resistance model of the interlayer hole based on the preset size of the interlayer hole and the preset resistivity.

[0033] A second model construction unit is configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the preset size of the interlayer hole and the properties of the intermediate layer dielectric.

[0034] An analysis unit is configured to analyze the anti-single particle effect of the three-dimensional monolithic integrated circuit based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole to obtain an analysis result.

[0035] In a fifth aspect, the present application provides an interlayer hole modeling device of a three-dimensional monolithic integrated circuit, comprising a processor and a memory:

[0036] The memory is configured to store a program for implementing any one of the methods for modeling an interlayer hole of a three-dimensional monolithic integrated circuit.

[0037] The processor is configured to execute the program stored in the memory.

[0038] In a sixth aspect, the present application provides an anti-single-particle effect analysis device based on a three-dimensional monolithic integrated circuit, comprising a processor and a memory:

[0039] The memory is configured to store a program for implementing an anti-single-particle effect analysis method based on a three-dimensional monolithic integrated circuit.

[0040] The processor is configured to execute the program stored in the memory.

[0041] In a seventh aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the steps of any one of the methods.

[0042] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0043] In the method for modeling an interlayer hole of a three-dimensional monolithic integrated circuit, after the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric are determined, a parasitic resistance model of the interlayer hole is constructed based on the size of the interlayer hole and the resistivity of the interlayer hole material, and in addition, a parasitic capacitance model corresponding to the interlayer hole is constructed based on the size of the interlayer hole and the properties of the intermediate layer dielectric.

[0044] In the above scheme, since the intermediate layer dielectric is considered to be an insulator when modeling the interlayer hole, there is no parasitic capacitance between the interlayer hole and the surrounding material, so that the interlayer hole model established by the present scheme is closer to the actual interlayer hole, and is more accurate and reliable than the model established by the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0046] Figure 1 The method flow chart for modeling an interlayer hole of a three-dimensional monolithic integrated circuit provided by the embodiments of the present application;

[0047] Figure 2A cross-sectional view of an interlayer hole model of a three-dimensional monolithic integrated circuit provided by an embodiment of the present application;

[0048] Figure 3 A top view of an interlayer hole model of a three-dimensional monolithic integrated circuit provided by an embodiment of the present application;

[0049] Figure 4 A schematic diagram of an interlayer hole modeling device of a three-dimensional monolithic integrated circuit provided by an embodiment of the present application;

[0050] Figure 5 A schematic diagram of an anti-single particle effect analysis device based on a three-dimensional monolithic integrated circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] Embodiments of the present application provide an interlayer hole modeling method of a three-dimensional monolithic integrated circuit, which solves the technical problem that the model established by the interlayer hole modeling method in the prior art is not accurate enough and has a large difference compared with the actual situation.

[0052] To solve the above technical problem, the technical solution of embodiments of the present application has the following general idea:

[0053] An interlayer hole modeling method of a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein the intermediate layer dielectric is provided with an interlayer hole, the method comprising: determining the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric; based on the size of the interlayer hole and the resistivity of the interlayer hole material, constructing a parasitic resistance model of the interlayer hole; and based on the size of the interlayer hole and the properties of the intermediate layer dielectric, constructing a parasitic capacitance model corresponding to the interlayer hole.

[0054] In order to better understand the above technical solution, the above technical solution will be described in detail below in combination with the drawings in the specification and specific embodiments.

[0055] First, the term "and / or" appearing in this paper is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents an "or" relationship between the front and rear associated objects.

[0056] The embodiment provides a modeling method of an interlayer hole of a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein the intermediate layer dielectric is provided with an interlayer hole. Figure 1 As shown in the flowchart of the modeling method of the interlayer hole of the three-dimensional monolithic integrated circuit provided in the embodiment of the present specification, the method comprises the following steps:

[0057] Step S1: determining the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric;

[0058] Step S2: constructing a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material;

[0059] Step S3: constructing a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric.

[0060] The modeling method of the interlayer hole of the three-dimensional monolithic integrated circuit provided in the embodiment of the present specification mainly models the interlayer hole in the three-dimensional monolithic integrated circuit, wherein the three-dimensional monolithic integrated circuit comprises a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, an intermediate layer dielectric located between the upper and lower layers, and an interlayer hole provided in the intermediate layer dielectric, wherein the upper and lower layers are both silicon layers, and the intermediate dielectric layer is an insulating layer.

[0061] Through modeling of the interlayer hole in the three-dimensional monolithic integrated circuit, the cutoff frequency and the effect of resisting single event effects can be further evaluated.

[0062] Step S1 is to determine the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric.

[0063] The three-dimensional monolithic integrated circuit is an integrated circuit in which circuit function modules are distributed on different chips, and the chips are bonded to form a three-dimensional stacked structure. The interlayer hole is a via hole for vertical interconnection of transistors in each layer of the three-dimensional monolithic integrated circuit. The interlayer hole can be made of different metal materials, such as copper, cobalt, tungsten, etc. The resistivity of the interlayer hole can be determined by the material and temperature of the interlayer hole. For a cuboid-shaped interlayer hole, the size can be the length, width, and height thereof; for a cylindrical interlayer hole, the size can be the radius of the bottom surface and the height thereof. Taking a cylindrical interlayer hole with a temperature of 20 degrees Celsius and a cobalt material as an example, the resistivity of the interlayer hole can be determined as 6.64 according to the temperature and the material, and the radius and height of the interlayer hole can be determined according to the shape thereof.

[0064] Step S2 is to construct a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material.

[0065] In a specific implementation, the parasitic resistance can be the resistance of a simple metal equivalent to the interlayer hole. The resistance value of the parasitic resistance can be obtained according to the temperature, the size of the interlayer hole, and the resistivity of the interlayer hole material, and then the parasitic resistance model of the interlayer hole is constructed.

[0066] Optionally, the step of constructing the parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material includes: determining a parasitic resistance value of the interlayer hole based on the length, width, and thickness of the interlayer hole and the resistivity of the interlayer hole material; and constructing the parasitic resistance model of the interlayer hole based on the parasitic resistance value.

[0067] In the embodiments of the present specification, the interlayer hole is taken as a cuboid for modeling, and the parasitic resistance of the interlayer hole can be determined by the following formula:

[0068]

[0069] where R is the parasitic resistance, p is the resistivity of the interlayer hole material, L is the length of the interlayer hole, W is the width of the interlayer hole, H is the thickness of the interlayer hole, as shown in FIGS. 1 and 2. MIVS MIVS MIVS MIVS Figure 2 、 Figure 3 After the parasitic resistance is determined, the parasitic resistance equivalent to the interlayer hole is modeled.

[0070] Step S3 is to construct a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the interlayer dielectric.

[0071] The interlayer dielectric is a sandwich layer between the upper and lower two layers of the three-dimensional monolithic integrated circuit, and is generally an insulating material. The properties of the interlayer dielectric are various, such as size, dielectric constant, thermal conductivity, etc. The parasitic capacitance is the coupling capacitance generated between the interlayer holes in the three-dimensional monolithic integrated circuit and / or the edge capacitance generated due to uneven distribution of electric field. According to the size of the interlayer hole and the properties of the interlayer dielectric, the coupling capacitance generated between the interlayer holes in the three-dimensional monolithic integrated circuit and the edge capacitance generated due to uneven distribution of electric field can be constructed.

[0072] ​​​​Optionally, the intermediate layer dielectric has a plurality of interlayer holes, and based on the size of the interlayer holes and the properties of the intermediate layer dielectric, a parasitic capacitance model corresponding to the interlayer holes is constructed, including: based on the length, width of the interlayer holes, and the width, dielectric constant of the intermediate layer dielectric, determining the capacitance value of a coupling capacitance, the coupling capacitance being a capacitance generated between two adjacent interlayer holes; and based on the capacitance value of the coupling capacitance, constructing a coupling capacitance model.

[0073] The coupling capacitance generated between two interlayer holes can be determined by the length, width of the interlayer holes, and the width, dielectric constant of the intermediate layer dielectric, and the specific calculation formula is as follows:

[0074]

[0075] Wherein, C1 is the coupling capacitance, ε ox is the dielectric constant of the intermediate layer dielectric, L MIVS is the length of the interlayer hole, W ox is the width of the intermediate layer dielectric, W MIVS is the width of the interlayer hole, as shown in Figure 2 , Figure 3

[0076] Optionally, based on the size of the interlayer holes and the properties of the intermediate layer dielectric, the parasitic capacitance is determined, further including: based on the dielectric constant of the intermediate layer dielectric, and the length, width, thickness of the interlayer hole, determining an edge capacitance, the edge capacitance being a capacitance generated by uneven distribution of electric field.

[0077] The edge capacitance generated by uneven distribution of electric field can be determined by the length, width, thickness of the interlayer hole, and the dielectric constant of the intermediate layer dielectric, and the specific calculation formula is as follows:

[0078]

[0079] Wherein, C2 is the edge capacitance, W MIV is the width of the interlayer hole, H MIV is the thickness of the interlayer hole, L MIV is the length of the interlayer hole, ε ox is the dielectric constant of the intermediate layer dielectric, as shown in Figure 2 , Figure 3

[0080] Optionally, the intermediate layer dielectric material is silicon dioxide.

[0081] ​​Based on the same inventive concept, the application further provides a method for analyzing anti-single particle effect of a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein an interlayer hole is arranged in the intermediate layer dielectric, and the method comprises:

[0082] determining a preset size of the interlayer hole, a preset resistivity of the interlayer hole, and an attribute of the intermediate layer dielectric;

[0083] constructing a parasitic resistance model of the interlayer hole based on the preset size of the interlayer hole and the preset resistivity;

[0084] constructing a parasitic capacitance model corresponding to the interlayer hole based on the preset size of the interlayer hole and the attribute of the intermediate layer dielectric;

[0085] analyzing the anti-single particle effect of the three-dimensional monolithic integrated circuit based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole, to obtain an analysis result.

[0086] The modeling method of the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole has been described in the above modeling method of the interlayer hole of the three-dimensional monolithic integrated circuit, and will not be elaborated here. For the interlayer hole of the three-dimensional monolithic integrated circuit, when the single particle effect occurs, the parasitic effect of the interlayer hole will have a significant influence on the propagation of the single particle pulse. Based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole, the anti-single particle effect of the three-dimensional monolithic integrated circuit is analyzed, which actually changes the size, layout and material of the interlayer hole, thereby changing the parasitic resistance of the interlayer hole and the parasitic capacitance of the interlayer hole corresponding to the interlayer hole, and then analyzing the weakening effect of the parasitic resistance and the parasitic capacitance of the interlayer hole on the single particle, to obtain an analysis result, which is finally applied to single particle effect reinforcement.

[0087] For example, if there are interlayer holes of cobalt and tungsten materials, the test lengths are 100 nm, 150 nm, 200 nm, and other conditions remain unchanged, by controlling variable method, changing one condition each time to analyze the influence of interlayer hole parasitic resistance and interlayer hole parasitic capacitance on single particle pulse propagation, such as: when the interlayer hole material is tungsten, analyze the weakening effect of interlayer hole parasitic resistance and interlayer hole parasitic capacitance on single particles when the length of the interlayer hole is 100 nm, 150 nm, 200 nm respectively, and obtain the analysis result; then change the interlayer hole material to cobalt, analyze the influence of interlayer hole parasitic resistance and interlayer hole parasitic capacitance on single particle pulse propagation when the length of the interlayer hole is 100 nm, 150 nm, 200 nm respectively, and obtain the analysis result, finally, all analysis results are summarized to obtain the best interlayer hole material and size for anti-single particle effect, which is applied to single particle effect reinforcement.

[0088] The technical solutions in the embodiments of the application have at least the following technical effects or advantages:

[0089] 1. In the embodiments of the application, the parasitic resistance between the interlayer holes, the coupling capacitance between different interlayer holes, and the edge capacitance caused by uneven electric field distribution are considered when modeling the interlayer holes, so that the interlayer hole model established by the scheme is closer to the actual interlayer hole, and is more accurate and reliable than the model established by the prior art.

[0090] 2. In the embodiments of the application, the model obtained by modeling the interlayer holes in the three-dimensional monolithic integrated circuit is used to analyze the influence of the interlayer hole material and size on the single particle effect, and is further used for single particle effect reinforcement, which is more conducive to the research of anti-radiation static random access memory.

[0091] Based on the same inventive concept, as shown in Figure 4 The application provides a kind of interlayer hole modeling device 100 of three-dimensional monolithic integrated circuit, three-dimensional monolithic integrated circuit includes: three-dimensional monolithic integrated circuit upper layer, three-dimensional monolithic integrated circuit lower layer, intermediate layer dielectric between three-dimensional monolithic integrated circuit upper layer and three-dimensional monolithic integrated circuit lower layer, interlayer hole is arranged in the intermediate layer dielectric, and it includes:

[0092] Determining unit 101 is used to determine the size of interlayer hole, the resistivity of interlayer hole material and the attribute of intermediate layer dielectric;

[0093] First construction unit 102 is used to construct the parasitic resistance model of interlayer hole based on the size of interlayer hole and the resistivity of interlayer hole material;

[0094] Second construction unit 103 is used to construct the parasitic capacitance model corresponding to interlayer hole based on the size of interlayer hole and the attribute of intermediate layer dielectric.

[0095] Optionally, the first constructing unit 102 is configured to: determine a parasitic resistance value of the interlayer hole based on a length, a width, a thickness of the interlayer hole and a resistivity of the interlayer hole material; and construct a parasitic resistance model of the interlayer hole based on the parasitic resistance value.

[0096] Optionally, the intermediate layer dielectric is provided with a plurality of interlayer holes, and the second constructing unit is configured to: determine a capacitance value of a coupling capacitance based on a length, a width of the interlayer hole and a width, a dielectric constant of the intermediate layer dielectric, the coupling capacitance being a capacitance generated between two adjacent interlayer holes; and construct a coupling capacitance model based on the capacitance value of the coupling capacitance.

[0097] Optionally, the second constructing unit 103 is configured to: determine a capacitance value of an edge capacitance based on a dielectric constant of the intermediate layer dielectric and a length, a width, a thickness of the interlayer hole, the edge capacitance being a capacitance generated due to uneven distribution of electric field; and construct an edge capacitance model based on the capacitance value of the edge capacitance.

[0098] Regarding the above device, the specific functions of each unit have been described in detail in the embodiments of the method for modeling the interlayer hole of the three-dimensional monolithic integrated circuit provided by the embodiments of the present specification, which will not be described in detail here.

[0099] Based on the same inventive concept, as shown in Figure 5 the present application provides an anti-single particle effect analysis device 200 based on a three-dimensional monolithic integrated circuit, the three-dimensional monolithic integrated circuit comprising: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, the intermediate layer dielectric being provided with an interlayer hole, the device 200 comprising:

[0100] A configuration unit 201 is configured to determine a preset size of the interlayer hole, a preset resistivity of the interlayer hole and properties of the intermediate layer dielectric.

[0101] A first model constructing unit 202 is configured to construct a parasitic resistance model of the interlayer hole based on the preset size and the preset resistivity of the interlayer hole.

[0102] A second model constructing unit 203 is configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the preset size of the interlayer hole and the properties of the intermediate layer dielectric.

[0103] An analysis unit 204 is configured to analyze the anti-single particle effect of the three-dimensional monolithic integrated circuit based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole, to obtain an analysis result.

[0104] ​​​​​​​​​As to the above device, the specific functions of each unit have been described in detail in the embodiments of the method for analyzing anti-single particle effect based on three-dimensional monolithic integrated circuit provided by the embodiments of the present application, and thus will not be described in detail here.

[0105] Based on the same inventive concept, the present application provides a device for modeling interlayer holes of three-dimensional monolithic integrated circuit, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for modeling interlayer holes of three-dimensional monolithic integrated circuit as described above when executing the program.

[0106] Based on the same inventive concept, the present application provides a device for analyzing anti-single particle effect based on three-dimensional monolithic integrated circuit, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for analyzing anti-single particle effect based on three-dimensional monolithic integrated circuit as described above when executing the program.

[0107] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium having a computer program stored thereon, wherein the program implements the steps of any of the method for modeling interlayer holes of three-dimensional monolithic integrated circuit and the method for analyzing anti-single particle effect based on three-dimensional monolithic integrated circuit as described above when executed by a processor.

[0108] Since the electronic device introduced in the present embodiment is the electronic device used to implement the method for information processing in the present application, the specific implementation of the electronic device and its various forms can be understood by those skilled in the art based on the method for information processing introduced in the present application, and thus the implementation of the method in the present application by the electronic device will not be described in detail here. As long as the electronic device used to implement the method for information processing in the present application is implemented by those skilled in the art, it belongs to the scope of the present application.

[0109] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0110] The present application is described in reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0111] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0113] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those of skill in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, the attached claims are intended to embrace all such variations and modifications as fall within the scope of the present application.

[0114] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method of modeling interlayer via in a three-dimensional monolithic integrated circuit, the method comprising: The three-dimensional monolithic integrated circuit comprises: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein an interlayer hole is arranged in the intermediate layer dielectric, and the method comprises: ​ determining the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the intermediate layer dielectric; based on the size of the interlayer hole and the resistivity of the interlayer hole material, a parasitic resistance model of the interlayer hole is constructed; based on the size of the interlayer hole and the properties of the intermediate layer dielectric, a parasitic capacitance model corresponding to the interlayer hole is constructed, including: based on the length, width of the interlayer hole, and the width, dielectric constant of the intermediate layer dielectric, the capacitance value of a coupling capacitance is determined, the coupling capacitance is the capacitance between two adjacent interlayer holes; based on the capacitance value of the coupling capacitance, a coupling capacitance model is constructed; and / or based on the size of the interlayer hole and the properties of the intermediate layer dielectric, a parasitic capacitance model corresponding to the interlayer hole is constructed, including: based on the dielectric constant of the intermediate layer dielectric, and the length, width, thickness of the interlayer hole, the capacitance value of an edge capacitance is determined, the edge capacitance is the capacitance generated by uneven electric field distribution; based on the capacitance value of the edge capacitance, an edge capacitance model is constructed.

2. The method of claim 1, wherein, based on the size of the interlayer hole and the resistivity of the interlayer hole material, a parasitic resistance model of the interlayer hole is constructed, including: based on the length, width, thickness of the interlayer hole, and the resistivity of the interlayer hole material, the parasitic resistance value of the interlayer hole is determined; based on the parasitic resistance value, a parasitic resistance model of the interlayer hole is constructed.

3. The method of claim 1, wherein the method is performed by a computer system. The intermediate layer dielectric material is silicon dioxide.

4. A method for analyzing the resistance to single event effects based on a three-dimensional monolithic integrated circuit, characterized in that, The three-dimensional monolithic integrated circuit comprises: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an intermediate layer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, wherein an interlayer hole is arranged in the intermediate layer dielectric, and the method comprises: determining the preset size of the interlayer hole, the preset resistivity of the interlayer hole, and the properties of the intermediate layer dielectric; based on the preset size of the interlayer hole and the preset resistivity, a parasitic resistance model of the interlayer hole is constructed; based on the preset size of the interlayer hole and the properties of the intermediate layer dielectric, a parasitic capacitance model corresponding to the interlayer hole is constructed; based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole, the single event effect resistance of the three-dimensional monolithic integrated circuit is analyzed to obtain an analysis result; wherein the construction process of the parasitic capacitance model comprises: based on the length, width of the interlayer hole, and the width, dielectric constant of the intermediate layer dielectric, the capacitance value of a coupling capacitance is determined, the coupling capacitance is the capacitance between two adjacent interlayer holes; based on the capacitance value of the coupling capacitance, a coupling capacitance model is constructed; and / or The parasitic capacitance model corresponding to the interlayer hole is constructed based on the size of the interlayer hole and the properties of the interlayer dielectric, including: determining the capacitance value of an edge capacitance based on the dielectric constant of the interlayer dielectric and the length, width and thickness of the interlayer hole, the edge capacitance being a capacitance generated by uneven electric field distribution; and constructing an edge capacitance model based on the capacitance value of the edge capacitance.

5. A device for modeling interlayer holes in a three-dimensional monolithic integrated circuit, characterized in that, The three-dimensional monolithic integrated circuit includes: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an interlayer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, the interlayer dielectric being provided with an interlayer hole, and the device includes: A determination unit is configured to determine the size of the interlayer hole, the resistivity of the interlayer hole material, and the properties of the interlayer dielectric. A first construction unit is configured to construct a parasitic resistance model of the interlayer hole based on the size of the interlayer hole and the resistivity of the interlayer hole material. A second construction unit is configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the interlayer dielectric. The second construction unit is configured to determine the capacitance value of a coupling capacitance based on the length and width of the interlayer hole and the width and dielectric constant of the interlayer dielectric, the coupling capacitance being a capacitance generated between two adjacent interlayer holes; and construct a coupling capacitance model based on the capacitance value of the coupling capacitance. The second construction unit is further configured to construct the parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the interlayer dielectric, including: determining the capacitance value of an edge capacitance based on the dielectric constant of the interlayer dielectric and the length, width and thickness of the interlayer hole, the edge capacitance being a capacitance generated by uneven electric field distribution; and constructing an edge capacitance model based on the capacitance value of the edge capacitance.

6. A three-dimensional monolithic integrated circuit-based anti-single event effect analysis device, characterized by, The three-dimensional monolithic integrated circuit includes: a three-dimensional monolithic integrated circuit upper layer, a three-dimensional monolithic integrated circuit lower layer, and an interlayer dielectric located between the three-dimensional monolithic integrated circuit upper layer and the three-dimensional monolithic integrated circuit lower layer, the interlayer dielectric being provided with an interlayer hole, and the device includes: A configuration unit is configured to determine a preset size of the interlayer hole, a preset resistivity of the interlayer hole, and properties of the interlayer dielectric. A first model construction unit is configured to construct a parasitic resistance model of the interlayer hole based on the preset size of the interlayer hole and the preset resistivity. A second model construction unit is configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the preset size of the interlayer hole and the properties of the interlayer dielectric. An analysis unit is configured to analyze the anti-single event effect of the three-dimensional monolithic integrated circuit based on the parasitic resistance model of the interlayer hole and the parasitic capacitance model corresponding to the interlayer hole, and obtain an analysis result. The second model construction unit is configured to determine a capacitance value of a coupling capacitance based on the length and width of the interlayer hole and the width and dielectric constant of the intermediate layer dielectric, the coupling capacitance being a capacitance generated between two adjacent interlayer holes; construct a coupling capacitance model based on the capacitance value of the coupling capacitance; and / or The second model construction unit is further configured to construct a parasitic capacitance model corresponding to the interlayer hole based on the size of the interlayer hole and the properties of the intermediate layer dielectric, including: determining a capacitance value of an edge capacitance based on the dielectric constant of the intermediate layer dielectric and the length, width and thickness of the interlayer hole, the edge capacitance being a capacitance generated due to uneven electric field distribution; and constructing an edge capacitance model based on the capacitance value of the edge capacitance.

7. A device for modeling interlayer holes in a three-dimensional monolithic integrated circuit, characterized in that, comprising a processor and a memory: The memory is configured to store a program for executing the method of any one of claims 1-3; The processor is configured to execute the program stored in the memory.

8. A three-dimensional monolithic integrated circuit-based anti-single event effect analysis device, characterized by, comprising a processor and a memory: The memory is configured to store a program for executing the method of claim 4; The processor is configured to execute the program stored in the memory.

Images