FPGA hardware acceleration method for CCS model back-substitution solution in static timing analysis

Abstract

The present invention discloses an FPGA hardware acceleration method for back-substitution and solving of CCS models in static timing analysis. The present invention implements a parallel architecture of matrix forward and backward back-substitution processes on FPGA, and the core part is to calculate the PE array. Compared with the traditional CPU, the architecture can reduce the running time of CCS model solving in the timing analysis process and improve the performance of the timing analysis tool. The present invention first transmits the matrix data solved by the timing analysis tool to the inside of FPAG. The PS-side ARM general processor on the FPGA opens the DMA channel to move the matrix data from DRAM to the on-chip memory BRAM by column, and at the same time controls the data transmission, allocates BRAM data and configures PE, and forwards the data in column order for back-substitution and solving. Similarly, the backward back-substitution process adopts a pipeline method, and multiplexes modules such as PE array, subtractor and trigger. The calculation result will be written back to DRAM and then transmitted to the PC.

Description

Technical Field

[0001] The present invention relates to an FPGA hardware acceleration method for back-generation solution of a composite current source (CCS) model in static timing analysis, and belongs to the field of integrated circuit design automation (Electronic Design Automation, EDA) and high-efficiency integrated circuit design. Background Art

[0002] The semiconductor industry is facing two major challenges: a) the scale of circuit design is getting larger and larger; b) the constraints and goals of circuit design are becoming more complex. In order to meet the constraints of large-scale circuit design, the amount of calculations in the design process has increased significantly. For example, when designing the physical wiring of the circuit, calculating the interconnect delay is very time-consuming. For this reason, the industry has been looking for ways to reduce the time and workload of modern integrated circuit design.

[0003] Generally, designers use timing analysis tools to view the internal logic and routing delay of the designed circuit, verify whether the circuit meets the design constraints, and analyze the circuit timing convergence. For a long time, the nonlinear delay model (NLDM) has been widely used in timing analysis to abstractly characterize the delay and output conversion time characteristics of circuit units. As the very large scale integration (VLSI) technology enters the deep submicron region, the behavior of circuit standard units becomes more nonlinear, and the advancement of technology requires more accurate circuit unit models. The traditional nonlinear delay model (NLDM) cannot accurately model many new effects such as high interconnect impedance, Miller effect, dynamic IR-drop, multi-threshold voltage, dynamic voltage and frequency conversion. The emergence of new current source models such as the composite current source (CCS) model and the effective current source model (ECSM) has significantly improved the accuracy of driver and receiver modeling.

[0004] In the CCS model, the receiver model is a two-dimensional lookup table based on the input transmission time and load capacitance. However, due to the existence of the Miller effect, the receiver model uses a dual-capacitor model, where the voltage is C1 before the conversion threshold voltage point, and the capacitance value becomes C2 if the voltage is greater than the threshold voltage; the driver model is also changed from using a simple Delay two-dimensional lookup table to using current waveform modeling, which relies on numerical integration to solve algebraic equations to obtain the voltage waveform and calculate the delay.

[0005] The CCS model solution process is as follows Figure 1First, the current waveform and capacitance value are obtained by looking up the CCS model receiver model and driver model, and the matrix equation is established using the improved node method:

[0006] Ax=b

[0007] Among them, the A matrix is ​​determined by the connection relationship between circuit elements, independent voltage sources and independent current sources; the x matrix contains the unknown voltage and current values ​​to be solved; the b matrix contains independent voltage sources and current sources. Since the matrix A only changes once when the node voltage value passes the conversion threshold during the CCS model solution process, the direct solution method is usually used to decompose the matrix and then back-solve it. The commonly used matrix decomposition method is LDU decomposition. Among them, L is a lower triangular matrix with a diagonal of 1; D is a diagonal matrix; U is an upper triangular matrix with a diagonal of 1. If LDU decomposition is used to solve the matrix, the calculation is divided into the following steps:

[0008] LDU x=b (A=LDU)

[0009] Integrate the current to find the voltage waveform, that is, perform back-and-forth substitution at a specific time step to solve for x;

[0010] Ly=b forward back substitution

[0011] Ux=y Backward Substitution

[0012] After solving the voltage waveform, it is necessary to determine whether the node voltage reaches the conversion voltage threshold point. If the voltage is greater than the threshold point, the capacitance value changes to C2, and the capacitance value needs to be re-looked up in the table and the A matrix is ​​updated; similarly, if the node voltage is less than the threshold point, the capacitance value C1 and the matrix A remain unchanged, and the next time integration is continued, that is, the forward and backward back-substitution solution is repeated until the simulation ends. However, during the timing analysis process, the forward and backward back-substitution calculation of the CCS model matrix is ​​time-consuming, and the matrix back-substitution time is much longer than the matrix decomposition time, resulting in a long running time and low efficiency of the timing analysis tool. Summary of the invention

[0013] The present invention is an FPGA hardware acceleration method for CCS model back-substitution in static timing analysis. In order to solve the problem of fast back-substitution of CCS model matrix in static timing analysis, the present invention implements a hardware architecture for accelerated calculation based on FPGA. The use of this architecture can reduce the time of CCS model solution and improve the performance of timing analysis tools.

[0014] The FPGA hardware acceleration method for back-substitution solution of CCS model in static timing analysis of the present invention comprises the following steps:

[0015] Step 1, send the CCS model decomposition matrix to the FPGA development board;

[0016] When the timing analysis tool completes the LDU decomposition, the PC transfers the matrix after the CCS model decomposition to the FPGA development board and stores it in the Off Chip DRAM of the FPGA development board;

[0017] A=LDU

[0018] Back-substitution solution:

[0019] Lz=b,Dr=z&Ux=r

[0020] Step 2: Move the matrix data to BRAM to control PE operation;

[0021] The PS-side ARM general-purpose processor on the FPGA opens the DMA channel to move the matrix data column by column to the on-chip memory BRAM;

[0022] Step 3: construct a PE processing unit array for periodic calculation. In the jth calculation cycle, input the jth row of the L matrix corresponding to z into the PE processing unit array. j Related items, z j , and b j ; The z j The relevant term is l (j+1)j ,l (j+2)j ,…,l nj , output z in the jth calculation cycle j ,z j+1 ,…,z n ;

[0023] Step 4: Use FSM to control the data flow and schedule the required calculation order. For the jth calculation cycle, the FSM controls the output z j To the divider Div, according to the formula r n =z n / d n , calculate r j , and complete the forward iteration.

[0024] Step 5. Similarly, the PE processing unit array is reused during backward iteration. The calculation results will be written back to the Off Chip DRAM and then transmitted to the PC for use by the timing analysis tool, thus completing the forward and backward iteration solution.

[0025] The method of the present invention adopts a direct solution method to solve the CCS model matrix. The matrix remains unchanged within a certain range and only needs to be decomposed once and back-substituted multiple times to improve the calculation efficiency.

[0026] Furthermore, the PE processing unit array includes a plurality of PE processing units, each of which includes a multiplier, an adder, and a subtractor. In j calculation cycles, the PE processing unit takes out the jth row of the lower triangular matrix L corresponding to z in row order.j The relevant item data is multiplied by z j Multiply and output the product to the adder for accumulation, update the data z in the adder j+1 ,z j+2 ,…,z n , and z j+1 Input to the subtractor and b j Make a difference and update z j+1 =b j -z j+1 .

[0027] Furthermore, the PE processing unit also includes FIFO_2, which is introduced to solve the problem of solving matrices of any size when FPGA resources are insufficient. When the matrix dimension is greater than the number of PEs, the calculated z value is temporarily stored in FIFO_2. The depth of FIFO_2 depends on the matrix dimension and the number of PEs.

[0028] Furthermore, the first calculation cycle will be completed within a clock cycles, where the size of a depends on the delay time of the multiplier. If the FPGA resources are insufficient and the constructed PE processing unit cannot meet the matrix calculation requirements, it will take multiple rounds of PE calculations to complete the first step of matrix calculation.

[0029] The matrix decomposition method used in this method is LDU decomposition, and the matrix L is a unit lower triangular matrix. There is no dependency between the previous and next data when back-substitution is performed, and efficient parallelization can be achieved.

[0030] Beneficial effects: Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0031] This method is universal for accelerating CCS model matrix calculation. By utilizing the reconfigurable characteristics of FPGA, the multiple forward and backward iterations in CCS model solving are simplified, the CCS model timing analysis solving time is shortened, the performance of CCS timing model solving is improved, and guidance is provided to designers.

[0032] (1) In order to reduce the time of back-substitution in the CCS model solution process, the matrix data to be solved can be transferred to the FPGA, and multiple PE arrays can be used in the FPGA to calculate the matrix back-substitution. Compared with the traditional CPU, this method can reduce the running time of this process.

[0033] (2) After LDU decomposition, L is a lower triangular matrix, which does not rely on forward and backward data when back-substituting, thus improving PE utilization and achieving efficient parallelization. At the same time, the introduction of FIFO in this method adapts to matrices of different dimensions appearing in the circuit, and is universal for solving CCS model timing analysis.

[0034] (3) The solver proposed in the present invention can also be used in scenarios such as power grid simulation.

[0035] This FPGA hardware acceleration method for solving the CCS model in static timing analysis is used to further optimize the data flow in data calculation. The subtractor and divider operations are calculated and reused in a pipeline manner to improve resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flow chart of solving the CCS model matrix of the present invention.

[0037] Figure 2 It is a diagram of the order of solving the triangular matrix of the present invention.

[0038] Figure 3 It is a forward and backward iteration sequence diagram of the triangular matrix of the present invention.

[0039] Figure 4 This is a parallel structure diagram of the invention for quickly solving the CCS model matrix

[0040] Figure 5 It is a diagram of the PE array structure of the present invention. DETAILED DESCRIPTION

[0041] When solving the triangular matrix in the CCS model, it is necessary to rely on forward and backward data. In the worst case, for example, if the matrix is ​​a fully dense matrix, any solution component needs to wait for its previous component to be solved. The waiting process wastes circuit resources and prolongs the solution time. The present invention implements a solution acceleration of matrix back-substitution of any scale on FPGA, which is used to solve the matrix equation Ax=b in the problem of solving the CCS model in timing analysis. Where A is a symmetric positive definite matrix, the Cholesky matrix LDU decomposition method can be used to obtain

[0042] A=LDU

[0043] Back-substitution solution:

[0044] Lz=b,Dr=z&Ux=r

[0045] Figure 2 The computational flow of the architecture is shown. Figure 3 This illustrates the pipeline computation sequence for solving linear trigonometric equations in parallel, which is performed column by column.

[0046] Step 1, send the CCS model decomposition matrix to the FPGA development board;

[0047] When the timing analysis tool completes the LDU decomposition, the PC transfers the matrix after the CCS model decomposition to the FPGA development board. The PC and FPGA are transmitted via PCIE or Ethernet high-speed communication protocol. The matrix data received from the PC is first stored in the Off Chip DRAM of the FPGA development board.

[0048] Step 2: Move the matrix data to BRAM to control PE operation;

[0049] The PS-side ARM general-purpose processor on the FPGA opens the DMA channel to move the matrix data to the on-chip memory BRAM by column, and controls data transmission, allocates BRAM data, and configures PE.

[0050] Step 3: Build a PE processing unit array for periodic calculations.

[0051] The PE processing unit array is used to calculate z n , multiple PE processing units built in FPGA perform periodic parallel calculations. In the jth calculation cycle, the jth row of the L matrix corresponding to z is input to the PE processing unit array. j Related items, z j , and b j ; The z j The relevant term is l (j+1)j ,l (j+2)j ,…,l nj , the PE processing unit array outputs the calculation result z j ,z j+1 ,…,z n , the data flow of the triangular matrix linear solver is controlled by FSM and the required calculation order is scheduled, and then the division is calculated in a pipeline manner to obtain r1, r2, r 3, …,r n For the jth computation cycle, the FSM controls the output z j To the divider Div, according to the formula r n =z n / d n , calculate r j And so on, the forward back iteration process is performed in parallel.

[0052] like Figure 5 As shown, the PE processing unit includes a multiplier, an adder, a FIFO_2 and a subtractor. When calculating, the PE processing unit takes out the jth row of the lower triangular matrix L in row order and the z j The relevant item data is multiplied by z j Multiply and output the product to the adder for accumulation, and update the data z in the adder through FIFO_2 j+1,z j+2, …z n , and input zj+1 into the subtractor and add it to b j Make a difference and update z j+1 =b j -z j+1 .

[0053] The following is an example of the first calculation cycle and the second calculation cycle;

[0054] In the first calculation cycle, the items related to z1 in the first row of the L matrix, z1, and b1 are input to the PE processing unit array, where the items related to z1 are l 21, l 31 ,l 51, l 41 ,…,l n1 In the multiplier of the PE unit, the data related to z1 in the first row is multiplied by z1 to obtain l 21 z1, l 31 z1,l 41 z 1, l 41 z1,…,l n1 z1, respectively denoted as z2, z 3, z 4, …,z n ; and input z2 into the subtractor and b j Make a difference and update z2=b1-z2=b1-l 21 For the first calculation cycle, the FSM control output z1=b1.

[0055] In the second calculation cycle, the items related to z2, z2, and b2 in the second row of the L matrix are input to the PE processing unit array, where the items related to z2 are l 32 ,l 42, l 52 ,…,l n2 In the multiplier of the PE unit, the data related to z2 in the second row is multiplied by z2 to obtain l 32 z2,l 42 z 2, l 42 z2,…,l n2 z2, respectively denoted as z 3, z 4, …,z n ; Input z2 into the subtractor and subtract it from b2, update z3 = b2 – z3 = b2 – l 31 z2 For the second computation cycle, the FSM controls output z2.

[0056] The first calculation cycle will be completed within a clock cycles, where the size of a depends on the delay time of the multiplier. If the FPGA resources are insufficient and the constructed PE processing unit cannot meet the matrix calculation requirements, it will take multiple rounds of PE calculations to complete the first step of matrix calculation. Since there is no dependency on forward and backward data during calculation, pipelines can be inserted during the calculation process to shorten the delay and improve calculation efficiency.

[0057] Step 4: Similarly, the PE processing unit array is reused during backward iteration, and the calculation results will be written back to the Off Chip DRAM and then transmitted to the PC for use by the timing analysis tool, thus completing the forward and backward iteration solution.

[0058] A separate divider is used outside the PE array to calculate r. A divider is reused for different calculation cycles to save resources and improve utilization. Using the LDU matrix decomposition method to perform triangular back-substitution can eliminate data dependencies and improve computational parallelism. The overall framework is as follows: Figure 4 As shown in the figure, the forward and backward back generation steps are similar, and the PE array can be reused. The final calculation results will be written back to the Off Chip DRAM and transferred to the PC for use by the timing analysis tool, thus completing the forward and backward back generation solution.

Claims

1. FPGA hardware acceleration method for CCS model back generation in static timing analysis, characterized in that: The steps include: Step 1, send the CCS model decomposition matrix to the FPGA development board; The matrix after decomposition of the CCS model is transferred to the FPGA development board and stored in the Off Chip DRAM of the FPGA development board; A=LDU Back-substitution solution: Lz=b,Dr=z&Ux=r Step 2: Move the matrix data to BRAM to control PE operation; The PS-side ARM general-purpose processor on the FPGA opens the DMA channel to move the matrix data column by column to the on-chip memory BRAM; Step 3: construct a PE processing unit array for periodic calculation. In the jth calculation cycle, input the jth row of the L matrix corresponding to z into the PE processing unit array. j Related items, z j , and b j ; The z j The relevant term is l (j+1)j ,l (j+2)j ,…,l nj , output z in the jth calculation cycle j ,z j+1 ,…,z n ; Step 4: Control the data flow and schedule the calculation order through FSM. For the jth calculation cycle, FSM controls the output z j To the divider Div, according to the formula r n =z n / d n , calculate r j , and complete the forward iteration; Step 5. Similarly, the PE processing unit array is reused during backward iteration. The calculation results will be written back to the Off Chip DRAM and then transmitted to the PC for use by the timing analysis tool, thus completing the forward and backward iteration solution.

2. The FPGA hardware acceleration method for back-substitution solution of CCS model in static timing analysis according to claim 1 is characterized in that: The PE processing unit includes a multiplier, an adder, and a subtractor. In j calculation cycles, the PE processing unit takes out the jth row of the lower triangular matrix L in row order. j The relevant item data is multiplied by z j Multiply and output the product to the adder for accumulation, update the data z in the adder j+1 ,z j+2 ,…,z n , and z j+1 Input to the subtractor and b j Make a difference and update z j+1 =b j -z j+1 .

3. The FPGA hardware acceleration method for back-substitution solution of CCS model in static timing analysis according to claim 2 is characterized in that: The PE processing unit also includes FIFO_2. When the matrix dimension is greater than the number of PE units, the calculated z value is temporarily stored in FIFO_2. The depth of FIFO_2 depends on the matrix dimension and the number of PE units.

4. The FPGA hardware acceleration method for back-substitution solution of CCS model in static timing analysis according to claim 1 is characterized in that: The first calculation cycle will be completed within a clock cycles, and the size of a depends on the delay time of the multiplier. If the FPGA resources are insufficient and the constructed PE processing unit cannot meet the matrix calculation requirements, it will be necessary to wait for multiple rounds of PE calculations to complete the first step of matrix calculation.

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