Static time sequence analysis method, device and equipment in FPGA (Field Programmable Gate Array) circuit and medium

Abstract

The embodiment of the invention discloses a static time sequence analysis method, device and equipment in an FPGA (Field Programmable Gate Array) circuit and a medium. The method comprises the following steps: acquiring a netlist in FPGA circuit design; according to the netlist, when it is determined that the current circuit device meets a preset black box processing condition, the current circuit device serves as a black box device; obtaining a port connection file of the black box device, and determining a connection relationship of the black box device according to the port connection file; mapping the connection relation to a target connection type according to an input interface type and an output interface type in the connection relation; obtaining a link transmission delay corresponding to the target connection type, and determining a path delay corresponding to each time sequence path according to the link transmission delay; and determining whether the FPGA circuit design meets expected working requirements or not according to the path delays. By simplifying a larger design device in the FPGA circuit into a black box for processing, static time sequence analysis can be simplified, the purpose of rapid time sequence analysis is achieved, and excessive memory occupation is avoided.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and in particular to a static timing analysis method, device, equipment and medium in an FPGA circuit. Background Art

[0002] In integrated circuit design, timing checks are required at each stage to ensure that the designed circuit meets the predetermined timing requirements. Static timing analysis (STA) is a method for estimating the expected timing of a circuit without performing simulation.

[0003] In the prior art, static timing analysis of Field-Programmable Gate Array (FPGA) circuits usually involves a complete analysis of all devices in the FPGA circuit. However, when encountering larger circuit devices, the paths of the larger circuit devices are complex, which results in a longer time required for comprehensive analysis, affecting the timing analysis rate.

[0004] Therefore, simplifying the timing analysis of larger devices is an urgent problem to be solved. Summary of the invention

[0005] The present invention provides a static timing analysis method, device, equipment and medium in an FPGA circuit to simplify the static timing analysis of larger design devices in the FPGA circuit, achieve the purpose of fast timing analysis, and avoid excessive memory usage.

[0006] According to one aspect of the present invention, a static timing analysis method in an FPGA circuit is provided, the method comprising:

[0007] Get the netlist in FPGA circuit design;

[0008] When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device;

[0009] Acquire a port connection file of a black box device, and determine a connection relationship of the black box device according to the port connection file;

[0010] Mapping the connection relationship to a target connection type according to an input interface type and an output interface type in the connection relationship;

[0011] Acquire a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay;

[0012] Based on the delays of each path, determine whether the FPGA circuit design meets the expected working requirements.

[0013] According to another aspect of the present invention, a static timing analysis device in an FPGA circuit is provided, the device comprising:

[0014] A netlist acquisition module is used to acquire the netlist in FPGA circuit design;

[0015] A black box device determination module, configured to determine, based on the netlist, that when a current circuit device satisfies a preset black box processing condition, use the current circuit device as a black box device;

[0016] A connection relationship determination module, used to obtain a port connection file of a black box device, and determine a connection relationship of the black box device according to the port connection file;

[0017] A target connection type determination module, used for mapping the connection relationship to a target connection type according to the input interface type and the output interface type in the connection relationship;

[0018] A path delay determination module, used to obtain a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay;

[0019] The circuit design detection module is used to determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path.

[0020] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0021] at least one processor; and

[0022] a memory communicatively connected to the at least one processor; wherein,

[0023] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the static timing analysis method in the FPGA circuit described in any embodiment of the present invention.

[0024] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the static timing analysis method in an FPGA circuit described in any embodiment of the present invention when executed.

[0025] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the static timing analysis method in an FPGA circuit described in any embodiment of the present invention is implemented.

[0026] The technical solution of the embodiment of the present invention is to obtain a netlist in an FPGA circuit design; determine, based on the netlist, when the current circuit device meets a preset black box processing condition, use the current circuit device as a black box device; obtain a port connection file of the black box device, and determine the connection relationship of the black box device based on the port connection file; map the connection relationship to a target connection type based on an input interface type and an output interface type in the connection relationship; obtain a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path based on the link transmission delay; determine, based on each path delay, whether the FPGA circuit design meets the expected working requirements, thereby solving the problem of large consumption of timing analysis resources for larger circuit devices encountered during static timing analysis of FPGA circuits, and simplifying larger design devices in FPGA circuits into black boxes for processing, thereby simplifying static timing analysis, achieving the purpose of fast timing analysis, and avoiding excessive memory usage.

[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a flow chart of a static timing analysis method in an FPGA circuit provided in Embodiment 1 of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of a cross-FPGA circuit provided according to Embodiment 1 of the present invention;

[0031] Figure 3 is a flow chart of a static timing analysis method in an FPGA circuit provided according to a second embodiment of the present invention;

[0032] Figure 4 is a flowchart of a static timing analysis method in an FPGA circuit provided by Embodiment 3 of the present invention;

[0033] Figure 5 is a schematic diagram of a black box device processing provided according to Embodiment 3 of the present invention;

[0034] Figure 6is a schematic diagram of the structure of a static timing analysis device in an FPGA circuit provided according to a fourth embodiment of the present invention;

[0035] Figure 7 It is a structural schematic diagram of an electronic device for implementing the static timing analysis method in the FPGA circuit of an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Embodiment 1

[0039] Figure 1 This is a flowchart of a static timing analysis method in an FPGA circuit provided according to the first embodiment of the present invention. This embodiment is applicable to static timing analysis when there are large circuit devices in the FPGA circuit. The method can be performed by a static timing analysis device in the FPGA circuit. The static timing analysis device in the FPGA circuit can be implemented in the form of hardware and / or software. The static timing analysis device in the FPGA circuit can be configured in an electronic device such as a computer. Figure 1 As shown, the method includes:

[0040] Step 110: Obtain a netlist in the FPGA circuit design.

[0041] In FPGA circuit design, the netlist is a crucial intermediate file that contains the logic units and connection information in the FPGA schematic.

[0042] Step 120: When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device.

[0043] In an embodiment of the present invention, there may be multiple situations for determining whether the current circuit device meets the preset black box processing conditions. Exemplarily, the preset black box processing condition may be to determine that the current circuit device is a larger circuit device. For example, when it is determined according to the netlist that there are multiple complex input-output connection relationships in the current circuit device, it may be determined that the current circuit device meets the preset black box processing conditions. For another example, the resource consumption of the device in the FPGA circuit may be analyzed according to the connection relationship in the netlist. If the resource consumption of the current circuit device is large, it may be determined that the current circuit device meets the preset black box processing conditions.

[0044] In another exemplary embodiment, the preset black box processing condition may be to determine that the path of the current circuit device is blocked. For example, when it is determined that the information of the next level cannot be obtained according to the netlist, it may be determined that the current circuit device meets the preset black box processing condition.

[0045] Step 130: Obtain a port connection file of the black box device, and determine a connection relationship of the black box device according to the port connection file.

[0046] The port connection file may be provided by a user, or may be obtained based on connection information in a netlist. The input and output connection relationship in the black box device may be obtained based on the connection information in the port connection file.

[0047] For example, Figure 2 1 is a schematic diagram of a cross-FPGA circuit structure provided according to the first embodiment of the present invention. Figure 2 As shown, according to the above black box processing conditions, Black box 1 in FPGA 1 can be used as a black box device, and Black box 2 in FPGA 2 can be used as a black box device. According to the connection information, it can be determined as follows Figure 2 The input and output connection relationship is shown.

[0048] Step 140: Map the connection relationship to the target connection type according to the input interface type and the output interface type in the connection relationship.

[0049] In FPGA circuits, input interface types include but are not limited to: endpoint input interface (such as Figure 2 in2 and in3), bus input interface (such as Figure 2 bus1[4:0], bus3[4:0] and bus4[4:0] in the clock information input interface (such as Figure 2 in6 and in7), drive clock information input interface (such as Figure 2Output interface types include but are not limited to: endpoint type output interface (such as Figure 2 out1, out2, out3 and out4 in), bus output interface (such as Figure 2 bus2[4:0] and bus5[4:0] in the ), drive clock information output interface (such as Figure 2 r2, r3, r4 and r5).

[0050] According to the input and output interface type, the connection relationship can be mapped to the target connection type. For example, in2 to out2 can be mapped to an endpoint type input and output connection type (in_out).

[0051] In order to simplify the above-mentioned mapping operation, in an optional implementation of an embodiment of the present invention, the connection relationship is mapped to the target connection type according to the input interface type and the output interface type in the connection relationship, including: constructing a preset connection type query table according to each preset input interface type and each preset output interface type; wherein the preset connection type query table includes a plurality of preset connection types, and corresponding link transmission delays; performing a connection relationship query in the preset connection type query table according to the input interface type and the output interface type in the connection relationship, and mapping the connection relationship to the target connection type.

[0052] Constructing a preset connection type query table can be to classify and sort out the interaction between the black box and the outside by input interface type and output interface type. Figure 2 The FPGA circuit structure diagram shown in the figure, the preset connection types include: 1. For the clock transmission to the endpoint (port) inside the black box, such as Figure 2 In in6 to R2, in7 to R3, store the preset connection type as clk, store clock information, and store according to the clock domain; 2. For the endpoint input interface (input port) to the internal timing device (reg, Figure 2 abbreviated as r in the figure, and different timing devices are distinguished by serial numbers) such as Figure 2 In in0 to r2, in1 to r3, in4 to r4, in5 to r5, the preset connection type is stored as in_reg, the endpoint input interface name (input port name) and the driving clock information are stored, and the direction is in; 3. For the path from reg to the endpoint output interface (output port), such as Figure 2 In r3 to out1, the preset connection type is stored as reg_out, the endpoint type output interface name (output port name) and the driving clock information are stored, and the direction is out; 4. For the path from input port to output port type, such as Figure 2 In in2 to out2, the default connection type is stored as in_out, and the input and output endpoint names are stored as port name; 5. For the input port to the bus output interface (output bus) type, such as Figure 2 In in3 to bus2[4:0], the preset connection type is stored as in_out, the input is stored as port name, and the output is bus_name[start bit: end bit]; 6. For the bus type input interface (input bus) to output bus type, such as Figure 2 In bus3[4:0] to bus5[4:0], the preset connection type is stored as in_out, the input is stored as bus name[start bit: end bit], and the output is stored as bus name[start bit: end bit]; 7. For the input bus to output port type, such as Figure 2 In bus1[4:0] to out3, the preset connection type is stored as in_out, the input is stored as bus_name[start bit:end bit], and the output is port name.

[0053] For each preset connection type, a corresponding link transmission delay may be set, wherein the link transmission delay may be set based on an empirical value, or the link transmission delay may be determined based on an evaluation tool (such as vivado) for an FPGA circuit.

[0054] Step 150: Obtain a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay.

[0055] According to the connection information, the FPGA circuit can be simplified to obtain the black box boundary and internal connection information, thereby obtaining each timing path. The timing path is composed of multiple timing arcs according to the connection relationship. The link transmission delay of each timing arc can be accumulated into the path delay corresponding to the timing path.

[0056] For example, Figure 2 As shown, from in0 to r2, the corresponding link transmission delay can be obtained, where the clock pin is in6 input. r3 is output through out1, passes through the TDM_T terminal, crosses the FPGA path to r5 in Black box2, and forms a timing path. The path transmitted to Black box1 through bus bus1[4:0] is abstracted as the input bus to output port path type. Based on the empirical value or the accurate value obtained by traversing the path in advance, the static timing analysis result from bus1[4:0] to the final r10 can be calculated. In addition, there is also a one-to-one correspondence between the number of buses, such as Figure 2In bus3[4:0] to bus4[4:0], each bit is a connection relationship (determined by the initial black box boundary connection relationship), which can be abstracted as a one-to-one correspondence between black boxes, so as to obtain the corresponding timing arcs and perform marking calculations after mapping.

[0057] Step 160: Determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path.

[0058] There are many ways to determine whether the FPGA circuit design meets the requirements. For example, when the path delay is greater than the set value, it can be determined that the FPGA circuit design does not meet the expected working requirements. Alternatively, other performance judgments of the circuit can be made based on the path delay to determine whether the FPGA circuit design meets the expected working requirements.

[0059] In an optional implementation of an embodiment of the present invention, determining whether the FPGA circuit design meets the expected working requirements is performed based on the delays of each path, including: screening the worst path in each timing path based on the delays of each path; determining the path hold time and setup time based on the worst path and the worst path delay corresponding to the worst path; and determining whether the FPGA circuit design can operate at a preset clock frequency based on the path hold time and setup time.

[0060] Among them, the worst path is the timing path with the longest path delay. The worst path delay is the path delay corresponding to the worst path. Setup time refers to the minimum time that the data must remain stable before the clock signal edge (usually the rising edge) of the trigger (timing device) arrives. Hold time refers to the minimum time that the data must remain stable after the clock signal edge of the trigger (timing device) arrives. Path delay is an important parameter that affects setup time and hold time. Therefore, based on the knowledge of sequential circuit analysis, the path hold time and setup time can be determined based on the worst path delay. Furthermore, based on the knowledge of sequential circuit analysis, it is possible to determine whether the FPGA circuit design can work at the preset clock frequency based on the hold time and setup time to guide the FPGA circuit design.

[0061] The technical solution of this embodiment is to obtain a netlist in the FPGA circuit design; determine, based on the netlist, that the current circuit device meets the preset black box processing conditions, and use the current circuit device as a black box device; obtain the port connection file of the black box device, and determine the connection relationship of the black box device based on the port connection file; map the connection relationship to the target connection type based on the input interface type and the output interface type in the connection relationship; obtain the link transmission delay corresponding to the target connection type, and determine the path delay corresponding to each timing path based on the link transmission delay; determine whether the FPGA circuit design meets the expected working requirements based on each path delay, thereby solving the problem of large consumption of timing analysis resources for large circuit devices encountered during static timing analysis of FPGA circuits. By simplifying the larger design devices in the FPGA circuit into black boxes for processing, static timing analysis can be simplified to achieve the purpose of fast timing analysis and avoid excessive memory usage.

[0062] Embodiment 2

[0063] Figure 3 1 is a flowchart of a static timing analysis method in an FPGA circuit provided according to Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution. The technical solution in this embodiment can be combined with each optional solution in one or more of the above embodiments. Figure 3 As shown, the method includes:

[0064] Step 310: Obtain a netlist in the FPGA circuit design.

[0065] Step 320: When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device.

[0066] In an optional implementation of an embodiment of the present invention, when it is determined based on the netlist that the current circuit device meets preset black box processing conditions, the current circuit device is used as a black box device, including: determining the device transmission time of the current circuit device and the circuit transmission time when the current circuit device is not added to the FPGA circuit through an FPGA circuit evaluation tool based on the netlist; when the device transmission time is greater than the circuit transmission time, the current circuit device is used as a black box device.

[0067] When the device transmission time of the current circuit device is greater than the circuit transmission time, it indicates that the current circuit device consumes a large amount of resources, and thus can be processed as a black box device.

[0068] In another optional implementation of the embodiment of the present invention, when it is determined according to the netlist that the current circuit device meets the preset black box processing conditions, the current circuit device is used as a black box device, including: according to the netlist, when the current circuit device includes at least two of the following connection relationships of the same type or different types, the current circuit device is used as a black box device: the input port is connected to the D end of the timing device, the D end of the timing device is connected to the output port, the clock pin input, the bus input, and the bus output.

[0069] Among them, the input port is connected to the D terminal of the timing device, for example, Figure 2 In0 to R2, In1 to R3, In4 to R4, In5 to R5 are shown. The D terminal of the sequential device is connected to the output port, for example, Figure 2 The clock pin input is as shown in r3 to out1. Figure 2 in6 and in7 as shown. The bus input is as Figure 2 The bus outputs are shown as bus1[4:0], bus3[4:0], and bus4[4:0]. Figure 2 bus2[4:0] and bus5[4:0] are shown.

[0070] Specifically, when the current circuit device includes multiple connections between the input port and the D end of the sequential device, multiple connections between the D end of the sequential device and the output port, multiple clock pin inputs, multiple bus inputs, or multiple bus outputs, the current circuit device can be processed as a black box device. Alternatively, when the current circuit device includes multiple connections between the input port and the D end of the sequential device, the D end of the sequential device and the output port, clock pin inputs, bus inputs, and bus outputs, the current circuit device can be processed as a black box device.

[0071] Step 330: Obtain the port connection file of the black box device, and determine the connection relationship of the black box device according to the port connection file.

[0072] Step 340: construct a preset connection type query table according to each preset input interface type and each preset output interface type.

[0073] The preset connection type query table includes a plurality of preset connection types and corresponding link transmission delays.

[0074] Step 350: According to the input interface type and the output interface type in the connection relationship, a connection relationship query is performed in a preset connection type query table, and the connection relationship is mapped to a target connection type.

[0075] Step 360: Obtain the link transmission delay corresponding to the target connection type, and determine the path delay corresponding to each timing path according to the link transmission delay.

[0076] Step 370: Filter the worst path among the timing paths according to the delays of the paths.

[0077] Step 380: Determine the path holding time and the path establishment time according to the worst path and the worst path delay corresponding to the worst path.

[0078] Step 390: Determine whether the FPGA circuit design can operate at a preset clock frequency based on the path hold time and setup time.

[0079] The technical solution of the embodiment of the present invention is to obtain a netlist in an FPGA circuit design; determine, based on the netlist, that the current circuit device meets the preset black box processing conditions, and use the current circuit device as a black box device; obtain a port connection file of the black box device, and determine the connection relationship of the black box device based on the port connection file; construct a preset connection type query table based on each preset input interface type and each preset output interface type; query the connection relationship in the preset connection type query table based on the input interface type and the output interface type in the connection relationship, and map the connection relationship to the target connection type; obtain the link transmission delay corresponding to the target connection type, and determine the connection relationship based on the preset connection type. Determine the path delay corresponding to each timing path according to the link transmission delay; select the worst path in each timing path according to each path delay; determine the path hold time and setup time according to the worst path and the worst path delay corresponding to the worst path; determine whether the FPGA circuit design can work at the preset clock frequency according to the path hold time and setup time, which solves the problem of large timing analysis resource consumption of large circuit devices encountered during static timing analysis of FPGA circuits. By simplifying the larger design devices in the FPGA circuit into black boxes for processing, static timing analysis can be simplified to achieve the purpose of fast timing analysis and avoid excessive memory usage.

[0080] Embodiment 3

[0081] Figure 4 1 is a flowchart of a static timing analysis method in an FPGA circuit provided according to Embodiment 3 of the present invention. This embodiment is a further refinement of the above technical solution. The technical solution in this embodiment can be combined with each optional solution in one or more of the above embodiments. Figure 4 As shown, the method includes:

[0082] Step 410: Obtain a netlist in the FPGA circuit design.

[0083] Step 420: When it is determined according to the netlist that the transmission information of the next circuit device has not been obtained, the current circuit device is used as a black box device.

[0084] Specifically, the instance elements in the netlist can be traversed. If it is found that the transmission information of the next circuit device cannot be obtained, the current circuit device can be used as a black box device to solve the problem of incomplete timing analysis caused by directly ignoring the path when the timing path is blocked in the prior art.

[0085] Step 430: When the port connection file of the black box device is not obtained, all input ports and output ports of the black box device are interconnected to obtain corresponding multiple timing paths.

[0086] Figure 5 FIG. 1 is a schematic diagram of a black box device processing according to Embodiment 3 of the present invention. Figure 5 As shown, when the black box is determined but the connection relationship within the black box device is unknown, all inputs and all outputs of the black box device can be connected separately. Figure 5 As shown, blackbox1 has two inputs, IN0 and IN1, and two outputs, OUT0 and OUT1. All input ports and all output ports are interconnected. There are 4 interconnection lines in blackbox 1, namely, IN0->OUT0, IN0->OUT1, IN1->OUT0, and IN1->OUT1. Before full connection, Figure 5 There is only one timing path r3->r7 in the blackbox. After full connection, the input and output of blackbox 1 and blackbox 2 can be freely combined. Figure 5 There are a total of 9 cross-FPGA timing paths: r1->IN0->OUT0->IN2->OUT2->r5, r1->IN0->OUT1->IN3->OUT2->r5, r1->IN0->OUT0->IN2->OUT3->r6, r1->IN0->OUT1->IN3->OUT3->r6, r2->IN1->OUT0->IN2->OUT2->r5, r2->IN1->OUT1->IN3->OUT2->r5, r2->IN1->OUT1->IN3->OUT3->r6, r2->IN1->OUT0->IN2->OUT3->r6, and r3->r7.

[0087] Step 440: Calculate the path delay of each timing path.

[0088] The path delay of each timing path can be assigned using empirical values. For example, 0.1ns is used. Especially in cross-FPGA circuits, since the cross-FPGA path will be transmitted through the cable line, whether it is directly connected by the cable line or transmitted through the time division multiplexing module (TDM), the delay will be large, ranging from tens of nanoseconds to hundreds of nanoseconds. Compared with this, the black box delay inside the FPGA can be ignored, so 0.1ns can be used to mark the black box delay inside the FPGA. Alternatively, the path delay can be calculated using the vivado tool.

[0089] Step 450: Determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path.

[0090] In an optional implementation of an embodiment of the present invention, determining whether the FPGA circuit design meets the expected working requirements is performed based on the delays of each path, including: screening the worst path in each timing path based on the delays of each path; determining the path hold time and setup time based on the worst path and the worst path delay corresponding to the worst path; and determining whether the FPGA circuit design can operate at a preset clock frequency based on the path hold time and setup time.

[0091] The technical solution of the embodiment of the present invention is to obtain a netlist in an FPGA circuit design; when it is determined based on the netlist that the transmission information of the next circuit device has not been obtained, the current circuit device is used as a black box device; when the port connection file of the black box device has not been obtained, all input ports and output ports of the black box device are interconnected to obtain multiple corresponding timing paths; the path delay of each timing path is calculated; and according to each path delay, it is determined whether the FPGA circuit design meets the expected working requirements, which solves the problem of incomplete timing analysis caused by directly ignoring the path when the timing path is blocked in the prior art. By processing the black box device, the timing processing path is increased, and the timing analysis of the design will not be inaccurate due to lack of paths due to ignoring the black box model.

[0092] Embodiment 4

[0093] Figure 6 1 is a schematic diagram of the structure of a static timing analysis device in an FPGA circuit provided according to a fourth embodiment of the present invention. Figure 6 As shown, the device includes: a netlist acquisition module 610, a black box device determination module 620, a connection relationship determination module 630, a target connection type determination module 640, a path delay determination module 650 and a circuit design detection module 660. Among them:

[0094] The netlist acquisition module 610 is used to acquire the netlist in the FPGA circuit design;

[0095] A black box device determination module 620 is used to determine, based on the netlist, that when the current circuit device meets the preset black box processing conditions, the current circuit device is used as a black box device;

[0096] A connection relationship determination module 630, used to obtain a port connection file of a black box device and determine a connection relationship of the black box device according to the port connection file;

[0097] A target connection type determination module 640 is used to map the connection relationship to a target connection type according to the input interface type and the output interface type in the connection relationship;

[0098] A path delay determination module 650 is used to obtain a link transmission delay corresponding to a target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay;

[0099] The circuit design detection module 660 is used to determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path.

[0100] Optionally, the black box device determination module 620 includes:

[0101] A transmission time evaluation unit, used to determine the device transmission time of the current circuit device and the circuit transmission time when the current circuit device is not added to the FPGA circuit according to the netlist through the FPGA circuit evaluation tool;

[0102] The first black box device determining unit is used to determine the current circuit device as a black box device when the device transmission time is greater than the circuit transmission time.

[0103] Optionally, the black box device determination module 620 includes:

[0104] The second black box device determination unit is configured to, according to the netlist, treat the current circuit device as a black box device when the current circuit device includes at least two of the following connection relationships of the same type or different types:

[0105] The input port is connected to the D terminal of the sequential device, and the D terminal of the sequential device is connected to the output port, the clock pin input, the bus input, and the bus output.

[0106] Optionally, the target connection type determination module 640 includes:

[0107] A preset connection type query table building unit, used to build a preset connection type query table according to each preset input interface type and each preset output interface type;

[0108] The preset connection type query table includes a plurality of preset connection types and corresponding link transmission delays;

[0109] The target connection type determination unit is used to query the connection relationship in a preset connection type query table according to the input interface type and the output interface type in the connection relationship, and map the connection relationship to the target connection type.

[0110] Optionally, the circuit design detection module 660 includes:

[0111] A worst path screening unit, used for screening the worst path among various timing paths according to the delay of each path;

[0112] A holding time and establishment time determination unit, configured to determine a path holding time and an establishment time according to a worst path and a worst path delay corresponding to the worst path;

[0113] The circuit design detection unit is used to determine whether the FPGA circuit design can work according to the preset clock frequency based on the path holding time and the setup time.

[0114] Optionally, the black box device determination module 620 includes:

[0115] The third black box device determining unit is used to determine, according to the netlist, that when the transmission information of the next circuit device is not obtained, the current circuit device is used as a black box device.

[0116] Optionally, the device further includes:

[0117] A timing path determination module, for interconnecting all input ports and output ports of the black box device to obtain multiple corresponding timing paths when the port connection file of the black box device is not obtained;

[0118] The path delay calculation module is used to calculate the path delay of each timing path.

[0119] The static timing analysis device in the FPGA circuit provided by the embodiment of the present invention can execute the static timing analysis method in the FPGA circuit provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0120] Embodiment 5

[0121] Figure 7A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0122] like Figure 7 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0123] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0124] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a static timing analysis method in an FPGA circuit.

[0125] In some embodiments, the static timing analysis method in the FPGA circuit can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the static timing analysis method in the FPGA circuit described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the static timing analysis method in the FPGA circuit by any other appropriate means (for example, by means of firmware).

[0126] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0127] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0128] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0129] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0130] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0131] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0132] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0133] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A static timing analysis method in an FPGA circuit, characterized in that: include: Get the netlist in FPGA circuit design; When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device; Acquire a port connection file of a black box device, and determine a connection relationship of the black box device according to the port connection file; Mapping the connection relationship to a target connection type according to an input interface type and an output interface type in the connection relationship; Acquire a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay; Based on the delays of each path, determine whether the FPGA circuit design meets the expected working requirements.

2. The method according to claim 1, characterized in that When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device, including: According to the netlist, determining, by an FPGA circuit evaluation tool, a device transmission time of the current circuit device and a circuit transmission time when the current circuit device is not added to the FPGA circuit; When the device transmission time is greater than the circuit transmission time, the current circuit device is used as a black box device.

3. The method according to claim 1, characterized in that When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device, including: According to the netlist, when the current circuit device includes at least two of the following connection relationships of the same type or different types, the current circuit device is used as a black box device: The input port is connected to the D terminal of the sequential device, and the D terminal of the sequential device is connected to the output port, the clock pin input, the bus input, and the bus output.

4. The method according to claim 1, characterized in that Mapping the connection relationship to a target connection type according to an input interface type and an output interface type in the connection relationship includes: Constructing a preset connection type query table according to each preset input interface type and each preset output interface type; The preset connection type query table includes a plurality of preset connection types and corresponding link transmission delays; According to the input interface type and the output interface type in the connection relationship, a connection relationship query is performed in the preset connection type query table, and the connection relationship is mapped to a target connection type.

5. The method according to claim 1, characterized in that Determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path, including: According to the delay of each path, the worst path is selected from each timing path; Determine a path holding time and a path establishment time according to the worst path and a worst path delay corresponding to the worst path; According to the path holding time and setup time, it is determined whether the FPGA circuit design can operate according to the preset clock frequency.

6. The method according to claim 1, characterized in that When it is determined according to the netlist that the current circuit device meets the preset black box processing condition, the current circuit device is used as a black box device, including: When it is determined according to the netlist that the transmission information of the next circuit device has not been acquired, the current circuit device is used as a black box device.

7. The method according to claim 6, characterized in that Also includes: When the port connection file of the black box device is not obtained, all input ports and output ports of the black box device are interconnected to obtain multiple corresponding timing paths; Calculate the path delay of each timing path.

8. A static timing analysis device in an FPGA circuit, characterized in that: include: A netlist acquisition module is used to acquire the netlist in FPGA circuit design; A black box device determination module, configured to determine, based on the netlist, that when a current circuit device satisfies a preset black box processing condition, use the current circuit device as a black box device; A connection relationship determination module, used to obtain a port connection file of a black box device, and determine a connection relationship of the black box device according to the port connection file; A target connection type determination module, used for mapping the connection relationship to a target connection type according to the input interface type and the output interface type in the connection relationship; A path delay determination module, used to obtain a link transmission delay corresponding to the target connection type, and determine a path delay corresponding to each timing path according to the link transmission delay; The circuit design detection module is used to determine whether the FPGA circuit design meets the expected working requirements based on the delay of each path.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the static timing analysis method in the FPGA circuit described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the static timing analysis method in the FPGA circuit according to any one of claims 1 to 7 when executed.

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