A full-automatic DRAM memory unit read-write function test method and system

Abstract

The application relates to the technical field of integrated circuit testing, and discloses a full-automatic DRAM memory unit read-write function test method and system, which comprises the following steps: collecting a silk-screen image of a to-be-tested chip, identifying the silk-screen image by using a ResNet neural network to obtain silk-screen information; reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to an ATE device; electrically connecting the ATE device with the to-be-tested chip, and performing read-write function test on the to-be-tested chip by the ATE device according to the received read-write function test method. The application realizes the automation of DRAM memory unit read-write function test work, effectively improves the read-write function test work efficiency, and ensures a high read-write function test accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing, and more particularly, to a full-automatic DRAM memory cell read-write function test method and system. BACKGROUND

[0002] DRAM memory cell read-write function test is usually based on a fault model of DRAM memory cell. Common fault models mainly include: (1) a fixed cell-based fault model; (2) a memory test fault model based on bridge defects; (3) a memory test fault model based on associated defects; (4) a data retention fault model, etc. The fault modes exhibited by these fault models mainly include: (1) hard failure or soft failure of fixed "1" / "0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) pattern sensitivity failure: the memory cannot work reliably when certain test patterns are used, etc.

[0003] DRAM chip memory cell read-write function test requires a large amount of time and a large amount of manpower and material resources. Even so, the possibility of human error is still relatively large. At present, test personnel are committed to the automation of the test process, and propose to use ATE (Automatic Test Equipment, integrated circuit automatic test machine) to test the chip. By setting the values of the device operating power supply, input level, output level, reference level, and load current, setting the power-on sequence of the device, setting the data format, timing, channel, and control register allocation of the address signal, control signal, and data signal of the device, respectively, the full-chip erasing and verification, single sector erasing and verification, write status register verification, read chip ID verification, full-chip memory cell read-write function verification, write protection verification, DC parameter verification, and AC parameter verification are performed. However, this method still requires the full participation of test personnel, and there are still problems of low efficiency and high error probability in DRAM memory cell read-write function test work. SUMMARY

[0004] The present application provides a full-automatic DRAM memory cell read-write function test method and system to overcome the defects of low efficiency and high error probability in current DRAM memory cell read-write function test work.

[0005] To solve the above technical problems, the technical solutions of the present application are as follows:

[0006] A full-automatic DRAM memory cell read-write function test method, comprising the following steps:

[0007] Collecting a silk screen image of a chip to be tested, and using a ResNet neural network to recognize the silk screen image to obtain silk screen information;

[0008] According to the silk screen information, read a read-write function test method matching the silk screen information from a preset database, and transmit the read-write function test method to an ATE device;

[0009] Electrically connect the ATE device with the chip to be tested, and perform read-write function test on the chip to be tested according to the received read-write function test method.

[0010] As a preferred solution, the step of performing read-write function test on the chip to be tested according to the received read-write function test method includes: setting values of working power supply, input level, output level, reference level and load current applied to the chip to be tested according to the received read-write function test method; setting power-on sequence of the chip to be tested; setting data format, timing, channel and allocation of control register of control signal, address signal and data signal of the chip to be tested; sequentially calling preset test patterns, writing data to the chip to be tested, and reading output data of the chip to be tested; comparing and verifying the output data of the chip to be tested with corresponding expected readout data, if the comparison is consistent, judging that the read-write function of the chip to be tested is normal, otherwise, judging that the read-write function of the chip to be tested is abnormal.

[0011] As a preferred solution, the preset test pattern includes one or more of “0” pattern, write-all-“1” read-all-“1” pattern, walking pattern and checkerboard pattern.

[0012] As a preferred solution, further including the following steps: classifying the chip to be tested according to the comparison and verification, transporting the chip judged as normal in read-write function to a first classification through a conveyor belt, transporting the chip judged as abnormal in read-write function to a second classification through the conveyor belt, and counting normal rate of the chip.

[0013] As a preferred solution, the step of reading a read-write function test method matching the silk screen information from a preset database according to the silk screen information includes: the silk screen information includes a chip model; according to the chip model in the silk screen information, calling a read-write function test method with the chip model label from the preset database, and transmitting to the ATE device.

[0014] Further, the present application also proposes a full-automatic DRAM memory unit read-write function test system, which applies the method proposed in any of the above technical solutions. Wherein, the system of the present application includes an image acquisition module, an identification module, a read-write function test method reading module, an ATE device, a conveyor belt and a power mechanism.

[0015] The image acquisition module is configured to acquire a silk screen image of the chip to be tested; the identification module is configured to identify the silk screen image of the chip to be tested by using a ResNet neural network, and output silk screen information of the chip to be tested; the read-write function test method reading module comprises a database, and the database is pre-stored with read-write function test methods with chip model labels; the read-write function test method reading module is configured to read, from the database, a read-write function test method matching the silk screen information according to the silk screen information; the ATE device is configured to perform read-write function test on the chip to be tested according to the received read-write function test method; and the conveying belt is configured to convey the chip to be tested to the image acquisition module and the ATE device in sequence under the action of the power mechanism.

[0016] As a preferred solution, the system further comprises an electrostatic shielding cover, which is configured to be arranged outside the ATE device and the periphery of the chip to be tested when the chip to be tested is conveyed to the position of the ATE device.

[0017] As a preferred solution, the system further comprises a conveying control module, which is connected with the ATE device and the power mechanism; the conveying control module controls the start-stop and conveying speed of the conveying belt by controlling the start-stop of the power mechanism; when the conveying belt conveys the chip to be tested to the position of the ATE device, the conveying control module controls the conveying belt to stop working; after the ATE device completes the read-write function test, the ATE device sends a test result signal to the conveying control module, and the conveying control module controls the conveying belt to convey the chip to be tested to the first classification port or the second classification port according to the test result signal.

[0018] As a preferred solution, the ATE device is pre-stored with a test pattern, which is configured to verify the read-write function test of the chip to be tested; the test pattern comprises one or more of a “0” pattern, a “1” pattern, a walking pattern and a chessboard pattern.

[0019] Further, the present application further proposes a full-automatic DRAM memory unit read-write function test system, comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps of the full-automatic DRAM memory unit read-write function test method proposed in any of the technical solutions above when executing the computer program.

[0020] Further, the present application further proposes a storage medium, which stores a computer program, and the computer program implements the steps of the full-automatic DRAM memory unit read-write function test method proposed in any of the technical solutions above when executed by a processor.

[0021] Compared with the prior art, the beneficial effects of the technical scheme of the present application are: the present application adopts ResNet neural network to recognize the silk screen image of the DRAM storage unit chip to be tested, reads and calls the corresponding read-write function test method from the database according to the recognition result, and then adopts the ATE device to test the read-write function of the chip to be tested according to the received read-write function test method, realizes the automation of the read-write function test work of the DRAM storage unit, effectively improves the work efficiency of the read-write function test, and at the same time ensures a high read-write function test accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The flowchart of the full-automatic DRAM storage unit read-write function test method of the embodiment of the present application.

[0023] Figure 2 The flowchart of the read-write function test of the ATE device of the embodiment of the present application.

[0024] Figure 3 The architecture diagram of the full-automatic DRAM storage unit read-write function test system of the embodiment of the present application. DETAILED DESCRIPTION

[0025] The drawings are only used for illustrative description and cannot be understood as a limitation of the patent;

[0026] In order to better illustrate the embodiment, some components in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0027] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0028] The technical scheme of the present application will be further described below in combination with the drawings and embodiments.

[0029] Embodiment 1

[0030] The embodiment proposes a full-automatic DRAM storage unit read-write function test method, as shown in Figure 1 The flowchart of the full-automatic DRAM storage unit read-write function test method of the embodiment of the present application.

[0031] The embodiment proposes a full-automatic DRAM storage unit read-write function test method, as shown in

[0032] S1, collect the silk screen image of the chip to be tested, adopt ResNet neural network to recognize the silk screen image, and obtain the silk screen information.

[0033] S2, read the read-write function test method matched with the silk screen information from the preset database 310 according to the silk screen information, and transmit the read-write function test method to the ATE device 400.

[0034] S3, electrically connect the ATE device 400 with the to-be-tested chip, and the ATE device 400 performs read-write function test on the to-be-tested chip according to the received read-write function test method.

[0035] In a specific implementation, a plurality of to-be-tested DRAM storage unit chips are placed on a conveyor belt to pass through an OpenMV camera and a J750-EX series ATE device 400 in sequence.

[0036] The OpenMV camera collects the silk screen image of the to-be-tested chip, and the ResNet neural network trained in MicroPython language is called to recognize the silk screen image to obtain the silk screen information, call the read-write function test method of the to-be-tested DRAM storage unit chip corresponding to the silk screen information, and send it to the ATE device 400 through a wireless transmission protocol.

[0037] The conveyor belt conveys the to-be-tested DRAM storage unit chip to the position of the ATE device 400, and the ATE device 400 is electrically connected with the to-be-tested chip. At this time, the ATE device 400 performs read-write function test on the to-be-tested chip according to the received read-write function test method.

[0038] The J750-EX is a very large scale integrated circuit (VLSI) test system with rich and powerful test resources, which can be used to meet the test requirements of new generation VLSI storage products. By setting test related parameters on the J750-EX and executing programs, the read-write test requirements of the DRAM storage unit can be well met.

[0039] In this embodiment, the ResNet neural network is used to recognize the silk screen image of the to-be-tested DRAM storage unit chip, and the corresponding read-write function test method is read from the database 310 according to the recognition result, and then the ATE device 400 is used to perform read-write function test on the to-be-tested chip according to the received read-write function test method. The automation of DRAM storage unit read-write function test work is realized, the read-write function test work efficiency is effectively improved, and the read-write function test accuracy is guaranteed.

[0040] In an optional embodiment, the step of performing read-write function test on the to-be-tested chip by the ATE device 400 according to the received read-write function test method comprises:

[0041] S3.1, the ATE device 400 sets respectively according to the received read-write function test method:

[0042] (1) the values of the operating power, input level, output level, reference level and load current applied to the chip under test;

[0043] (2) the power-on sequence of the chip under test;

[0044] (3) the data format, timing, channel and allocation of control registers of the control signal, address signal and data signal of the chip under test.

[0045] S3.2, sequentially invoke the preset test pattern, write data to the chip under test, and read the output data of the chip under test.

[0046] S3.3, compare and verify the output data of the chip under test with the corresponding expected readout data: if the comparison is consistent, it is judged that the read-write function of the chip under test is normal; otherwise, it is judged that the read-write function of the chip under test is abnormal.

[0047] As shown in FIG. 4, a flowchart for performing read-write function test on the ATE device 400 of the embodiment is shown. Figure 2

[0048] For the common fault model of DRAM memory cells, test patterns are used to test the read-write function. Common fault modes include: (1) hard failure or soft failure fixed as "1" or "0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) pattern sensitivity failure.

[0049] When performing full-chip memory cell read-write function test on DRAM memory cells, the above fault modes are mainly tested by setting different test patterns.

[0050] In an optional embodiment, the test patterns used include one or more of "0" pattern (writeall_00_readall_00.pat), write-all-1 read-all-1 pattern (writeall_ff_readall_ff.pat), walking pattern (walking.pat), and checkboard pattern (checkboard.pat).

[0051] Further, in an optional embodiment, the method further includes the following steps: according to the comparison and verification, the chip under test is classified, the chip judged to have normal read-write function is transported to the first classification through a conveyor belt, the chip judged to have abnormal read-write function is transported to the second classification through a conveyor belt, and the normal rate of the chip is counted.

[0052] In this embodiment, according to the read-write function test result of the DRAM memory cell chip under test, the chip is classified.

[0053] ​In a specific implementation process, whether all test items pass is judged according to the test result of the read-write function of the DRAM chip according to J750-EX, and classification is performed through a double-path conveyor belt; if yes, the to-be-tested chip is directly conveyed from the first path conveyor belt to the first classification box for storage as a qualified chip; if no, the to-be-tested chip is conveyed from the second path conveyor belt to the second classification box for storage as an unqualified chip, and the current read-write function test pass rate is counted.

[0054] Further, in an optional embodiment, the silk screen information includes a chip model.

[0055] In this embodiment, the step of reading the read-write function test method matching the silk screen information from the preset database 310 according to the silk screen information includes the following steps: according to the chip model in the silk screen information, the read-write function test method with the chip model label is called from the preset database 310 and transmitted to the ATE device 400.

[0056] The database 310 of this embodiment stores read-write function test methods corresponding to different chip models. This embodiment uses a ResNet neural network to recognize the silk screen image of the to-be-tested chip to obtain the silk screen information with the chip model, and calls the matching read-write function test method according to the chip model of the to-be-tested chip, thereby realizing automatic read-write function test while ensuring high test accuracy.

[0057] Embodiment 2

[0058] This embodiment proposes a full-automatic DRAM memory unit read-write function test system, as shown in Figure 3 The architecture diagram of the full-automatic DRAM memory unit read-write function test system of this embodiment is shown.

[0059] The full-automatic DRAM memory unit read-write function test system proposed in this embodiment includes:

[0060] The image acquisition module 100 is used to acquire the silk screen image of the to-be-tested chip.

[0061] The recognition module 200 is used to recognize the silk screen image of the to-be-tested chip by using a ResNet neural network, and output the silk screen information of the to-be-tested chip.

[0062] The read-write function test method reading module 300 includes a database 310, and the database 310 is preset with read-write function test methods with chip model labels.

[0063] The read-write function test method reading module 300 is used to read the read-write function test method matching the silk screen information from the database 310 according to the silk screen information.

[0064] The ATE device 400 is used for read-write function test of the chip under test according to the received read-write function test method.

[0065] The conveyor belt is used for conveying the chip under test to pass through the image acquisition module 100 and the ATE device 400 under the action of the power mechanism.

[0066] In a specific implementation process, the recognition module 200 is internally provided with a ResNet neural network called by MicroPython language, and the image acquisition module 100, the recognition module 200, the read-write function test method reading module 300 and the ATE device 400 are internally provided with a wireless information transmission protocol called by MicroPython language.

[0067] In the embodiment, the ATE device 400 is pre-provided with a test pattern for read-write function test verification of the chip under test.

[0068] The test pattern includes one or more of a "0" pattern, a write-all "1" and read-all "1" pattern, a walking pattern, and a checkerboard pattern.

[0069] Further, after the recognition module 200 completes recognition and outputs the silk screen printing information of the chip under test, the recognized silk screen printing information is transmitted to the read-write function test method reading module 300. The silk screen printing information includes a chip model.

[0070] The read-write function test method reading module 300 reads the read-write function test method matched with the silk screen printing information from the database 310 according to the received silk screen printing information. Specifically, the read-write function test method reading module 300 retrieves the read-write function test method with the chip model label from the pre-provided database 310 according to the chip model in the silk screen printing information, and transmits it to the ATE device 400 for read-write function test.

[0071] In a specific implementation process, the ATE device 400 adopts a J750-EX series tester. When the ATE device 400 performs read-write function test on the chip under test according to the received read-write function test method, the ATE device 400 sets the values of the working power supply, the input level, the output level, the reference level and the load current applied to the chip under test according to the received read-write function test method; sets the power-on sequence of the chip under test; sets the data format, timing, channel and control register allocation of the control signal, address signal and data signal of the chip under test.

[0072] After the connection and setting of the to-be-tested chip are completed, the ATE device 400 sequentially calls preset test patterns, writes data to the to-be-tested chip, reads output data of the to-be-tested chip, and then compares and verifies the output data of the to-be-tested chip with corresponding expected readout data, if the comparison is consistent, it is judged that the read-write function of the to-be-tested chip is normal, otherwise, it is judged that the read-write function of the to-be-tested chip is abnormal.

[0073] In an optional embodiment, the system further comprises an electrostatic shielding cover, which is used to cover the ATE device 400 and the periphery of the to-be-tested chip when the to-be-tested chip is transported to the position of the ATE device 400.

[0074] The electrostatic shielding cover added in the embodiment is used to reduce various failures of the DRAM memory unit chip caused by static problems in the testing process.

[0075] In another optional embodiment, the system further comprises a transport control module connected with the ATE device 400 and the power mechanism; the transport control module controls the start-stop and transport speed of the conveyor belt by controlling the start-stop of the power mechanism.

[0076] When the conveyor belt transports the to-be-tested chip to the position of the ATE device 400, the transport control module controls the conveyor belt to stop working.

[0077] When the ATE device 400 completes the read-write function test, the ATE device 400 sends a test result signal to the transport control module, and the transport control module controls the conveyor belt to transport the to-be-tested chip to the first classification port or the second classification port according to the test result signal.

[0078] The first classification port and the second classification port are provided with a first classification box and a second classification box on one side, respectively, for classifying and storing the DRAM memory unit chips of the current batch that pass the read-write function test and do not pass the read-write function test.

[0079] Further, the embodiment also enables the ATE device 400 to statistically count the normal rate of the read-write function test of the DRAM memory unit chips of the current batch, facilitating the statistical and analysis work of the staff.

[0080] Embodiment 3

[0081] The embodiment proposes a full-automatic DRAM memory unit read-write function test system, which comprises a memory and a processor, and the memory stores a computer program.

[0082] The processor implements the steps of the full-automatic DRAM memory unit read-write function test method of embodiment 1 when executing the computer program.

[0083] Further, the embodiment also proposes a full-automatic DRAM memory unit read-write function test system, which comprises a storage medium having a computer program stored thereon.

[0084] The computer program is executed by a processor to implement the steps of the full-automatic DRAM memory unit read-write function test method of the embodiment 1.

[0085] The same or similar reference signs correspond to the same or similar components;

[0086] The terms describing the positional relationship in the drawings are only used for illustrative description, and should not be understood as a limitation to the patent;

[0087] Obviously, the above embodiments of the present application are merely exemplary and are not intended to limit the embodiments of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to enumerate all the embodiments. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A fully automatic DRAM memory cell read / write function test method, characterized by, The method comprises the following steps: Collecting a silk screen image of the chip to be tested, identifying the silk screen image by using a ResNet neural network to obtain silk screen information; the silk screen information includes a chip model; According to the silk screen information, reading a read-write function test method matching the silk screen information from a pre-set database, and transmitting the read-write function test method to an ATE device; The ATE device is electrically connected to the chip to be tested, and the ATE device performs read-write function test on the chip to be tested according to the received read-write function test method; The ATE device sets the values of the working power supply, input level, output level, reference level and load current applied to the chip to be tested according to the received read-write function test method; and sets the power-on sequence of the chip to be tested; The data format, timing, channel and control register allocation of the control signal, address signal and data signal of the chip to be tested are set; The pre-set test pattern is called in sequence, data is written to the chip to be tested, and the output data of the chip to be tested is read; The output data of the chip to be tested is compared with the corresponding expected readout data, if the comparison is consistent, it is judged that the read-write function of the chip to be tested is normal; otherwise, it is judged that the read-write function of the chip to be tested is abnormal; The ATE device is connected with a conveying control module and a power mechanism, the conveying control module controls the start and stop of the conveying belt based on the ATE output signal, and is used for conveying the chip to be tested to a test position, and conveying the tested chip to a predetermined position based on the test result.

2. The fully automatic DRAM memory cell read / write function test method according to claim 1, wherein, The pre-set test pattern includes one or more of "0" pattern, "1" pattern, walking pattern and chessboard pattern.

3. The method of claim 1, wherein the method is characterized by, The method further comprises the following steps: According to the comparison and verification, the chip to be tested is classified, the chip judged to have normal read-write function is transported to a first classification through the conveying belt, the chip judged to have abnormal read-write function is transported to a second classification through the conveying belt, and the normal rate of the chip is counted.

4. The method according to any one of claims 1 to 3, wherein, The step of reading a read-write function test method matching the silk screen information from a pre-set database according to the silk screen information comprises: According to the chip model in the silk screen information, a read-write function test method with the chip model label is called from the pre-set database and transmitted to the ATE device.

5. A fully automatic DRAM memory cell read-write function test system, characterized in that, The method of any one of claims 1-4; wherein the system comprises: An image acquisition module for acquiring a silk screen image of the chip to be tested; An identification module for identifying the silk screen image of the chip to be tested by using a ResNet neural network to output the silk screen information of the chip to be tested; A read-write function test method reading module, wherein the database is pre-set with a read-write function test method with a chip model label; The read-write function test method reading module is used to read a read-write function test method matching the silk screen information from the database according to the silk screen information; An ATE device for performing read-write function test on the chip to be tested according to the received read-write function test method; A conveying belt for conveying the chip to be tested through the image acquisition module and the ATE device under the action of the power mechanism.

6. The fully automatic DRAM memory cell read / write function test system according to claim 5, wherein, The system further comprises an electrostatic shield cover, which is arranged outside the ATE device and the periphery of the chip to be tested when the chip to be tested is conveyed to the ATE device position.

7. The fully automatic DRAM memory cell read / write function test system according to claim 5, wherein, The system further comprises a conveying control module connected with the ATE device and the power mechanism; the conveying control module controls the start and stop of the conveying belt and the conveying speed by controlling the start and stop of the power mechanism; When the conveying belt conveys the chip to be tested to the ATE device position, the conveying control module controls the conveying belt to stop working; When the ATE device completes the read-write function test, the ATE device sends a test result signal to the conveying control module, and the conveying control module controls the conveying belt to convey the chip to be tested to the first classification port or the second classification port according to the test result signal.

8. The fully automatic DRAM memory cell read / write function test system according to claim 5, wherein, The ATE device is pre-set with a test pattern for read-write function test verification of the chip to be tested; the test pattern comprises one or more of a "0" pattern, a "1" pattern, a walking pattern, and a chessboard pattern.

9. A full-automatic DRAM memory unit read-write function test system, comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to realize the steps of the full-automatic DRAM memory unit read-write function test method in any one of claims 1-4.

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