Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a patterned material layer; forming a plurality of first mask layers on the patterned material layer, the first mask layers extending in a first direction and being spaced apart in a second direction; performing ion doping with the first mask layers as masks to form a plurality of spaced-apart doped layers, the remaining patterned material layer serving as a pattern layer; removing the first mask layers; forming a second mask layer covering the pattern layer and exposing part of the doped layers; removing the doped layers exposed by the second mask layer to form first recesses; removing the second mask layer; and removing the pattern layer to form second recesses. In the embodiment of the present application, the first mask layers and the second mask layers are formed on the pattern layer in sequence, the contact time of the pattern layer with the organic material layer is less, the C in the first mask layers and the second mask layers is less likely to diffuse into the pattern layer, and the pattern layer is less likely to have residues when the pattern layer is removed, so that the morphology quality of the second recesses is better, and the electrical performance of the semiconductor structure is optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] As the integration density of integrated circuits continues to increase, and integrated circuits are rapidly developing towards submicron and deep submicron dimensions, their pattern linewidths will become increasingly finer, which places higher demands on semiconductor processes. Therefore, conducting in-depth research on how to achieve fine-linewidth patterns to meet the new requirements of semiconductor processes has become an urgent task.

[0003] Lithographing is a key process technology for realizing integrated circuit patterns. In lithography, a photosensitive material (photoresist) is coated onto a thin film on a substrate. Light of a wavelength corresponding to the photoresist's photosensitive properties is passed through a mask with a specific pattern and irradiated onto the photoresist surface. After development, a photoresist pattern corresponding to the pattern on the mask is formed. In subsequent integrated circuit processes, this photoresist pattern is used as a barrier layer to selectively etch the underlying thin film, thus completely transferring the pattern from the mask to the substrate. The finer the linewidth of the integrated circuit pattern, the higher the imaging resolution of the photoresist is required. Since the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, reducing the wavelength of the exposure light source becomes the main way to achieve fine linewidth patterns.

[0004] In the process of patterning integrated circuits using photolithography, in order to improve the accuracy of pattern transfer, an anti-reflective coating and an organic material layer are deposited sequentially below the photoresist layer. Usually, the etching resistance of the film layer in contact with the organic material layer is improved, which can easily reduce the accuracy of pattern transfer. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the accuracy of pattern transfer and optimizes the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising: a substrate, a substrate mask material layer located on the substrate, and a pattern material layer located on the substrate mask material layer; forming a plurality of first mask layers extending along a first direction and spaced apart in a second direction on the pattern material layers, the first direction and the second direction being perpendicular to each other; performing ion doping on the pattern material layers using the first mask layers as masks to form a doped layer, the remaining pattern material layers serving as the pattern layer, the pattern layer and the doped layer having an etching selectivity ratio; after forming the doped layer, removing the first mask layers; after removing the first mask layers, forming a second mask layer covering the pattern layer and exposing a portion of the doped layer; removing the doped layer exposed by the second mask layer to form a first groove; after forming the first groove, removing the second mask layer; after removing the second mask layer, removing the pattern layer to form a second groove.

[0007] Optionally, the patterned material layer can be ion-doped using an ion implantation process to form the doped layer.

[0008] Optionally, in the step of ion doping the patterned material layer, the doping ions include one or both of B and C.

[0009] Optionally, the material of the first mask layer includes: an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

[0010] Optionally, the method for forming the semiconductor structure includes: forming a sidewall layer on the sidewall of the first groove before removing the patterned layer.

[0011] Optionally, the material of the sidewall layer includes TiO.

[0012] Optionally, the step of forming a sidewall layer on the sidewall of the first groove includes: forming a sidewall material layer that conformally covers the first groove and the graphic layer; removing the sidewall material layer from the bottom surface of the first groove and the top surface of the graphic layer, and using the remaining sidewall material layer located on the sidewall of the first groove as the sidewall layer.

[0013] Optionally, the sidewall material layer may be formed using atomic layer deposition or chemical vapor deposition.

[0014] Optionally, a maskless dry etching process can be used to remove the sidewall material layer on the bottom surface of the first groove and the top surface of the pattern layer.

[0015] Optionally, the material of the second mask layer includes: an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

[0016] Optionally, a wet etching process can be used to remove the patterned layer to form a second groove.

[0017] Optionally, the method for forming the semiconductor structure further includes: forming a first blocking layer that blocks the first groove in a second direction; forming a second blocking layer that blocks the second groove in a second direction; etching the substrate mask material layer using the first blocking layer, the second blocking layer, and the sidewall layer as masks to form a substrate mask layer; and etching the substrate using the first blocking layer, the second blocking layer, the sidewall layer, and the substrate mask layer as masks to form an opening in the substrate.

[0018] Optionally, the material of the first blocking layer includes TiO or silicon oxide.

[0019] Optionally, the material of the second blocking layer includes TiO or silicon oxide.

[0020] Optionally, the step of forming a first blocking layer that blocks the first groove in the second direction includes: filling the first groove with a first blocking material layer; forming a first blocking mask layer on the first blocking material layer; and etching the first blocking material layer using the first blocking mask layer as a mask to form the first blocking layer.

[0021] Optionally, the step of forming a second blocking layer that blocks the second groove in the second direction includes: filling the second groove with a second blocking material layer; forming a second blocking mask layer on the second blocking material layer; and etching the second blocking material layer using the second blocking mask layer as a mask to form the second blocking layer.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0023] In the semiconductor structure formation method provided by this invention, a plurality of first mask layers extending along a first direction and spaced apart in a second direction are formed on the patterned material layer. The patterned material layer is then ion-doped using the first mask layers as masks to form a plurality of doped layers. After forming the doped layers, the first mask layers are removed. After removing the first mask layers, a second mask layer is formed that covers the patterned layer and exposes a portion of the doped layers. The exposed doped layers of the second mask layer are removed to form a first groove. After forming the first groove, the patterned layer is removed to form a second groove. Both the first and second mask layers include an organic material layer, which is in contact with the patterned layer. The organic material layer contains organic macromolecules, and the organic macromolecules contain carbon (C). Compared to the case where five mask layers are formed sequentially on the pattern layer until the second groove is formed after removing the pattern layer, in the semiconductor structure formation method provided by the embodiments of the present invention, a first mask layer and a second mask layer are formed sequentially on the pattern layer until the second groove is formed after removing the pattern layer. Consequently, the contact time between the pattern layer and the organic material layer located thereon is less, and the carbon in the first and second mask layers is less likely to diffuse into the pattern layer. Therefore, during the removal of the pattern layer, there is less likelihood of residual pattern layer, resulting in better morphological quality of the second groove. This improves the accuracy of subsequent pattern transfer based on the second groove and is beneficial for optimizing the electrical performance of the semiconductor structure.

[0024] In an optional embodiment, the method for forming the semiconductor structure further includes: forming a first blocking layer that blocks the first groove in a second direction; forming a second blocking layer that blocks the second groove in a second direction; etching a substrate mask material layer exposed by the first and second grooves using the first blocking layer, the second blocking layer, and the sidewall layer as masks to form a substrate mask layer; and etching the substrate using the first blocking layer, the second blocking layer, the sidewall layer, and the substrate mask layer as masks to form an opening in the substrate. Because the pattern layer is less likely to remain after the removal step, the morphology of the second groove is better. During the etching process using the first blocking layer, the second blocking layer, and the sidewall layer as masks to etch the substrate mask material layer exposed by the first and second grooves, the resulting substrate mask layer has a better morphology. This results in a better morphology of the opening formed when the substrate is etched using the first blocking layer, the second blocking layer, the sidewall layer, and the substrate mask layer as masks, which is beneficial for improving the electrical performance of the semiconductor structure. Attached Figure Description

[0025] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0026] Figures 14 to 27 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0027] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0028] Figures 1 to 13 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0029] like Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 A cross-sectional view at BB shows a substrate comprising: a substrate 1, a substrate mask material layer 2 on the substrate 1, and a pattern material layer (not shown) on the substrate mask material layer 2; a first mask layer 7 is formed on the pattern material layer; ions are doped into the pattern material layer exposed by the first mask layer 7 to form a doped layer 8, and the remaining pattern material layer serves as a pattern layer 3, which includes a first pattern layer 3a and a second pattern layer 3b. The method for forming the semiconductor structure further includes: after forming the doped layer 8, removing the first mask layer 7.

[0030] like Figure 3 and Figure 4 As shown, Figure 4 for Figure 3 In the cross-sectional view at AA, after removing the first mask layer 7, a second mask layer 9 is formed on the doped layer 8 and the patterned layer 3, with the extension direction of the patterned layer 3 as the longitudinal direction. Figure 3 (in the y-direction), with the extension direction perpendicular to the graphic layer 3 as the horizontal direction ( Figure 3 (in the x-direction); using the second mask layer 9 as a mask, the first patterned layer 3a is etched to form a first opening 10 that laterally breaks the first patterned layer 3a. The method for forming the semiconductor structure further includes: after forming the first opening 10, removing the second mask layer 9.

[0031] like Figure 5 As shown, after removing the second mask layer 9, a third mask layer (not shown in the figure) is formed on the doped layer 8 and the patterned layer 3; the second patterned layer 3b is etched using the third mask layer as a mask to form a second opening 11 that laterally disconnects the other patterned layer 3.

[0032] like Figure 6 and Figure 7 As shown, Figure 7 for Figure 6In the cross-sectional view at DD, after removing the third mask layer, a fourth mask layer 13 is formed on the doped layer 8 and the patterned layer 3; the doped layer 8 is removed using the fourth mask layer 13 as a mask to form a first groove 12. The method for forming the semiconductor structure further includes: after forming the first groove 12, removing the fourth mask layer 13.

[0033] like Figure 8 As shown, Figure 8 For based on Figure 7 A schematic cross-sectional view shows a first barrier material layer 14 formed on the patterned layer 3 and the substrate mask material layer 2 exposed by the patterned layer 3.

[0034] like Figure 9 and Figure 10 As shown, Figure 10 for Figure 9 In the cross-sectional view at DD, the first barrier material layer 14 on the top of the pattern layer 3 and the surface of the substrate mask material layer 2 is removed. The remaining first barrier material layer 14 located on the sidewall of the pattern layer 3 serves as the sidewall layer 15, and the remaining first barrier material layer 14 located in the first opening 10 and the second opening 11 serves as the first barrier layer 16.

[0035] like Figure 11 and Figure 12 As shown, Figure 12 for Figure 11 In the cross-sectional view at EE, a second barrier material layer (not shown) is formed in the first groove 12; a fifth mask layer 17 is formed on the second barrier material layer; the second barrier material layer is etched using the fifth mask layer 17 as a mask to form a second barrier layer 18.

[0036] like Figure 13 As shown, the fifth mask layer 17 is removed, and after removing the fifth mask layer 17, the pattern layer 3 is removed to form the second groove 19. Subsequently, the substrate mask material layer 2 is etched using the first blocking layer 16, the second blocking layer 18, and the sidewall layer 15 as masks to form the substrate mask layer; the substrate 1 is etched using the first blocking layer 16, the second blocking layer 18, the sidewall layer 15, and the substrate mask layer as masks to form an opening in the substrate 1 for filling the interconnect structure.

[0037] The first mask layer 7, the second mask layer 9, the third mask layer, the fourth mask layer 13, and the fifth mask layer 17 each include: an organic material layer 4, an anti-reflective coating 5 on the organic material layer 4, and a photoresist layer 6 on the anti-reflective coating 5. The organic material layer 4 is in direct contact with the top of the pattern layer 3, and C in the organic material layer 4 diffuses into the pattern layer 3. During the process of removing the pattern layer 3 to form the second groove 10, the pattern layer 3 is difficult to etch, and the pattern layer 3 is prone to remain. The morphology quality of the second groove is poor. During the subsequent etching of the substrate mask material layer 2 using the first blocking layer 16, the second blocking layer 18, and the sidewall layer 15 as masks, the remaining pattern layer 3 will interfere with the formation of the substrate mask layer, resulting in poor pattern transfer accuracy and poor formation quality of the substrate mask layer. Correspondingly, the formation quality of the opening formed by continuing to etch the substrate 1 is poor, which in turn leads to poor morphology quality of the interconnect structure subsequently formed in the opening, resulting in poor electrical performance of the semiconductor structure.

[0038] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising: a substrate, a substrate mask material layer located on the substrate, and a pattern material layer located on the substrate mask material layer; forming a plurality of first mask layers extending along a first direction and spaced apart in a second direction on the pattern material layers, the first direction and the second direction being perpendicular to each other; performing ion doping on the pattern material layers using the first mask layers as masks to form a doped layer, the remaining pattern material layers serving as the pattern layer, the pattern layer and the doped layer having an etching selectivity ratio; after forming the doped layer, removing the first mask layers; after removing the first mask layers, forming a second mask layer covering the pattern layer and exposing a portion of the doped layer; removing the doped layer exposed by the second mask layer to form a first groove; after forming the first groove, removing the second mask layer; after removing the second mask layer, removing the pattern layer to form a second groove.

[0039] In the semiconductor structure formation method provided by this invention, a plurality of first mask layers extending along a first direction and spaced apart in a second direction are formed on the patterned material layer. The patterned material layer is then ion-doped using the first mask layers as masks to form a plurality of doped layers. After forming the doped layers, the first mask layers are removed. After removing the first mask layers, a second mask layer is formed that covers the patterned layer and exposes a portion of the doped layers. The exposed doped layers of the second mask layer are removed to form a first groove. After forming the first groove, the patterned layer is removed to form a second groove. Both the first and second mask layers include an organic material layer, which is in contact with the patterned layer. The organic material layer contains organic macromolecules, and the organic macromolecules contain carbon (C). Compared to the case where five mask layers are formed sequentially on the pattern layer until the second groove is formed after removing the pattern layer, in the semiconductor structure formation method provided by the embodiments of the present invention, a first mask layer and a second mask layer are formed sequentially on the pattern layer until the second groove is formed after removing the pattern layer. Consequently, the contact time between the pattern layer and the organic material layer located thereon is less, and the carbon in the first and second mask layers is less likely to diffuse into the pattern layer. Therefore, during the removal of the pattern layer, there is less likelihood of residual pattern layer, resulting in better morphological quality of the second groove. This improves the accuracy of subsequent pattern transfer based on the second groove and is beneficial for optimizing the electrical performance of the semiconductor structure.

[0040] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 14 to 27 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] refer to Figure 14 and Figure 15 , Figure 15 for Figure 14 A cross-sectional view at BB shows a substrate including a substrate 100, a substrate mask material layer 101 on the substrate 100, and a pattern material layer 102 on the substrate mask material layer 101.

[0043] In this embodiment, the substrate 100 includes a dielectric layer. The substrate 100 is subsequently etched to form an opening in the dielectric layer.

[0044] The dielectric layer is made of a low-k dielectric material, which helps to reduce the parasitic capacitance between the subsequently formed metal interconnects, thereby reducing the RC delay in the later stage.

[0045] In this embodiment, the dielectric layer is made of SiCOH. In other embodiments, the dielectric layer may also be made of silicon oxide.

[0046] It should be noted that the substrate 100 also includes a transistor, which is typically formed at the bottom of the dielectric layer. The transistor includes a gate structure and source / drain structures located on both sides of the gate structure. A contact hole plug (not shown in the figure) is also formed in the substrate to contact the source / drain structures.

[0047] The substrate mask material layer 101 is used to prepare for subsequent etching of the dielectric layer. The substrate mask material layer 101 has high etching resistance, and during the subsequent etching of the dielectric layer, the materials of the dielectric layer and the substrate mask material layer 101 have a large etching selectivity ratio.

[0048] In this embodiment, the substrate mask material layer 101 is made of silicon titanate. In other embodiments, the substrate mask material layer may also be made of silicon nitride or amorphous silicon.

[0049] The patterned material layer 102 is used to provide a process platform for the subsequent formation of the etched substrate mask material layer 101.

[0050] In this embodiment, the patterned material layer 102 is made of amorphous silicon (a-Si). In other embodiments, the patterned material layer may also be made of silicon oxide. Amorphous silicon is a commonly used material in manufacturing processes, and its formation process is simple, which helps to reduce the manufacturing cost of semiconductor structures.

[0051] refer to Figure 16 and Figure 17 , Figure 17 for Figure 16 In the cross-sectional view at BB, a plurality of first mask layers 108 extending along a first direction (y direction) and spaced apart in a second direction (x direction) are formed on the patterned material layer 102. Figure 17 As shown in the figure, the first direction and the second direction are perpendicular to each other.

[0052] The first mask layer 108 is used as a doping mask for the subsequent formation of a doped layer.

[0053] In this embodiment, the first mask layer 108 includes an organic material layer 105, an anti-reflective coating 106 on the organic material layer 105, and a photoresist layer 107 on the anti-reflective coating 106.

[0054] In this embodiment, the organic material layer 105 includes ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), or SOC (spinon carbon) material.

[0055] In this embodiment, the material of the anti-reflective coating 106 includes BARC (bottom anti-reflective coating) material or Si-ARC (silicon anti-reflective coating) material.

[0056] Continue to refer to Figure 16 and Figure 17 Using the first mask layer 108 as a mask, the pattern material layer 102 is ion-doped to form a doped layer 103, and the remaining pattern material layer 102 serves as a pattern layer 104. The pattern layer 104 and the doped layer 103 have an etching selectivity ratio.

[0057] Ions are doped into the patterned material layer 102, modifying the material of the doped layer 102. The etching resistance of the doped layer 103 is greater than that of the patterned layer 104. After the doped layer 103 is formed, the first mask layer 108 is removed. After removing the first mask layer 108, a second mask layer is formed, covering the patterned layer 104 and exposing part of the doped layer 103. The doped layer is removed using the second mask layer as a mask to form a first groove. During the formation of the first groove, part of the doped layer 103 is retained. During the subsequent removal of the patterned layer 104 to form the second groove, the remaining doped layer 103 is less likely to be damaged.

[0058] In this embodiment, the patterned material layer 102 is ion-doped using an ion implantation process to form a doped layer 103. Ion implantation is characterized by its simplicity and low cost.

[0059] In this embodiment, during the step of ion doping the patterned material layer 102, the doping ions include one or both of B and C. Both B and C can modify the material of the patterned material layer 102, and the etching resistance of the doped layer 103 is greater than that of the patterned layer 104.

[0060] In this embodiment, during the process of ion doping the patterned material layer 102 to form the doped layer 103, although the top of the first mask layer 108 is damaged, the photoresist layer 107 still retains a portion of its thickness. In other embodiments, during the process of ion doping the patterned material layer to form the doped layer, the photoresist layer and a portion of the anti-reflective coating can also be removed.

[0061] The method for forming the semiconductor structure further includes: after forming the doped layer 103, removing the first mask layer 108. Removing the first mask layer 108 prepares for the subsequent formation of the second mask layer.

[0062] In this embodiment, the first mask layer 108 is removed by an ashing process.

[0063] refer to Figure 18 and Figure 19 , Figure 19 for Figure 18 In the cross-sectional view at BB, after removing the first mask layer 108, a second mask layer 113 is formed that covers the pattern layer 104 and exposes part of the doped layer 103.

[0064] The second mask layer 113 serves as an etching mask for subsequent removal of a portion of the doped layer 103.

[0065] In this embodiment, the second mask layer 113 includes an organic material layer 105, an anti-reflective coating 106 on the organic material layer 105, and a photoresist layer 107 on the anti-reflective coating 106.

[0066] In this embodiment, the organic material layer 105 includes ODL material, DUO material, or SOC material.

[0067] In this embodiment, the material of the anti-reflective coating 106 includes BARC material or Si-ARC material.

[0068] Continue to refer to Figure 18 and Figure 19 Remove the doped layer 103 exposed by the second mask layer 113 to form the first groove 109.

[0069] The first groove 109 is formed in preparation for the subsequent formation of a sidewall layer on the sidewall of the first groove 109.

[0070] In this embodiment, a portion of the doped layer 103 is removed using a dry etching process with the second mask layer 113 as a mask to form the first groove 109. The dry etching process has anisotropic etching characteristics, providing good control over the etching profile and achieving highly accurate pattern transformation. This helps ensure that the morphology of the first groove 109 meets process requirements and also improves the removal efficiency of the doped layer 103. Furthermore, during the process of removing the doped layer 103 and forming the first groove 109 using the dry etching process, the top of the substrate mask material layer 101 can be used as the etching stop position, reducing damage to other film structures.

[0071] It should be noted that because the second mask layer 113 exposes part of the doped layer 103, after removing the doped layer 103 exposed by the second mask layer 113, a portion of the doped layer 103 is still retained, and the retained doped layer 103 is not shown in the figure.

[0072] The method for forming the semiconductor structure further includes: after forming the first groove 109, removing the second mask layer 113.

[0073] The second mask layer 113 is removed to expose the pattern layer 104, which prepares for the removal of the pattern layer 104 and provides process space for the subsequent formation of the sidewall material layer.

[0074] In this embodiment, an ashing process is used to remove the second mask layer 113.

[0075] refer to Figures 20 to 23 , Figure 21 for Figure 20 Cross-sectional view at DD Figure 23 for Figure 22 In the cross-sectional view at DD, the method for forming the semiconductor structure includes: after removing the second mask layer 113 and before removing the pattern layer 104, forming a sidewall layer 110 on the sidewall of the first recess 109 (e.g., ...). Figure 23 (As shown).

[0076] The graphic layer 104 is then removed to form a second groove, and the sidewall layer 110 is used to block the first groove 109 and the second groove.

[0077] Specifically, the material of the sidewall layer 110 includes TiO.

[0078] The step of forming a sidewall layer 110 on the sidewall of the first groove 109 includes: forming a sidewall material layer 111 that conformally covers the first groove 109 and the graphic layer 104; removing the sidewall material layer 111 from the bottom surface of the first groove 109 and the top surface of the graphic layer 104, and the remaining sidewall material layer 111 located on the sidewall of the first groove 109 as the sidewall layer 110.

[0079] In this embodiment, the sidewall material layer 111 is formed using chemical vapor deposition (CVD). CVD is a method for generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements. It has good step coverage and allows for control over the deposition thickness of the sidewall material layer 111, resulting in a high purity film. In other embodiments, atomic layer deposition (ALD) can also be used to form the sidewall material layer.

[0080] In this embodiment, a maskless dry etching process is used to remove the sidewall material layer 111 on the bottom surface of the first groove 109 and the top surface of the pattern layer 104. The maskless dry etching process has the characteristic of anisotropic etching, which is beneficial to ensure that the sidewall material layer 101 on the top surface of the pattern layer 104 and the substrate mask material layer 101 is completely removed while the damage to the sidewall material layer 101 on the sidewall of the pattern layer 104 is small. This makes it difficult to reduce the thickness of the sidewall layer 110 formed on the sidewall of the first groove 109, thereby saving a mask and reducing the process cost of forming the sidewall layer 110.

[0081] refer to Figure 24 and Figure 25 , Figure 25 for Figure 24 In the cross-sectional view at DD, after removing the second mask layer 113, the pattern layer 104 is removed to form the second groove 112.

[0082] In the semiconductor structure formation method provided in this embodiment of the invention, a plurality of first mask layers 108 extending along a first direction and spaced apart in a second direction are formed on the patterned material layer 102. The patterned material layer 102 is ion-doped using the first mask layers 108 as masks to form a plurality of doped layers 103. After forming the doped layers 103, the first mask layers 108 are removed. After removing the first mask layers 108, a second mask layer 113 is formed that covers the patterned layer 104 and exposes a portion of the doped layers 103. The doped layers 103 exposed by the second mask layer 113 are removed to form a first groove 109. After forming the first groove 109, the patterned layer 104 is removed to form a second groove 112. Both the first mask layer 108 and the second mask layer 113 include an organic material layer. The organic material layer is in contact with the pattern layer 104. The organic material layer contains organic macromolecules, and the organic macromolecules contain carbon. Compared with the case where five mask layers are formed on the pattern layer until the pattern layer is removed and the second groove is formed, in the semiconductor structure formation method provided in this embodiment of the invention, the first mask layer 108 and the second mask layer 113 are formed on the pattern layer 104 until the pattern layer 104 is removed and the second groove 112 is formed. The contact time between the pattern layer 104 and the organic material layer thereon is shorter. Consequently, the carbon in the first mask layer 108 and the second mask layer 113 is less likely to diffuse into the pattern layer 104. Therefore, during the removal of the pattern layer 104, the pattern layer 104 is less likely to have residues, resulting in better morphological quality of the second groove 112. This improves the accuracy of subsequent pattern transfer based on the second groove 112 and optimizes the electrical performance of the semiconductor structure.

[0083] In this embodiment, a wet etching process is used to remove the pattern layer 104 to form the second groove 112. The wet etching process is isotropic etching, which has a high etching rate, is simple to operate, and has low process cost.

[0084] Specifically, the material of the patterned layer 104 includes amorphous silicon, and the corresponding wet etching solution includes tetramethylammonium hydroxide (TMAH) solution.

[0085] It should be noted that during the removal of the pattern layer 104, because the etching resistance of the doped layer 103 is greater than that of the pattern layer 104, the doped layer 103 that is exposed during the removal of the second mask layer 113 is not easily damaged.

[0086] It should also be noted that a sidewall layer 110 is formed on the sidewall of the first groove 109. Correspondingly, in the step of removing the graphic layer 104 to form the second groove 112, the first groove 109 and the second groove 112 are separated by the sidewall layer 110.

[0087] refer to Figure 26 The method for forming the semiconductor structure further includes: forming a first blocking layer 114 that blocks the first groove 109 in a second direction (x direction), wherein the second direction is perpendicular to the first direction.

[0088] The first blocking layer 114 is used to block the first groove 109.

[0089] In this embodiment, the material of the first blocking layer 114 includes silicon oxide. In other embodiments, the material of the first blocking layer may also include TiO.

[0090] The step of forming a first blocking layer 114 that blocks the first groove 109 in the second direction includes: filling the first groove 109 with a first blocking material layer (not shown in the figure); forming a first blocking mask layer (not shown in the figure) on the first blocking material layer; and etching the first blocking material layer with the first blocking mask layer as a mask to form the first blocking layer 114.

[0091] In this embodiment, the first blocking material layer is formed at a relatively low temperature, and the material of the first blocking material layer is LTO (low temperature oxide). This material has good filling properties, which is beneficial to improving the filling quality of the first blocking material layer in the first groove 109. Moreover, this material is easy to remove, which reduces the difficulty of etching to form the first blocking layer 114.

[0092] Continue to refer to Figure 26 A second blocking layer 115 is formed to block the second groove 112 in the second direction.

[0093] In this embodiment, the material of the second blocking layer 115 includes silicon oxide. In other embodiments, the material of the second blocking layer includes TiO.

[0094] The step of forming a second blocking layer 115 that blocks the second groove 112 in the second direction includes: filling the second groove 112 with a second blocking material layer (not shown in the figure); forming a second blocking mask layer (not shown in the figure) on the second blocking material layer; and etching the second blocking material layer with the second blocking mask layer as a mask to form the second blocking layer 115.

[0095] In this embodiment, the second blocking material layer is formed at a relatively low temperature, specifically, the material of the second blocking material layer is LTO (low temperature oxide). This material has good filling properties, which is beneficial to improving the filling quality of the second blocking material layer in the second groove 112. Moreover, this material is easy to remove, which reduces the difficulty of etching to form the second blocking layer 115.

[0096] refer to Figure 27 , Figure 27 For based on Figure 25 The cross-sectional view shows that the method for forming the semiconductor structure further includes: etching the substrate mask material layer 101 exposed by the first groove 109 and the second groove 112 using the sidewall layer 110, the first blocking layer 114, and the second blocking layer 115 as masks to form a substrate mask layer 118; etching the substrate 100 using the sidewall layer 110, the first blocking layer 114, the second blocking layer 115, and the substrate mask layer 118 as masks to form a plurality of spaced openings 116 and substrate spacers 117 located between the openings 116.

[0097] Because the pattern layer 104 is less likely to remain after the removal step, the morphology of the second groove 112 is better. During the etching of the substrate mask material layer 102 exposed by the first groove 109 and the second groove 112 using the first blocking layer 114, the second blocking layer 115 and the sidewall layer 110 as masks, the morphology of the substrate mask layer 118 formed is better. This results in better morphology of the opening 116 formed by etching the substrate 100 using the first blocking layer 114, the second blocking layer 115, the sidewall layer 110 and the substrate mask layer 118 as masks, which is beneficial to improving the electrical performance of the semiconductor structure.

[0098] Subsequent processes form the subsequent interconnect structure within the opening 116. Specifically, the opening 116 is located within the dielectric layer.

[0099] In this embodiment, the substrate mask material layer 101 is etched using a dry etching process with the sidewall layer 110, the first blocking layer 114, and the second blocking layer 115 as masks to form a substrate mask layer 118. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which is beneficial for ensuring that the morphology of the substrate mask layer 118 meets the process requirements.

[0100] In this embodiment, the substrate 100 is etched using a dry etching process with the sidewall layer 110, the first blocking layer 114, the second blocking layer 115, and the substrate mask layer 118 as masks to form multiple spaced openings 116 and substrate spacers 117 located between the openings 116. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the openings 116 meets process requirements. Furthermore, the dry etching process allows for precise control of the formation depth of the openings 116.

[0101] The interconnect structure formed subsequently is located in the opening 116. The dielectric layer is made of a low-k dielectric material, which helps to reduce the parasitic capacitance between the interconnect structures and thus helps to reduce the RC delay in the later stage.

[0102] The method for forming the semiconductor structure further includes: after forming the opening 116, removing the sidewall layer 110, the first blocking layer 114, the second blocking layer 115, and the substrate mask layer 118.

[0103] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising: a substrate, a substrate mask material layer on the substrate, and a patterning material layer on the substrate mask material layer; Multiple first mask layers extending along a first direction and spaced apart in a second direction are formed on the patterned material layer, wherein the first direction and the second direction are perpendicular to each other. Using the first mask layer as a mask, the pattern material layer is ion-doped to form a doped layer, and the remaining pattern material layer serves as the pattern layer. The pattern layer and the doped layer have an etching selectivity ratio. After the doped layer is formed, the first mask layer is removed; After removing the first mask layer, a second mask layer is formed that covers the patterned layer and exposes a portion of the doped layer; Remove the doped layer exposed by the second mask layer to form a first groove; After the first groove is formed, the second mask layer is removed; After removing the second mask layer, the pattern layer is removed to form the second groove; The method for forming the semiconductor structure includes: forming a sidewall layer on the sidewall of the first groove before removing the patterned layer; The method for forming the semiconductor structure further includes: forming a first blocking layer that blocks the first groove in a second direction; forming a second blocking layer that blocks the second groove in a second direction; etching a substrate mask material layer exposed by the first and second grooves using the first blocking layer, the second blocking layer, and the sidewall layer as masks to form a substrate mask layer; and etching the substrate using the first blocking layer, the second blocking layer, the sidewall layer, and the substrate mask layer as masks to form an opening in the substrate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The patterned material layer is ion-doped using an ion implantation process to form the doped layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of ion doping the patterned material layer, the doping ions include one or both of B and C.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first mask layer includes: an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The material of the sidewall layer includes TiO.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a sidewall layer on the sidewall of the first groove includes: A sidewall material layer is formed to conformally cover the first groove and the graphic layer; Remove the sidewall material layer from the bottom surface of the first groove and the top surface of the graphic layer, and the remaining sidewall material layer located on the sidewall of the first groove shall serve as the sidewall layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The sidewall material layer is formed using atomic layer deposition or chemical vapor deposition.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The sidewall material layer on the bottom surface of the first groove and the top of the pattern layer is removed using a maskless dry etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second mask layer includes: an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The patterned layer is removed using a wet etching process to form a second groove.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first blocking layer includes TiO or silicon oxide.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second blocking layer includes TiO or silicon oxide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first blocking layer that blocks the first groove in the second direction includes: A first blocking material layer is filled into the first groove; A first blocking mask layer is formed on the first blocking material layer; The first blocking material layer is etched using the first blocking mask layer as a mask to form the first blocking layer.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second blocking layer that blocks the second groove in the second direction includes: A second blocking material layer is filled into the second groove; A second blocking mask layer is formed on the second blocking material layer; The second blocking material layer is etched using the second blocking mask layer as a mask to form the second blocking layer.

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