Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface therebetween, incorporating a modifying ion at the first interface, the modifying ion being bonded with an ion in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than before the modifying ion is incorporated, the first chemical bond formed by a defect ion and an ion in the gate dielectric layer (or the gate oxide layer) at the first interface being less likely to be broken, reducing the probability of interface trap charge, thereby reducing the interface state density, reducing the threshold voltage and the saturated drain current of the device from drifting, and improving the negative bias temperature instability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a forming method of a semiconductor structure. BACKGROUND

[0002] With the continuous development of integrated circuit process technology, in order to improve the integration of integrated circuits, while improving the working speed of the device and reducing power consumption, the feature size of MOS devices is continuously reduced, and MOS devices are facing a series of challenges. At present, the semiconductor industry uses HK dielectric material to replace SiON and uses metal gate to replace polysilicon gate technology, that is, high-k metal gate (HKMG) technology, to solve the problems of threshold voltage drift, polysilicon gate depletion effect, excessively high gate resistance and Fermi level pinning.

[0003] However, with the further reduction of the feature size of the device, the HKMG technology also faces continuous challenges, such as the negative bias temperature instability (NBTI) problem in PMOS devices and the time dependent dielectric breakdown (TDDB) problem of the ultra-thin gate oxide layer in NMOS devices.

[0004] The existing HKMG process technology needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a forming method of a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer located on the gate oxide layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface; incorporating a modification ion at the first interface, the modification ion being bonded to an ion in the gate dielectric layer or the gate oxide layer to form a first chemical bond at the first interface.

[0007] Optionally, the modification ion is also doped into the gate dielectric layer, and the modification ion is bonded to an ion in the gate dielectric layer to form a second chemical bond.

[0008] Optionally, the gate oxide layer and the substrate also have a second interface, and the modification ion is also doped to the second interface.

[0009] Optionally, the modification ion is also doped into the gate oxide layer.

[0010] Optionally, the method of incorporating the modified ions at the first interface comprises: forming a first sacrificial layer on the gate dielectric layer; performing plasma treatment on the first sacrificial layer to implant the modified ions into the first interface; after the plasma treatment on the first sacrificial layer, performing a first annealing treatment on the gate dielectric layer and the gate oxide layer; and removing the first sacrificial layer after the first annealing treatment.

[0011] Optionally, the material of the first sacrificial layer comprises titanium nitride.

[0012] Optionally, before the incorporation of the modified ions at the first interface, the method further comprises: forming a cover layer on the gate dielectric layer; and the material of the cover layer comprises titanium nitride.

[0013] Optionally, after the incorporation of the modified ions at the first interface, the method further comprises: forming an etching stop layer on the cover layer; and the material of the etching stop layer comprises tantalum nitride.

[0014] Optionally, after the incorporation of the modified ions at the first interface and before the formation of the etching stop layer, the method further comprises: performing a modification treatment on the cover layer.

[0015] Optionally, the modification treatment comprises: forming a modified material layer on the cover layer; after the formation of the modified material layer, performing a third annealing treatment on the modified material layer and the cover layer to make the modified material layer react with the cover layer to form a barrier layer; and removing the unreacted modified material layer after the third annealing treatment.

[0016] Optionally, after the formation of the etching stop layer, the method further comprises: forming a work function layer on the etching stop layer, the work function layer being an N-type or P-type work function material; the P-type work function material comprising one or more of tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride; and the N-type work function material comprising one or more of titanium aluminide, titanium aluminide carbide, tantalum aluminide nitride, titanium aluminide nitride, tantalum nitride carbide, and aluminum nitride.

[0017] Optionally, the method of incorporating the modified ions at the first interface comprises: forming a second sacrificial layer containing the modified ions on the surface of the gate oxide layer; after the formation of the second sacrificial layer, performing a second annealing treatment on the second sacrificial layer, the gate oxide layer, and the gate dielectric layer; and removing the second sacrificial layer after the second annealing treatment.

[0018] Optionally, the material of the second sacrificial layer comprises tungsten.

[0019] Optionally, the process of forming the second sacrificial layer comprises a chemical vapor deposition process or an atomic layer deposition process.

[0020] Optionally, before the modification ions are doped at the first interface, the method further comprises: forming a cover layer on the gate dielectric layer; and the material of the cover layer comprises titanium nitride.

[0021] Optionally, after the cover layer is formed, before the modification ions are doped at the first interface, the method further comprises: performing a modification treatment on the cover layer.

[0022] Optionally, the modification treatment comprises: forming a modification material layer on the cover layer; after the modification material layer is formed, performing a third annealing treatment on the modification material layer and the cover layer, so that the modification material layer and the cover layer react to form a barrier layer; and after the barrier layer is formed, removing the unreacted modification material layer.

[0023] Optionally, after the modification ions are doped at the first interface, the method further comprises: forming an etching stop layer on the cover layer; and the material of the etching stop layer comprises tantalum nitride.

[0024] Optionally, after the etching stop layer is formed, the method further comprises: forming a work function layer on the etching stop layer, the work function layer being an N-type or P-type work function material; the P-type work function material comprises one or more of tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride; and the material of the N-type work function material comprises one or more of titanium aluminum, titanium aluminum carbide, tantalum aluminum nitride, titanium aluminum nitride, tantalum carbon nitride, and aluminum nitride.

[0025] Optionally, the first chemical bond comprises hafnium-fluorine bond and silicon-fluorine bond; and the second chemical bond comprises silicon-fluorine bond.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0027] In the method for forming a semiconductor structure provided by the technical scheme, the gate dielectric layer and the gate oxide layer have a first interface, modification ions are doped at the first interface, the modification ions are bonded with the ions in the gate dielectric layer or the gate oxide layer, a first chemical bond is formed at the first interface, the bond combination ability of the first chemical bond is stronger than that before the modification ions are doped, the first chemical bond formed by the defect ions and the ions in the gate dielectric layer (or the gate oxide layer) at the first interface is not easy to be broken, the probability of interface trap charge is reduced, the interface state density is reduced, the threshold voltage and the saturated drain current of the device are less likely to drift, and the negative bias temperature instability is improved.

[0028] Further, the modified ions also dope into the gate dielectric layer, the modified ions bond with ions in the gate dielectric layer to form second chemical bonds. The second chemical bonds have stronger bond energy, which is used to passivate defects in the gate dielectric layer, reduce the probability of current tunneling caused by defects, and thus improve the insulation breakdown performance of the device over time.

[0029] Further, there is also a second interface between the gate oxide layer and the substrate, and the modified ions also dope into the second interface to reduce the probability of interface trap charges of the gate oxide layer and the substrate, thus reducing the interface state density, reducing the threshold voltage and saturation drain current drift of the device, and improving the negative bias temperature instability.

[0030] Further, the gate dielectric layer includes a high-K dielectric material, the high-K dielectric material includes one or more of hafnium oxide, hafnium silicate, and hafnium silicon oxynitride; the material of the gate oxide layer includes silicon oxide; and the modified ions include fluorine ions. The first chemical bonds include hafnium-fluorine bonds and silicon-fluorine bonds, and the bond energy of the hafnium-fluorine bonds and the silicon-fluorine bonds is higher than that of hydrogen-silicon bonds. Therefore, the interface state density at the first interface can be reduced, the threshold voltage and saturation drain current drift of the device can be reduced, and the negative bias temperature instability can be improved.

[0031] Further, the modified ions include fluorine ions, and the second chemical bonds formed include silicon-fluorine bonds, which can reduce the interface state density of the second interface, reduce the threshold voltage and saturation drain current drift of the device, and improve the negative bias temperature instability. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figures 1 to 3 is a cross-sectional schematic view of a semiconductor structure formation process;

[0033] Figures 4 to 11 is a structure schematic view of each step of the semiconductor structure formation method in an embodiment of the present application;

[0034] Figures 12 to 16 is a structure schematic view of each step of the semiconductor structure formation method in another embodiment of the present application. DETAILED DESCRIPTION

[0035] It should be noted that the "surface", "upper", and "lower" in the present specification are used to describe the relative positional relationship in space, and do not necessarily mean direct contact.

[0036] As described in the background, the performance of the semiconductor structure formed by using the existing HKMG technology needs to be improved. Now, a semiconductor structure will be described and analyzed.

[0037] Figures 1 to 3is a sectional view of a semiconductor structure forming process.

[0038] Referring to Figure 1 , a substrate 101 is provided; a gate oxide material layer 102 is formed on the substrate 101; a high-K dielectric material layer 103 is formed on the gate oxide material layer 102; a covering material layer 104 is formed on the high-K dielectric material layer 103; an etching stop material layer 105 is formed on the covering material layer 104; a work function material layer 106 is formed on the etching stop material layer 105.

[0039] Referring to Figure 2 , a polysilicon material layer 107 is formed on the work function material layer 106; a hard mask layer 108 is formed on the polysilicon material layer 107, and the hard mask layer 108 exposes part of the polysilicon material layer 107.

[0040] Referring to Figure 3 , the polysilicon material layer 107, the work function material layer 106, the etching stop material layer 105, the covering material layer 104, the high-K dielectric material layer 103 and the gate oxide material layer 102 are etched until the surface of the substrate 101 is exposed, to form a gate structure 109, which includes a gate oxide layer 110 on the substrate 101, a high-K dielectric layer 111 on the gate oxide layer 110, a covering layer 112 on the high-K dielectric layer 111, an etching stop layer 113 on the covering layer 112, a work function layer 114 on the etching stop layer 113, and a gate layer 115 on the work function layer 114.

[0041] The above method is used in HKMG technology, to form a gate dielectric layer of an NMOS or PMOS device. In use of the device, especially the PMOS device, under the action of a bias gate voltage and high temperature, hydrogen ions introduced in the process of forming the gate oxide layer 110 break the hydrogen-silicon bonds at the interface between the gate oxide layer 110 and the high-K dielectric layer due to the diffusion of the hydrogen ions, to form carrier trapping centers, thus causing the threshold voltage and saturation drain current of the device to drift, i.e. negative bias temperature instability. The negative bias temperature instability further reduces the speed of the transistor and increases the mismatch of the transistor, eventually leading to the failure of the circuit, thus directly affecting the service life of the device.

[0042] In order to solve the above problems, the application provides a semiconductor structure forming method, wherein the gate dielectric layer and the gate oxide layer have a first interface, a modified ion is doped at the first interface, the modified ion is bonded with an ion in the gate dielectric layer or the gate oxide layer, a first chemical bond is formed at the first interface, the bond combination ability of the first chemical bond is stronger than that before the modified ion is doped, the first chemical bond formed by the defect ion at the first interface and the ion in the gate dielectric layer (or the gate oxide layer) is not easy to be broken, the probability of interface trap charge is reduced, the interface state density is reduced, the threshold voltage and the saturated drain current of the device are prevented from drifting, and the negative bias temperature instability is improved.

[0043] In order to make the above-mentioned objects, characteristics and beneficial effects of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0044] Figures 4 to 11 is a structural schematic diagram of each step of the semiconductor structure forming method in an embodiment of the application.

[0045] Please refer to Figure 4 , a substrate 200 is provided.

[0046] Subsequently, a multilayer structure between the gate and the substrate 200 is formed on the substrate 200. In this embodiment, the multilayer structure between the gate and the substrate is formed in a polysilicon gate process technology. In other embodiments, the multilayer structure between the gate and the substrate is also formed in a metal replacement gate process.

[0047] The substrate 200 can be a planar structure or a three-dimensional structure. In this embodiment, the substrate 200 is a planar structure. In another embodiment, the substrate is located on the top surface of part of a base, and has an opening in an interlayer dielectric layer on the base, the bottom of the opening exposing the surface of the substrate. In yet another embodiment, the substrate is a three-dimensional structure, and the substrate has a fin portion.

[0048] The material of the substrate 200 can be single crystal silicon, polycrystalline silicon or amorphous silicon, and can also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, etc. In this embodiment, the material of the substrate 200 includes silicon.

[0049] Please refer to Figure 5 , a gate oxide layer 201 and a gate dielectric layer 202 located on the gate oxide layer 201 are formed on the substrate 200, and the gate dielectric layer 202 and the gate oxide layer 201 have a first interface 203.

[0050] The gate oxide layer 201 and the substrate 200 also have a second interface 204.

[0051] The material of the gate oxide layer 201 includes silicon oxide. The gate oxide layer 201 can effectively reduce the interface defects between the substrate 200 and the gate dielectric layer 202, thereby improving the interface state and facilitating the improvement of the performance of the formed semiconductor structure.

[0052] The material of the gate dielectric layer 202 includes high-K dielectric material, which includes one or more of hafnium oxide, hafnium silicate, and hafnium silicon oxynitride. In this embodiment, the material of the gate dielectric layer 202 is hafnium oxide. The gate dielectric layer 202 is used to reduce the quantum tunneling effect of the gate dielectric layer 202, improve the gate leakage current, and improve the performance of the device.

[0053] The formation process of the gate oxide layer 201 includes a chemical vapor deposition process. The hydrogen ions introduced during the formation of the gate oxide layer 201 cause the hydrogen-silicon bond at the interface of the gate oxide layer 201 and the high-K dielectric layer (gate dielectric layer 202) to break due to the intensified diffusion of hydrogen ions, forming carrier trapping centers, thereby causing the threshold voltage and saturation drain current of the device to drift, i.e., negative bias temperature instability.

[0054] Subsequently, modified ions are doped at the first interface 203, which bond with the ions in the gate dielectric layer 202 or the gate oxide layer 201, forming first chemical bonds at the first interface 203, which have stronger bond strength than before the modified ions are doped. The first chemical bonds (i.e., hydrogen-silicon bonds) formed by the defect ions at the first interface 203 and the ions in the gate dielectric layer 202 (or the gate oxide layer 201) are not easily broken, which can reduce the probability of generating trap charges at the first interface 203, thereby reducing the interface state density of the first interface 203, reducing the phenomenon of threshold voltage and saturation drain current drift of the device, and improving negative bias temperature instability.

[0055] Please refer to Figure 6 Before the modified ions are doped at the first interface 203, a cover layer 205 is also formed on the gate dielectric layer 202.

[0056] The material of the cover layer 205 includes titanium nitride. The cover layer 205 is used to solve the problem of polysilicon gate depletion in the metal-embedded polysilicon gate process.

[0057] Subsequently, modified ions are doped at the first interface 203. The method of doping modified ions at the first interface 203 is described in Figures 7 to 8 .

[0058] Please refer to Figure 7A first sacrificial layer 206 is formed on the gate dielectric layer 202; the first sacrificial layer 206 is subjected to plasma treatment so that the modified ions 207 are implanted at the first interface 203.

[0059] In this embodiment, specifically, the first sacrificial layer 206 is formed on the cap layer 205.

[0060] In another embodiment, after the first interface is doped with the modified ions, a cap layer is formed on the gate dielectric layer, and the first sacrificial layer is directly formed on the gate dielectric layer.

[0061] The forming process of the first sacrificial layer 206 includes an atomic layer deposition process.

[0062] The material of the first sacrificial layer 206 includes titanium nitride. The first sacrificial layer 206 is used to reduce damage to the gate dielectric layer 202 during the plasma treatment process.

[0063] The modified ions 207 include fluorine ions; the modified ions 207 include one or more of NF3, CHF3, CH3F, and C4F6. In this embodiment, the modified ions 207 are NF3.

[0064] The process parameters of the plasma treatment process include: a radio frequency power range of 150 to 500 watts, an ion gas containing fluorine ions is used, and a pressure range of 0.1 to 10 torr.

[0065] Please refer to Figure 8 After the first sacrificial layer 206 is subjected to the plasma treatment, the gate dielectric layer 202 and the gate oxide layer 201 are subjected to a first annealing treatment; after the first annealing treatment, the first sacrificial layer 206 is removed.

[0066] The process parameters of the first annealing treatment process include: a temperature range of 100 to 1000 degrees Celsius, and an annealing time range of 10 to 60 seconds. The first annealing treatment process is used to diffuse the modified ions 207 from the first interface 203 to the gate oxide layer and the second interface 204, and to form chemical bonds between the modified ions 207 and the ions in the gate dielectric layer 202, the gate oxide layer 201, the first interface 203, and the second interface 204.

[0067] In this embodiment, the modified ions 207 are bonded to the ions in the gate dielectric layer 202 or the gate oxide layer 201 to form a first chemical bond at the first interface 203, and the first chemical bond includes hafnium-fluorine bonds and silicon-fluorine bonds.

[0068] In this embodiment, the modified ions 207 are also doped to the second interface 204.

[0069] Through the first annealing process, the modified ions 207 are also doped into the second interface 204, and the modified ions 207 combine with silicon ions in the substrate 200 or the gate oxide layer 201 at the second interface 204 to form second chemical bonds, i.e. silicon-fluorine bonds, which have a bond energy greater than that of hydrogen-silicon bonds, and thus are not easily broken relative to hydrogen-silicon bonds, reducing the probability of the second interface 204 generating trap charges, thereby reducing the interface state density of the second interface 204, reducing the threshold voltage and saturation drain current drift of the device, and improving the negative bias temperature instability of the formed device.

[0070] In this embodiment, the modified ions 207 are also doped into the gate dielectric layer 202, and the modified ions 207 are bonded to ions in the gate dielectric layer 202 to form second chemical bonds. The second chemical bonds include silicon-fluorine bonds, and the second chemical bonds have a strong bond energy, which is used to passivate defects in the gate dielectric layer 202, reducing the probability of current tunneling caused by defects forming traps, thereby improving the time-dependent dielectric breakdown performance of the device.

[0071] In this embodiment, the modified ions 207 are also doped into the gate oxide layer 201. The modified ions 207 bond to ions in the gate oxide layer 201 to form strong chemical bonds, which are used to passivate defects in the gate oxide layer 201, reducing the probability of current tunneling caused by defects forming traps, thereby improving the time-dependent dielectric breakdown performance of the device.

[0072] The process for removing the first sacrificial layer 206 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the first sacrificial layer 206 is a wet etching process, and the chemical solution used in the wet etching process includes H2O2. The wet etching process is advantageous in reducing etching damage to the gate dielectric layer 202 during the removal of the first sacrificial layer 206.

[0073] Subsequently, an etching stop layer is formed on the cover layer 205. After the modified ions 207 are doped at the first interface 203, the cover layer 205 is subjected to a modification process before the etching stop layer is formed. The modification process of the cover layer 205 is described in detail in the following embodiments. Figures 9 to 10 .

[0074] Please refer to Figure 9 , a modified material layer 208 is formed on the cover layer 205.

[0075] The material of the modified material layer 208 includes amorphous silicon. The modified material layer 208 is used to modify the cover layer 205 later to form a barrier layer.

[0076] The thickness of the modified material layer 208 ranges from 10 angstroms to 150 angstroms.

[0077] The forming process of the modified material layer 208 includes a chemical vapor deposition process.

[0078] Please refer to Figure 10 After the modified material layer 208 is formed, the modified material layer 208 and the cover layer 205 are subjected to a third annealing process, so that the modified material layer 208 and the cover layer 205 react to form a barrier layer 209; after the third annealing process, the unreacted modified material layer 208 is removed.

[0079] The process parameters of the third annealing process include that the annealing temperature ranges from 850 degrees Celsius to 1050 degrees Celsius.

[0080] The material of the barrier layer 209 includes titanium silicon nitride. In this embodiment, the material of the modified material layer 208 is amorphous silicon, the material of the cover layer 205 is titanium nitride, and therefore the material of the barrier layer 209 formed by the reaction of the modified material layer 208 and the cover layer 205 is titanium silicon nitride.

[0081] Subsequently, an etching stop layer is formed on the cover layer 205, and a work function layer is formed on the etching stop layer. The barrier layer 209 is used to block the diffusion of ions in the work function layer into the gate dielectric layer 202, reduce the defect density in the gate dielectric layer 202, and improve the breakdown performance of the device, especially the time-varying breakdown performance of the NMOS device.

[0082] The process of removing the unreacted modified material layer 208 includes one of a dry etching process and a wet etching process, or a combination of both. In this embodiment, the process of removing the unreacted modified material layer 208 is a wet etching process. The process parameters of the wet etching process include that the chemical solution includes an ammonia solution, the temperature ranges from 40 degrees Celsius to 70 degrees Celsius, and the ratio of ammonia gas to water in the ammonia solution ranges from 1:5 to 1:10 (volume ratio). Since the ammonia solution has a high selectivity ratio to amorphous silicon material and titanium silicon nitride, it is beneficial to remove the unreacted modified material layer 208 in the process and reduce the damage to the barrier layer 209.

[0083] Please refer to Figure 11 An etching stop layer 210 is formed on the cover layer 205; after the etching stop layer 210 is formed, a work function layer 211 is also formed on the etching stop layer 210.

[0084] In this embodiment, specifically, the etching stop layer 210 is formed on the barrier layer 209.

[0085] The material of the etching stop layer 210 includes tantalum nitride. The etching stop layer 210 is used to protect the cover layer 205 from being damaged in the subsequent etching process.

[0086] The work function layer is N-type or P-type work function material. The P-type work function material includes one or more of tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride; the material of the N-type work function material includes one or more of titanium aluminum, titanium aluminum carbide, tantalum aluminum nitride, titanium aluminum nitride, tantalum carbon nitride, and aluminum nitride. In this embodiment, the work function layer is N-type work function material, and the material of the work function layer is tantalum aluminum nitride.

[0087] In this embodiment, a device of one conduction type is formed, i.e. N-type or P-type MOS device. In another embodiment, the substrate is located on a base, the base includes a first region and a second region, the first region is used to form an NMOS device (or PMOS device), and the second region is used to form a PMOS device (or NMOS device), the device on the second region is of a different conduction type from the device on the first region, the work function layer is used to form a work function layer on the first region, and the semiconductor forming method further includes: forming a patterned layer on the work function layer, the patterned layer exposes the work function layer on the second region; etching the work function layer until the etching stop layer is exposed to form a first work function layer on the first region; and forming a second work function layer on the surface of the etching stop layer on the second region.

[0088] Figures 12 to 16 is a structural schematic diagram of each step of the semiconductor structure forming method in another embodiment of the present application.

[0089] In this embodiment, before the modification ions are doped at the first interface, a cover layer is also formed on the gate dielectric layer, and after the cover layer is formed, before the modification ions are doped at the first interface, the cover layer is also subjected to modification treatment. The modification treatment process, please refer to Figure 5 on the basis of, please refer to Figures 12 to 13 .

[0090] Please refer to Figure 12 , a cover layer 301 is formed on the gate dielectric layer 202; and a modification material layer 302 is formed on the cover layer 301.

[0091] The material of the cover layer 301 includes titanium nitride. The cover layer 301 is used to solve the problem of polycrystalline silicon gate depletion in the metal embedded polycrystalline silicon gate process.

[0092] The material of the modification material layer 302 includes amorphous silicon. The modification material layer 302 is used to modify the cover layer 301 subsequently to form a barrier layer.

[0093] The thickness of the modified material layer 302 ranges from 10 angstroms to 150 angstroms.

[0094] The forming process of the modified material layer 302 includes a chemical vapor deposition process.

[0095] Please refer to Figure 13 After the modified material layer 302 is formed, the modified material layer 302 and the cover layer 301 are subjected to a third annealing process, so that the modified material layer 302 and the cover layer 301 react to form a barrier layer 303.

[0096] The process parameters of the third annealing process include an annealing temperature ranging from 850 degrees Celsius to 1050 degrees Celsius.

[0097] The material of the barrier layer 303 includes titanium silicon nitride. In this embodiment, the material of the modified material layer 302 is amorphous silicon, the material of the cover layer 301 is titanium nitride, the cover layer 301 and the modified material layer 302 react to form the barrier layer 303, so the material of the barrier layer 303 is titanium silicon nitride.

[0098] The barrier layer 303 is used to block the diffusion of ions in a work function layer formed subsequently into the gate dielectric layer 202, reduce the defect density in the gate dielectric layer 202, and improve the breakdown performance of the device, especially the time-varying breakdown performance of the NMOS device.

[0099] After the barrier layer 303 is formed, the unreacted modified material layer 302 is removed.

[0100] The process of removing the unreacted modified material layer 302 includes one of a dry etching process and a wet etching process, or a combination of both. In this embodiment, the unreacted modified material layer 302 and the second sacrificial layer are removed in the same subsequent process, saving production processes. In other embodiments, the unreacted modified material layer 302 can be removed before the second sacrificial layer is formed.

[0101] Subsequently, a second sacrificial layer containing the modified ions is formed on the surface of the gate oxide layer 201, which is used to incorporate modified ions at the first interface 203. The method of incorporating modified ions at the first interface 203 is described in Figures 14 to 15 .

[0102] Please refer to Figure 14 , the second sacrificial layer 304 containing the modified ions is formed on the surface of the gate oxide layer 201.

[0103] In the embodiment, specifically, a second sacrificial layer 304 containing the modified ions is formed on the surface of the unreacted modified material layer 302. In another embodiment, after the unreacted modified material layer 302 is removed, the second sacrificial layer is formed on the barrier layer 303.

[0104] The material of the second sacrificial layer 304 includes tungsten.

[0105] The process of forming the second sacrificial layer 304 includes a chemical vapor deposition process or an atomic layer deposition process. In the embodiment, the process of forming the second sacrificial layer 304 is an atomic layer deposition process. The process parameters of the atomic layer deposition process include: the reaction gas includes tungsten hexafluoride, hydrogen, silane or borane, the flow rate of tungsten hexafluoride ranges from 200 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of hydrogen ranges from 4500 standard milliliters per minute to 5500 standard milliliters per minute, the flow rate of silane or borane ranges from 150 standard milliliters per minute to 250 standard milliliters per minute, and the pressure ranges from 30 Torr to 50 Torr. The atomic layer deposition process has good step coverage, is conducive to forming a material film with uniform thickness, makes the concentration distribution of the modified ions in the second sacrificial layer 304 uniform, and is conducive to uniformly incorporating the modified ions into the first interface 203 subsequently.

[0106] In the embodiment, the modified ions are fluorine ions. Because tungsten hexafluoride gas is used in the process of forming the second sacrificial layer 304, the second sacrificial layer 304 contains a large amount of fluorine ions. The fluorine ions will diffuse into the first interface 203 in the subsequent second annealing process and react with the ions in the gate oxide layer 201 or the gate dielectric layer 202.

[0107] Please refer to Figure 15 , after the second sacrificial layer 304 (as shown in Figure 14 ) is formed, the second sacrificial layer 304, the gate oxide layer 201 and the gate dielectric layer 202 are subjected to a second annealing process; and after the second annealing process, the second sacrificial layer 304 is removed.

[0108] The process parameters of the second annealing process include: the temperature ranges from 500 degrees Celsius to 700 degrees Celsius.

[0109] The second annealing process diffuses the modified ions in the second sacrificial layer 304 into the first interface 203 and bonds with the ions in the gate dielectric layer 202 or the gate oxide layer 201, forming first chemical bonds at the first interface, which have stronger bond energy than the hydrogen-silicon bonds formed by the defect ions and the ions in the gate dielectric layer 202 (or the gate oxide layer 201) before the modified ions are incorporated, and are not easily broken, reducing the probability of the first interface 203 generating trap charges, thereby reducing the interface state density of the first interface 203, reducing the threshold voltage and the phenomenon of the saturation drain current of the device drifting, and improving the negative bias temperature instability of the formed device.

[0110] In this embodiment, the second annealing process also diffuses the modified ions from the first interface to the gate oxide layer and the second interface 204, and bonds the modified ions with the silicon ions in the substrate 200 or the gate oxide layer 201 at the second interface 204 to form second chemical bonds, i.e., silicon-fluorine bonds, which have greater bond energy than hydrogen-silicon bonds and are not easily broken relative to hydrogen-silicon bonds, reducing the probability of the second interface 204 generating trap charges, thereby reducing the interface state density of the second interface 204, reducing the threshold voltage and the phenomenon of the saturation drain current of the device drifting, and improving the negative bias temperature instability of the formed device.

[0111] In this embodiment, the second annealing process also diffuses the modified ions into the gate dielectric layer 202 and bonds the modified ions with the ions in the gate dielectric layer 202 to form second chemical bonds. The second chemical bonds include silicon-fluorine bonds, which have strong bond energy and are used to passivate defects in the gate dielectric layer 202, reducing the probability of current tunneling caused by traps formed by defects, thereby improving the time-dependent dielectric breakdown performance of the device.

[0112] In this embodiment, the second annealing process also diffuses the modified ions into the gate oxide layer 201 and bonds the modified ions with the ions in the gate oxide layer 201 to form strong chemical bonds, which are used to passivate defects in the gate oxide layer 201, reducing the probability of current tunneling caused by traps formed by defects, thereby improving the time-dependent dielectric breakdown performance of the device.

[0113] The process of removing the second sacrificial layer 304 includes one of a dry etching process and a wet etching process or a combination of both.

[0114] In the embodiment, the process of removing the second sacrificial layer 304 is a wet etching process. The second sacrificial layer 304 and the unreacted modified material layer 302 are removed together in the same production process, which reduces the process steps and saves production cost. The chemical solution used in the wet etching process includes H2O2.

[0115] Please refer to Figure 16 After the modified ions are incorporated at the first interface 203, an etching stop layer 305 is formed on the cover layer 301. After the etching stop layer 305 is formed, a work function layer 306 is formed on the etching stop layer 305.

[0116] The material of the etching stop layer 305 includes tantalum nitride.

[0117] The work function layer 306 is an N-type or P-type work function material. The P-type work function material includes one or more of tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride. The N-type work function material includes one or more of titanium aluminum, titanium aluminum carbide, tantalum aluminum nitride, titanium aluminum nitride, tantalum carbon nitride, and aluminum nitride. In the embodiment, the work function layer is an N-type work function material, and the material of the work function layer is tantalum aluminum nitride.

[0118] In the embodiment, a device of one conduction type is formed, i.e., an N-type or P-type MOS device. In another embodiment, the substrate is located on a base, and the base includes a first region and a second region. The first region is used to form an NMOS device (or a PMOS device), and the second region is used to form a PMOS device (or an NMOS device). The device on the second region is of a different conduction type from the device on the first region. The work function layer is used to form a work function layer on the first region. The semiconductor forming method further includes: forming a patterned layer on the work function layer, which exposes the work function layer on the second region; etching the work function layer until the etching stop layer is exposed to form a first work function layer on the first region; and forming a second work function layer on the surface of the etching stop layer on the second region.

[0119] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a method for forming a gate oxide layer and a gate dielectric layer on a substrate. The application provides a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer being located on the gate oxide layer and having a first interface with the gate oxide layer; forming a cover layer on the gate dielectric layer; after forming the cover layer, incorporating modified ions at the first interface, the modified ions being bonded with ions in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than a chemical bond formed by defect ions and ions in the gate dielectric layer or the gate oxide layer before the modified ions are incorporated at the first interface, the method for incorporating the modified ions at the first interface comprising: Method 1: forming a first sacrificial layer on the gate dielectric layer; performing plasma treatment on the first sacrificial layer to inject the modified ions into the first interface; after the plasma treatment on the first sacrificial layer, performing first annealing treatment on the gate dielectric layer and the gate oxide layer; after the first annealing treatment, removing the first sacrificial layer; or Method 2: forming a second sacrificial layer containing the modified ions on the surface of the gate oxide layer; after forming the second sacrificial layer, performing second annealing treatment on the second sacrificial layer, the gate oxide layer and the gate dielectric layer; after the second annealing treatment, removing the second sacrificial layer; in Method 1, after the modified ions are incorporated at the first interface, the cover layer is also subjected to modification treatment; in Method 2, before the modified ions are incorporated at the first interface, the cover layer is also subjected to modification treatment; wherein the method for the modification treatment comprises: forming a modified material layer on the cover layer; after forming the modified material layer, performing third annealing treatment on the modified material layer and the cover layer, so that the modified material layer and the cover layer react to form a barrier layer; after forming the barrier layer, removing the unreacted modified material layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The modified ions are also doped into the gate dielectric layer, the modified ions being bonded with ions in the gate dielectric layer to form a second chemical bond.

3. The method of forming a semiconductor structure of claim 1, wherein, The gate oxide layer and the substrate also have a second interface, and the modified ions are also doped into the second interface.

4. The method of forming a semiconductor structure of claim 1, wherein, The modified ions are also doped into the gate oxide layer.

5. The method of forming a semiconductor structure of claim 1, wherein, The material of the first sacrificial layer comprises titanium nitride.

6. The method of forming a semiconductor structure of claim 1, wherein, The material of the cover layer comprises titanium nitride.

7. The method of forming a semiconductor structure of claim 1, wherein, After the modified ions are incorporated at the first interface, the method further comprises: forming an etching stop layer on the cover layer; the material of the etching stop layer comprises tantalum nitride.

8. The method of forming a semiconductor structure of claim 7, wherein, After the modified ions are incorporated at the first interface, the cover layer is subjected to modification treatment before the etching stop layer is formed.

9. The method of forming a semiconductor structure of claim 7, wherein, After the etching stop layer is formed, the method further comprises: forming a work function layer on the etching stop layer, the work function layer being an N-type or P-type work function material; the P-type work function material comprises one or more of tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride and titanium silicon nitride; the N-type work function material comprises one or more of titanium aluminide, titanium aluminide carbide, tantalum aluminide nitride, titanium aluminide nitride, tantalum nitride carbide and aluminum nitride.

10. The method of forming a semiconductor structure of claim 1, wherein, The material of the second sacrificial layer comprises tungsten.

11. The method of forming a semiconductor structure of claim 1, wherein, The process of forming the second sacrificial layer comprises a chemical vapor deposition process or an atomic layer deposition process.

12. The method of forming a semiconductor structure of claim 2, wherein, The first chemical bond comprises a hafnium-fluorine bond and a silicon-fluorine bond; and the second chemical bond comprises a silicon-fluorine bond.

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