Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including adjacent dense regions and sparse regions; forming a plurality of first gate layers and a plurality of second gate layers on the substrate, and a dielectric layer covering the first gate layers and the second gate layers, the dielectric layer exposing top surfaces of the first gate layers and the second gate layers, the first gate layers being located on the dense regions, the second gate layers being located on the dense regions, and a spacing between adjacent first gate layers being smaller than a spacing between adjacent second gate layers; and performing a grinding process to grind surfaces of the first gate layers, the second gate layers, and the dielectric layer, the grinding process including a first grinding process, the first grinding process having a first grinding rate for materials of the first gate layers and the second gate layers, the first grinding process having a second grinding rate for a material of the dielectric layer, and the first grinding rate being greater than the second grinding rate. The semiconductor structure formed by the method has better performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a forming method of semiconductor structure. BACKGROUND

[0002] With the decrease of the size of semiconductor devices, more and more device units are integrated on a unit area, the density of the device is gradually increased, and the size between the devices is reduced, which also increases the difficulty of manufacturing. With the reduction of the critical dimension (CD) of the integrated circuit, a metal gate is usually formed by a 'gate last process'. The gate last process needs to form a gate opening in a dielectric layer and fill the gate opening with a gate material.

[0003] The so-called gate last process refers to: providing a semiconductor substrate, a dummy gate structure is formed on the semiconductor substrate; forming an interlayer dielectric layer on the surface of the etching stop layer; performing a planarization process on the interlayer dielectric layer with the surface of the dummy gate structure as a stop layer; forming a trench after removing the dummy gate structure; filling metal into the trench by physical vapor deposition or metal target sputtering to form a metal gate electrode layer; and planarizing the metal gate electrode layer until the interlayer dielectric layer is exposed to form a metal gate. The planarization process can be achieved by chemical mechanical polishing (CMP) technology, which is one of the important process steps in the semiconductor manufacturing process.

[0004] However, the performance of the semiconductor device formed by the existing method is poor. SUMMARY

[0005] The technical problem solved by the present application is to provide a forming method of semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical scheme of the present application provides a forming method of semiconductor structure, comprising: providing a substrate, the substrate comprising adjacent dense areas and sparse areas; forming a plurality of first gate layers and a plurality of second gate layers on the substrate and a dielectric layer covering the first gate layers and the second gate layers, the dielectric layer exposing the top surfaces of the first gate layers and the second gate layers, the first gate layers being located on the dense areas, the second gate layers being located on the dense areas, and the spacing between adjacent first gate layers being smaller than the spacing between adjacent second gate layers; and performing a grinding process to grind the surfaces of the first gate layers, the second gate layers and the dielectric layer, the grinding process comprising: a first grinding process, the first grinding process having a first grinding rate for the materials of the first gate layers and the second gate layers, the first grinding process having a second grinding rate for the material of the dielectric layer, and the first grinding rate being greater than the second grinding rate.

[0007] Optionally, the first polishing process reduces a height of the first gate layer and the dielectric layer on the dense region and a height of the second gate layer on the sparse region by a first height, and reduces a height of the dielectric layer on the sparse region by a second height, and the first height is greater than the second height.

[0008] Optionally, the first gate layer and the second gate layer are made of a same material; the material of the first gate layer and the second gate layer comprises a high-K dielectric material and a metal; the high-K dielectric material comprises one or more combinations of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide and aluminum oxide; and the metal comprises one or more combinations of copper, tungsten, aluminum, titanium and nickel.

[0009] Optionally, the material of the dielectric layer comprises one or more combinations of silicon oxide, silicon nitride, silicon oxynitride and titanium dioxide.

[0010] Optionally, a ratio of the first polishing rate and the second polishing rate ranges from 50:1 to 100:1.

[0011] Optionally, the first polishing process comprises a chemical mechanical polishing process.

[0012] Optionally, the polishing process further comprises a second polishing process for polishing surfaces of the first gate layer, the second gate layer and the dielectric layer to reduce heights of the first gate layer, the second gate layer and the dielectric layer.

[0013] Optionally, the second polishing process is performed after the first polishing process.

[0014] Optionally, the second polishing process is performed before the first polishing process.

[0015] Optionally, the second polishing process has a third polishing rate for the material of the first gate layer and the second gate layer, and has a fourth polishing rate for the material of the dielectric layer, and a ratio of the third polishing rate and the fourth polishing rate ranges from 0.9:1 to 1.1:1.

[0016] Optionally, the second polishing process comprises a chemical mechanical polishing process.

[0017] Optionally, the dielectric layer on the sparse region has a groove therein, and the groove has a third height from a top to a bottom in a direction perpendicular to the surface of the substrate.

[0018] Optionally, the first polishing process makes a difference between the first height and the second height greater than or equal to the third height.

[0019] Optionally, the method for forming the first gate layer, the second gate layer, the dielectric layer and the recess comprises: forming a plurality of first dummy gate layers on the dense region and a plurality of second dummy gate layers on the sparse region; forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first dummy gate layers and the second dummy gate layers, and the top surface of the initial dielectric layer being higher than the top surfaces of the first dummy gate layers and the second dummy gate layers; planarizing the initial dielectric layer until the top surfaces of the first dummy gate layers and the second dummy gate layers are exposed, forming the dielectric layer and the recess in the dielectric layer on the sparse region; removing the first dummy gate layers and the second dummy gate layers to form the first gate opening and the second gate opening in the dielectric layer; forming an initial gate material film in the first gate opening, the second gate opening and on the surface of the dielectric layer; planarizing the initial gate material film until the surface of the dielectric layer on the dense region is exposed, forming the first gate layer in the first gate opening and the second gate layer in the second gate opening.

[0020] Optionally, the method further comprises: performing the grinding process multiple times to grind the first gate layer, the second gate layer and the surface of the dielectric layer until the first gate layer and the second gate layer reach a target height.

[0021] Optionally, the substrate comprises a substrate and a fin and an isolation layer on the surface of the substrate, and the isolation layer covers part of the sidewall surface of the fin; the first gate layer and the second gate layer span the fin and cover part of the top surface and the sidewall surface of the fin, and the dielectric layer is on the surface of the isolation layer.

[0022] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0023] The forming method of the semiconductor structure provided in the technical scheme comprises a grinding process, the grinding process comprises a first grinding process, the first grinding process has a first grinding rate for the material of the first gate layer and the second gate layer, and the first grinding rate is greater than a second grinding rate for the material of the medium layer. Since the device density on the sparse area is less than the device density on the dense area, that is, the area ratio of the medium layer on the dense area to the total area of the medium layer and the first gate layer is small, the first grinding process not only has a large grinding rate for the material of the first gate layer on the dense area, but also affects the grinding rate for the material of the medium layer on the dense area, so that the height of the medium layer and the first gate layer on the dense area is uniformly reduced, and the surface flatness of the dense area is good. Since the area ratio of the medium layer on the sparse area to the total area of the medium layer and the second gate layer is large, the first grinding process has a grinding rate for the material of the second gate layer that is greater than the grinding rate for the material of the medium layer, that is, the grinding rate for the material of the medium layer on the dense area is less than the grinding rate for the material of the second gate layer on both sides of the medium layer, so that the groove morphology in the medium layer on the dense area is improved. In summary, the method makes the surface flatness of the sparse area and the dense area good.

[0024] Further, the grinding process further comprises a second grinding process, the second grinding process has a third grinding rate for the material of the first gate layer and the second gate layer, and the ratio of the third grinding rate to a fourth grinding rate for the material of the medium layer is close, so that the second grinding process can quickly grind the sparse area and the dense area, thereby the second grinding process can quickly make the height of the first gate layer and the second gate layer close to the target height, which is beneficial to save process time and facilitate process control.

[0025] Further, the distance between the top and the bottom of the groove in the medium layer on the sparse area is a third height, by controlling the time of the first grinding process, when the difference between the first height and the second height is greater than the third height, the groove can be improved well, and the overall surface flatness on the sparse area is good. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1 to 4 FIG. 1 is a structural schematic diagram of each step of the forming method of the semiconductor structure in an embodiment;

[0027] Figures 5 to 11 FIG. 2 is a structural schematic diagram of each step of the forming method of the semiconductor structure in an embodiment. DETAILED DESCRIPTION

[0028] It should be noted that the “surface”, “upper”, and “lower” in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0029] Firstly, the reasons for poor performance of the existing semiconductor structure are described in detail in combination with the drawings, Figures 1 to 4 is a structural schematic diagram of each step of the method for forming the semiconductor structure in an embodiment.

[0030] Referring to Figure 1 , a substrate 100 is provided, which includes adjacent dense region I and sparse region II; a plurality of first dummy gate layers 111 are formed on the dense region I, and a plurality of second dummy gate layers 112 are formed on the sparse region II; an initial dielectric layer 120 is formed on the substrate 100 to cover the first dummy gate layers 111 and the second dummy gate layers 112, and the top surface of the initial dielectric layer 120 is higher than the top surfaces of the first dummy gate layers 111 and the second dummy gate layers 112.

[0031] Referring to Figure 2 , the initial dielectric layer 120 is planarized until the first dummy gate layers 111 and the second dummy gate layers 112 are exposed, so that the initial dielectric layer forms a dielectric layer 130; the first dummy gate layers 111 and the second dummy gate layers 112 are removed to form first gate openings 141 and second gate openings 142 in the dielectric layer 130.

[0032] Referring to Figure 3 , a gate material film 150 is formed on the first gate openings 141, the second gate openings 142, and the surface of the dielectric layer 130, and the top surface of the gate material film 150 is higher than the top surface of the dielectric layer 130.

[0033] Referring to Figure 4 , the gate material film 150 is planarized to remove the gate material film 150 on the surface of the dielectric layer 130, lower the height of the dielectric layer 130, form a first gate layer 161 in the first gate opening 141, and form a second gate layer 162 in the second gate opening 142, and the first gate layer 161 and the second gate layer 162 reach a target height.

[0034] In the above method, the process of planarizing the gate material film 150 is usually a chemical mechanical polishing process, which removes the gate material film 150 on the surface of the dielectric layer 130, lowers the height of the dielectric layer 130, and makes the heights of the first gate layer 161 and the second gate layer 162 on the dielectric layer 130 reach the target height.

[0035] However, since the device density on the sparse region II is less than the device density on the dense region I, there is a difference in polishing rate of the devices on the sparse region II and the dense region I during the planarization of the initial dielectric layer 120, especially the polishing rate of the initial dielectric layer 120 material with a large area ratio on the sparse region II is large, which results in the groove a in the dielectric layer 130 on the sparse region II. And during the subsequent planarization of the gate material film 150, the polishing rate of the dielectric layer 130 material and the gate material film 150 material is close, although it can make the height of the first gate layer 161 and the second gate layer 162 reach the target height, but the groove a in the dielectric layer 130 on the sparse region II still exists.

[0036] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, by performing a polishing treatment to polish the first gate layer, the second gate layer and the surface of the dielectric layer, the polishing treatment comprises: a first polishing process, the first polishing process has a first polishing rate to the material of the first gate layer and the second gate layer, the first polishing process has a second polishing rate to the material of the dielectric layer, and the first polishing rate is greater than the second polishing rate, since the first polishing process not only has a large polishing rate to the first gate layer material on the dense region, but also affects the polishing rate to the dielectric layer material with a small area on the dense region, so that the height of the dielectric layer and the first gate layer on the dense region is uniformly reduced. At the same time, since the first polishing process has a larger polishing rate to the second gate layer material than to the dielectric layer material, that is, the polishing rate to the dielectric layer on the dense region is less than the polishing rate to the second gate layer on both sides of the dielectric layer, so that the groove morphology in the dielectric layer on the dense region is improved. In summary, the method makes the flatness of the overall surface of the sparse region and the dense region better.

[0037] In order to make the above-mentioned purposes, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0038] Figures 5 to 11 is a structure schematic diagram of each step of the forming method of the semiconductor structure in an embodiment of the present application.

[0039] Please refer to Figure 5 , a substrate 200 is provided, the substrate 200 comprises a dense region I and a sparse region II adjacent to each other.

[0040] The material of the substrate 200 comprises: silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0041] In other embodiments, the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0042] The substrate 200 comprises a substrate (not shown in the figure) and fins (not shown in the figure) and an isolation layer (not shown in the figure) on the surface of the substrate, and the isolation layer covers part of the sidewall surface of the fins.

[0043] In other embodiments, the substrate is a planar substrate.

[0044] Next, a plurality of first gate layers and a plurality of second gate layers are formed on the substrate 200, and a dielectric layer covering the first gate layers and the second gate layers is formed, the dielectric layer exposes the top surface of the first gate layers and the second gate layers, the first gate layers are located on the dense region I, the second gate layers are located on the sparse region II, and the spacing between adjacent first gate layers is smaller than the spacing between adjacent second gate layers. For details of the process of forming the first gate layers, the second gate layers and the dielectric layer, please refer to Figures 6 to 9 .

[0045] In this embodiment, the dielectric layer on the sparse region II has a groove, and the groove has a third height from top to bottom in the direction perpendicular to the surface of the substrate 200.

[0046] For details, please refer to Figure 6 , a plurality of first dummy gate layers 210 are formed on the dense region I, and a plurality of second dummy gate layers 220 are formed on the sparse region II; an initial dielectric layer 230 covering the first dummy gate layers 210 and the second dummy gate layers 220 is formed on the substrate 200, and the top surface of the initial dielectric layer 230 is higher than the top surface of the first dummy gate layers 210 and the second dummy gate layers 220.

[0047] The first dummy gate layers 210 and the second dummy gate layers 220 occupy space for the first gate layers and the second gate layers formed by the "gate last process" subsequently.

[0048] Specifically, in this embodiment, the first dummy gate layers 210 and the second dummy gate layers 220 span the fins and are located on the top surface and the sidewall surface of part of the fins.

[0049] In this embodiment, the method for forming the semiconductor structure further comprises: after forming the first dummy gate layers 210 and the second dummy gate layers 220, and before forming the initial dielectric layer 230, the first dummy gate layers 210 have first sidewalls (not marked in the figure) on both sides, and the second dummy gate layers 220 have second sidewalls (not marked in the figure) on both sides.

[0050] The first sidewalls serve as the sidewall surface of the first gate layers formed subsequently, and the second sidewalls are located on the sidewall surface of the second gate layers formed subsequently.

[0051] In the embodiment, the first and second sidewalls are made of the same material, which is silicon nitride. In the embodiment, the first and second sidewalls are made of one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

[0052] In the embodiment, the method for forming the semiconductor structure further comprises, after forming the first and second sidewalls and before forming the initial dielectric layer 230, forming source-drain doped regions in the fins on both sides of the first dummy gate layer 210 and the first sidewall, and in the fins on both sides of the second dummy gate layer 220 and the second sidewall (not shown in the figure).

[0053] In the embodiment, the initial dielectric layer 230 is located on the surfaces of the fins and the isolation layer.

[0054] The material of the initial dielectric layer 230 is an insulating material, which includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide. In the embodiment, the material of the initial dielectric layer 230 is silicon oxide.

[0055] Please refer to Figure 7 , planarize the initial dielectric layer 230 until the top surfaces of the first and second dummy gate layers 210 and 220 are exposed, form a dielectric layer 231, and the dielectric layer 231 in the sparse region I has a recess 232.

[0056] The dielectric layer 231 is formed by planarizing the initial dielectric layer 230, and accordingly, the material of the dielectric layer 231 is an insulating material, which includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

[0057] Because the device density in the sparse region II is less than that in the dense region I, there is a difference in the polishing rate of the devices in the sparse region II and the dense region I during the planarization of the initial dielectric layer 230, especially the polishing rate of the initial dielectric layer 230 material with a large area ratio in the sparse region II is large, which causes the recess 232 in the dielectric layer 231 in the sparse region II.

[0058] The recess 232 has a third height L3 from the top to the bottom in the direction perpendicular to the surface of the substrate 200.

[0059] Please continue to refer to Figure 7 , after the top surfaces of the first and second dummy gate layers 210 and 220 are exposed, remove the first and second dummy gate layers 210 and 220, and form a first gate opening 241 and a second gate opening 242 in the dielectric layer 231.

[0060] The first gate opening 241 provides space for forming a first gate layer, and the second gate opening 242 provides space for forming a second gate layer.

[0061] Specifically, the first gate opening 241 is located in the dielectric layer 231 on the dense region I, and the second gate opening 242 is located in the dielectric layer 231 on the sparse region II.

[0062] Please refer to Figure 8 An initial gate material film 250 is formed on the surface of the dielectric layer 231, in the first gate opening 241, and in the second gate opening 242.

[0063] The initial gate material film 250 provides material for forming the first gate layer and the second gate layer.

[0064] The forming method of the initial gate material film 250 includes: forming an initial gate dielectric film (not shown in the figure) on the surface of the initial gate dielectric film, on the bottom and sidewall surface of the first gate opening 241, on the bottom and sidewall surface of the second gate opening 242, and on the surface of the dielectric layer 231; and forming an initial gate film (not shown in the figure) on the surface of the initial gate dielectric film, and the initial gate film fills the first gate opening 241 and the second gate opening 242.

[0065] The material of the initial gate dielectric film includes high-K dielectric material, and the high-K dielectric material includes one or a combination of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, or aluminum oxide. In this embodiment, the material of the initial gate dielectric film is hafnium oxide.

[0066] The material of the initial gate film includes metal, and the metal includes one or a combination of copper, tungsten, aluminum, titanium, and nickel. In this embodiment, the material of the initial gate film is tungsten.

[0067] It should be noted that the initial gate material film 250 also fills the groove 232 located in the dielectric layer 231.

[0068] Please refer to Figure 9 The initial gate material film 250 is planarized until the surface of the dielectric layer 231 on the sparse region II and the dense region I is exposed, the first gate layer 261 is formed in the first gate opening 241, and the second gate layer 262 is formed in the second gate opening 242.

[0069] In this embodiment, the first gate layer 261 and the second gate layer 262 span the fin and cover part of the top surface and the sidewall surface of the fin, and the dielectric layer 231 is located on the surface of the isolation layer.

[0070] The first gate layer 261 and the second gate layer 262 are formed by planarizing the initial gate material film 250.

[0071] It should be noted that, in the process of planarizing the initial gate material film 250, because the device density on the sparse area II is less than the device density on the dense area I, the rate of grinding the initial gate material film 250 on the sparse area II is greater than the rate of grinding the initial gate material film 250 on the dense area I, so that the surface of the dielectric layer 231 on the dense area I is exposed at the same time, and the initial gate material film 250 in the groove 232 can be removed to expose the surface of the dielectric layer 231 on the sparse area II.

[0072] Then, a grinding process is performed to grind the first gate layer 261, the second gate layer 262 and the surface of the dielectric layer 231, the grinding process includes: a first grinding process, the first grinding process has a first grinding rate for the material of the first gate layer 261 and the second gate layer 262, the first grinding process has a second grinding rate for the material of the dielectric layer 231, and the first grinding rate is greater than the second grinding rate.

[0073] In this embodiment, the grinding process further includes: a second grinding process, the first gate layer 261, the second gate layer 262 and the surface of the dielectric layer 231 are ground to reduce the height of the first gate layer 261, the second gate layer 262 and the dielectric layer 231.

[0074] In this embodiment, the second grinding process is performed before the first grinding process.

[0075] The process of performing the grinding process will be described in detail with reference to Figures 10 to 11 .

[0076] The second grinding process will be described in detail with reference to Figure 10 , the first gate layer 261, the second gate layer 262 and the surface of the dielectric layer 231 are ground to reduce the height of the first gate layer 261, the second gate layer 262 and the dielectric layer 231.

[0077] The second grinding process has a third grinding rate for the material of the first gate layer 261 and the second gate layer 262, and a fourth grinding rate for the material of the dielectric layer, and the ratio of the third grinding rate to the fourth grinding rate ranges from 0.9:1 to 1.1:1.

[0078] In this embodiment, the ratio of the third grinding rate to the fourth grinding rate is 1:1.

[0079] In this embodiment, the ratio of the grinding rate of the second grinding process for the first side wall and the second side wall to the grinding rate of the dielectric layer 231 ranges from 0.9:1 to 1.1:1.

[0080] Specifically, in this embodiment, the grinding rate of the second grinding process on the first and second sidewalls is the same as the grinding rate on the dielectric layer 231.

[0081] Since the ratio of the third grinding rate of the second grinding process on the materials of the first gate layer 261 and the second gate layer 262 to the fourth grinding rate on the material of the dielectric layer 231 is close, the second grinding process can grind the sparse region II and the dense region I more quickly. Thus, through the second grinding process, the height of the first gate layer 261 and the second gate layer 262 can be brought closer to the target height more quickly, which is beneficial to saving process time and making it easier to control the process.

[0082] Please refer to Figure 11 After performing the second polishing process, a first polishing process is performed. The first polishing process has a first polishing rate on the materials of the first gate layer 261 and the second gate layer 262, and a second polishing rate on the material of the dielectric layer 231. The first polishing rate is greater than the second polishing rate.

[0083] In this embodiment, the first polishing process reduces the height of the first gate layer 261 and dielectric layer 231 on the dense region I and the second gate layer 262 on the sparse region II by a first height L1 and reduces the height of the dielectric layer 231 on the sparse region II by a second height L2, and the first height L1 is greater than the second height L2.

[0084] The first grinding process includes chemical mechanical grinding.

[0085] The ratio of the first grinding rate to the second grinding rate ranges from 50:1 to 100:1.

[0086] In this embodiment, the ratio of the first grinding rate to the second grinding rate is 60:1.

[0087] Specifically, in this embodiment, by controlling the first grinding process and the grinding time, the first grinding process makes the difference between the first height L1 and the second height L2 greater than or equal to the third height L3.

[0088] Since the distance between the top and bottom of the groove 232 in the medium layer 231 on the sparse region II is the third height L3, by controlling the time of the first grinding process, when the difference between the first height L1 and the second height L2 is greater than the third height L3, the groove 232 can be improved better, and the overall surface flatness on the sparse region II can be better.

[0089] In other embodiments, the first grinding process can also make the difference between the first height and the second height less than the third height.

[0090] Specifically, by the first grinding process, since the grinding rate of the first grinding process on the first gate layer 261 and the second gate layer 262 is greater than the grinding rate on the dielectric layer 231, the rate of reducing the dielectric layer 231 on the sparse area II away from the second gate layer 262 is greater than the rate of reducing the dielectric layer 231 on the sparse area II adjacent to the second gate layer 262, the groove 232 on the sparse area II is improved, and the surface on the sparse area II is relatively flat.

[0091] By performing the grinding process, the grinding process includes: a first grinding process, the first grinding process has a first grinding rate on the material of the first gate layer 261 and the second gate layer 262, which is greater than a second grinding rate on the material of the dielectric layer 231. Since the device density on the sparse area II is less than the device density on the dense area I, that is, the area of the dielectric layer 231 on the dense area I accounts for a smaller proportion of the total area of the dielectric layer 231 and the first gate layer 261, the first grinding process not only has a greater grinding rate on the material of the first gate layer 261 on the dense area I, but also affects the grinding rate on the material of the dielectric layer 231 on the dense area I with a smaller area, so that the height of the dielectric layer 231 and the first gate layer 261 on the dense area I is uniformly reduced, and the surface flatness on the dense area I is better. The area of the dielectric layer 231 on the sparse area II accounts for a larger proportion of the total area of the dielectric layer 231 and the second gate layer 262. Since the grinding rate of the first grinding process on the material of the second gate layer 262 is greater than the grinding rate on the material of the dielectric layer 231, that is, the grinding rate on the dielectric layer 231 on the dense area I is less than the grinding rate on the second gate layer 262 located on both sides of the dielectric layer 231, so that the groove 232 morphology in the dielectric layer 231 on the dense area II is improved. In summary, the method makes the flatness of the overall surface of the sparse II area and the dense area I better.

[0092] In other embodiments, the first grinding process is performed before the second grinding process.

[0093] It should be noted that in this embodiment, after the second grinding process and the first grinding process, not only is the groove 232 on the sparse area II improved, but also the height of the first gate layer 261 and the second gate layer 262 is reduced to the target height, so as to meet the process requirements, and at this time, the grinding process is no longer performed.

[0094] In other embodiments, after the second grinding process and the first grinding process, the grooves on the sparse area are improved well, so that the overall surface on the sparse area is flat, however, the height of the first gate layer and the second gate layer has not reached the target height, and the method for forming the semiconductor structure further includes: performing multiple times of the grinding process to grind the first gate layer, the second gate layer and the medium layer surface, so that the first gate layer and the second gate layer reach the target height.

[0095] Although the present application has been disclosed with reference to the above embodiments, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising adjacent dense and sparse regions; A plurality of first dummy gate layers are formed on the dense region, and a plurality of second dummy gate layers are formed on the sparse region; an initial dielectric layer is formed on the substrate covering the first and second dummy gate layers, and the top surface of the initial dielectric layer is higher than the top surfaces of the first and second dummy gate layers; the initial dielectric layer is planarized until the top surfaces of the first and second dummy gate layers are exposed to form a dielectric layer, and the dielectric layer on the sparse region has grooves. Remove the first dummy gate layer and the second dummy gate layer, and form a first gate opening and a second gate opening in the dielectric layer; form an initial gate material film in the first gate opening, the second gate opening and the surface of the dielectric layer; planarize the initial gate material film until the surface of the dielectric layer on the sparse region and the dense region is exposed, form a first gate layer in the first gate opening, form a second gate layer in the second gate opening, and form a dielectric layer covering the first gate layer and the second gate layer. The dielectric layer exposes the top surfaces of the first gate layer and the second gate layer, and the spacing between adjacent first gate layers is smaller than the spacing between adjacent second gate layers; A grinding process is performed to grind the surfaces of the first gate layer, the second gate layer, and the dielectric layer. The polishing process includes: a first polishing process, wherein the first polishing process has a first polishing rate on the materials of the first gate layer and the second gate layer, and a second polishing rate on the materials of the dielectric layer, wherein the first polishing rate is greater than the second polishing rate; and the first polishing process makes the overall surface of the sparse region flat. The polishing process further includes: a second polishing process, polishing the surfaces of the first gate layer, the second gate layer, and the dielectric layer to reduce the height of the first gate layer, the second gate layer, and the dielectric layer to a height close to the target height; the ratio of the polishing rate of the second polishing process on the first gate layer and the second gate layer to the polishing rate on the dielectric layer is close to that of the second polishing process. The first polishing process reduces the height of the first gate layer and dielectric layer in the dense region and the second gate layer in the sparse region by a first height, and reduces the height of the dielectric layer in the sparse region by a second height, wherein the first height is greater than the second height; the distance between the top and bottom of the groove in the dielectric layer in the sparse region is a third height, and by controlling the time of the first polishing process, the difference between the first height and the second height is greater than or equal to the third height, wherein the second height is the height by which the lowest point of the top surface of the dielectric layer drops.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first gate layer and the second gate layer are made of the same material; The materials of the first gate layer and the second gate layer include: a high-K dielectric material and a metal; the high-K dielectric material includes one or more combinations of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide and aluminum oxide; the metal includes one or more combinations of copper, tungsten, aluminum, titanium and nickel.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the dielectric layer includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The ratio of the first grinding rate to the second grinding rate ranges from 50:1 to 100:

1.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first grinding process includes chemical mechanical grinding.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the first grinding process, the second grinding process is performed.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second grinding process is performed before the first grinding process.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second polishing process has a third polishing rate for the materials of the first gate layer and the second gate layer, and a fourth polishing rate for the materials of the dielectric layer, and the ratio of the third polishing rate to the fourth polishing rate ranges from 0.9:1 to 1.1:

1.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second grinding process includes chemical mechanical grinding.

10. The method for forming a semiconductor structure as described in claim 5, characterized in that, The groove has a third height from top to bottom along a direction perpendicular to the substrate surface; the first grinding process makes the difference between the first height and the second height greater than or equal to the third height.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: The grinding process is performed multiple times to grind the surfaces of the first gate layer, the second gate layer, and the dielectric layer, so that the first gate layer and the second gate layer reach the target height.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes: a substrate and a fin and an isolation layer located on the surface of the substrate, wherein the isolation layer covers a portion of the sidewall surface of the fin; a first gate layer and a second gate layer span the fin and cover a portion of the top surface and sidewall surface of the fin; and a dielectric layer is located on the surface of the isolation layer.

Images