Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: forming a first dielectric material layer on a substrate, the first dielectric material layer being located on the sidewalls of an initial first fin; removing the first core layer; after removing the first core layer, etching the initial first fin using the first sidewall as a mask to form two separate first fins and a first opening located between the two first fins; after forming the first isolation structure, etching back the first dielectric material layer to form a second isolation structure, the top surface of the second isolation structure being lower than the top surface of the first fin. The first fin and the first opening are formed simultaneously using a single etching process using the first sidewall as a mask, simplifying the production process. Furthermore, the first dielectric material layer is used to form the second isolation structure and protects the substrate, the second fin, and the sidewalls of the initial first fin from etching damage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the fin field-effect transistor (FinFET) is an emerging multi-gate device. Compared with planar metal-oxide semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel suppression capabilities and higher operating currents, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, transistor dimensions have been reduced to below a few nanometers. The size of the FinFET itself has been reduced to its limit. Whether it is fin distance, short-channel effects, leakage, or material limitations, transistor manufacturing has become precarious, and even the physical structure cannot be completed.

[0003] Surround gate (gate-all-around, GAA) devices have become a new direction of research and development in the industry. The characteristic of this technology is that the gate wraps the channel on all four sides. The source and drain are no longer in contact with the substrate. Instead, multiple source and drain electrodes such as linear (which can be understood as stick-shaped) or flat or sheet-shaped are distributed transversely perpendicular to the gate to achieve the basic structure and function of MOSFET. This design largely solves the various problems caused by the reduction in gate spacing, including capacitance effects, etc. In addition, the channel is wrapped by the gate on all four sides, so the channel current is smoother than the three-sided wrapping of FinFET.

[0004] However, as an important development direction in the industry, wrap-around gate devices still need further improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a composite layer on the substrate, the composite layer comprising a plurality of overlapping initial sacrificial layers and an initial channel layer located between two adjacent initial sacrificial layers; forming a plurality of first axial layer structures on a surface of the composite layer on the first region, the first axial layer structures comprising the first axial layer and two first sidewalls of the first axial layer sidewalls; etching the composite layer and the substrate using the first axial layer structure as a mask to form an initial first fin; forming a first dielectric material layer on the substrate, the first dielectric material layer being located at The initial first fin sidewall; removing the first axial layer; after removing the first axial layer, etching the initial first fin using the first sidewall as a mask to form two mutually separate first fins and a first opening located between the two first fins, the first fin including a first bottom structure located on the first area, a plurality of overlapping first sacrificial layers located on the first bottom structure, and a first channel layer located between two adjacent first sacrificial layers; forming a first isolation structure in the first opening; after forming the first isolation structure, etching back the first dielectric material layer to form a second isolation structure, the top surface of the second isolation structure being lower than the top surface of the first fin.

[0007] Optionally, the substrate also includes a second region; the method for forming the semiconductor structure also includes: forming a plurality of second fins on the second region, the second fins including a second bottom structure located on the second region, several overlapping second sacrificial layers located on the second bottom structure, and a second channel layer located between two adjacent second sacrificial layers.

[0008] Optionally, the second isolation structure is further located on the sidewall of the second fin, and a top surface of the second isolation structure is flush with a top surface of the second bottom structure.

[0009] Optionally, the second fin is formed before the first fin is formed.

[0010] Optionally, the composite layer is also located on the second region, and the method for forming the second fin includes: forming a plurality of second side walls on the surface of the composite layer on the second region; etching the composite layer and the substrate using the second side walls as a mask to form a plurality of mutually discrete second fins located on the second region.

[0011] Optionally, the material of the second sidewall spacer is an insulating dielectric material, and the material of the second sidewall spacer includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0012] Optionally, the method for forming the first axial layer structure includes: forming multiple first axial layers on part of the composite layer; forming a first sidewall material layer on the sidewall of the first axial layer and the composite layer; etching back the first sidewall material layer to expose the surface of the composite layer and the surface of the first axial layer to form a first axial layer structure.

[0013] Optionally, the second side wall is formed simultaneously with the first side wall, and the first axial layer structure is also located on a partial surface of the composite layer on the second area. The method for forming the first side wall and the second side wall includes: removing the first axial layer on the first area, and forming the first side wall on the surface of the composite layer on the first area; removing the first axial layer on the second area, and forming the second side wall on the surface of the composite layer on the second area.

[0014] Optionally, the process of removing the first axial core layer on the second region includes one of wet etching and dry etching or a combination of the two.

[0015] Optionally, the method for forming the second side wall includes: forming a second axial layer on the surface of the composite layer in the second area; forming a second side wall material layer covering the second axial layer and the surface of the composite layer; etching back the second side wall material layer to expose the surface of the composite layer and the surface of the second axial layer to form a second axial layer structure, the second axial layer structure including the second axial layer and the second side wall located on the side wall of the second axial layer; and removing the second axial layer.

[0016] Optionally, the material of the second axial core layer is different from the material of the surface of the composite layer, and the material of the second axial core layer is different from the material of the second sidewall; the material of the second axial core layer includes amorphous silicon.

[0017] Optionally, the process of removing the second axis layer includes one of wet etching and dry etching, or a combination of the two.

[0018] Optionally, the second side wall is also located on the surface of the composite layer on the first area, and the first side wall includes: the second side wall on the first area, and a third side wall located between the first axial layer and the second side wall on the first area; the method for forming the first axial layer structure includes: after forming the second axial layer structure, forming an auxiliary layer on the surface of the composite layer, and the auxiliary layer is also located on the side wall of the second axial layer structure; removing the second axial layer on the surface of the composite layer on the first area, forming a groove in the second side wall on the first area; forming a third side wall on the side wall of the groove; forming the first axial layer in the third side wall; after forming the first axial layer structure, removing the auxiliary layer.

[0019] Optionally, the material of the first axial core layer is different from the material of the surface of the composite layer, the material of the first axial core layer is different from the material of the third sidewall; and the material of the first axial core layer includes silicon carbide.

[0020] Optionally, the material of the third spacer is an insulating dielectric material, and the material of the third spacer includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0021] Optionally, the material of the auxiliary layer is different from the material of the surface of the composite layer, and the material of the auxiliary layer is different from the material of the second sidewall; the material of the auxiliary layer includes one of silicon oxide, amorphous carbon and photoresist.

[0022] Optionally, the process of removing the auxiliary layer includes one of wet etching and dry etching, or a combination of the two.

[0023] Optionally, it also includes: forming a first dummy gate across the first fin, the first dummy gate being located at a portion of the top surface and a portion of the sidewall surface of the first fin; forming a first source and drain region in one of the first fins on both sides of the first dummy gate; forming a second source and drain region in another first fin on both sides of the first dummy gate; forming an interlayer dielectric layer on the surface of the substrate and the surface of the first fin, the interlayer dielectric layer being also located at the sidewall of the first dummy gate and exposing the top surface of the first dummy gate; removing the first dummy gate and forming a first gate opening in the interlayer dielectric layer; removing the first sacrificial layer exposed at the bottom of the first gate opening and forming a first groove between the first channel layer exposed by the first gate opening; and forming a first gate on the first gate opening and in the first groove.

[0024] Optionally, the first source / drain region contains first doping ions, which are N-type or P-type ions; the second source / drain region contains second doping ions, which are N-type or P-type ions, and the second doping ions have a different conductivity type from the first doping ions.

[0025] Optionally, it also includes: forming a second dummy gate across the second fin, the second dummy gate being located on part of the top surface and part of the sidewall surface of the second fin; forming a third source and drain region in the second fin on both sides of the second dummy gate; the interlayer dielectric layer is also located on the second fin surface and the second dummy gate sidewall, and exposes the second dummy gate top surface; removing the second dummy gate, forming a second gate opening in the interlayer dielectric layer; removing the second sacrificial layer exposed at the bottom of the second gate opening, and forming a second groove between the second channel layer exposed by the second gate opening; forming a second gate in the second gate opening and the second groove on the second region.

[0026] Optionally, the material of the initial sacrificial layer is different from the material of the initial channel layer.

[0027] Optionally, the material of the initial sacrificial layer includes silicon germanium, and the material of the initial channel layer includes silicon.

[0028] Optionally, the material of the first sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0029] Optionally, the material of the first isolation structure is an insulating dielectric material, and the material of the first isolation structure includes silicon oxide; the material of the second isolation structure is an insulating dielectric material, and the material of the second isolation structure includes silicon oxide.

[0030] Optionally, the top surface of the second isolation structure is flush with the top surface of the first bottom structure.

[0031] Optionally, the process of removing the first axial layer includes one of a wet etching process and a dry etching process, or a combination of the two.

[0032] Optionally, the material of the first axial core layer is different from the material of the surface of the composite layer, the material of the first axial core layer is different from the material of the first sidewall; and the material of the first axial core layer includes amorphous silicon.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0034] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first dielectric material layer is formed on the substrate, the first dielectric material layer being located on the sidewalls of the initial first fin. After removing the first core layer, the initial first fin is etched using the first sidewalls and the first dielectric material layer as a mask to form two separate first fins and a first opening located between the two first fins, with a first isolation structure formed within the first opening. On the one hand, the first fin and the first opening are simultaneously formed using a single etching process using the first sidewalls as a mask, simplifying the production process and not relying on a patterned layer. The width and position of the first fin and the first opening are not restricted by pattern transfer lithography techniques, thus enabling self-aligned formation of the first isolation structure and reducing the requirements for the lithography process. On the other hand, when forming the first opening, the first dielectric material layer protects the substrate, the second fin, and the sidewalls of the initial first fin from etching damage. After forming the first isolation structure, the second isolation structure is formed by etching back the first dielectric material layer. The first dielectric material layer also provides material for forming the second isolation structure, reducing process steps and saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 2 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0036] Figures 3 to 12 1 is a schematic cross-sectional structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0037] Figures 13 to 26 It is a schematic cross-sectional structural diagram corresponding to each step in a semiconductor structure forming method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0038] As described in the background art, the performance of semiconductor devices formed in the prior art needs to be improved. This is now explained and analyzed in conjunction with a semiconductor structure.

[0039] Figures 1 to 2 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0040] Please refer to Figure 1 , providing a substrate 101 and a fin 102 located on the surface of the substrate 101 ; forming a hard mask material layer 103 on the surface of the substrate 101 , and forming a patterned photoresist layer 104 on the hard mask material layer 103 .

[0041] Please refer to Figure 2The hard mask material layer 103 is etched with the photoresist layer 104 to form a hard mask layer 105. The hard mask layer 105 partially exposes the surface of the fin 102. The substrate 101 is etched using the hard mask layer 105 as a mask to form a partition trench (not shown in the figure); the partition trench is filled with an insulating medium such as silicon oxide or silicon nitride to form a partition structure 106.

[0042] The above method is used in the fin isolation structure of the GAA device, wherein the fin 102 includes several overlapping sacrificial layers and a channel layer located between two adjacent sacrificial layers. After the fin 102 is formed, the isolation groove of the GAA device is formed by etching the substrate 101 using a patterned hard mask layer 105 as a film template, and the isolation groove is located in the substrate 101 and the fin 102. As the size of devices continues to shrink, the precision requirements for the photolithography process are becoming increasingly higher. Due to the influence of photolithography technology, when the pattern of the photoresist layer 105 is transferred to the substrate 101, the size of the pattern will change, thereby affecting the size of the isolation groove and the size of the fin 102, and also making the position of the isolation groove inaccurate. At the same time, the fin 102 and the isolation groove are formed by a two-step etching process, and the complex process increases production costs.

[0043] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure. A first dielectric material layer is formed on the substrate, the first dielectric material layer being positioned on the sidewalls of the initial first fin. After removing the first core layer, the initial first fin is etched using the first sidewalls and the first dielectric material layer as a mask to form two separate first fins and a first opening between the two first fins. A first isolation structure is formed within the first opening. On the one hand, the first fin and the first opening are simultaneously formed using the first sidewalls as a mask in a single etching process, simplifying the production process and not relying on a patterned layer. The width and position of the first fin and the first opening are not restricted by pattern transfer photolithography techniques, thereby enabling self-aligned formation of the first isolation structure and reducing photolithography process requirements. On the other hand, during the formation of the first opening, the first dielectric material layer protects the substrate, the second fin, and the sidewalls of the initial first fin from etching damage. After the first isolation structure is formed, the second isolation structure is formed by etching back the first dielectric material layer. The first dielectric material layer also provides material for forming the second isolation structure, simplifying the production process and saving production costs.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 3 to 12It is a schematic cross-sectional structural diagram corresponding to each step in a semiconductor structure forming method according to an embodiment of the present invention.

[0046] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a first region; forming a composite layer 201 on the substrate 200, wherein the composite layer 201 includes several overlapping initial sacrificial layers 202 and an initial channel layer 203 located between two adjacent initial sacrificial layers 202.

[0047] The substrate 200 is made of single crystal silicon. In other embodiments, the substrate may also be a silicon-on-insulator (SOI) structure or a germanium-on-insulator (Ge-on-insulator) structure.

[0048] The composite layer 201 is used to subsequently form a first fin.

[0049] The material of the initial sacrificial layer 202 is different from the material of the initial channel layer 203. The initial channel layer 203 is used to form a channel layer for forming a channel of a device. The initial sacrificial layer 202 is used to subsequently form a first sacrificial layer, which will be removed later. The material of the initial sacrificial layer 202 has a higher etching selectivity relative to the material of the initial channel layer 203, so that the impact on the first channel layer when the first sacrificial layer is subsequently removed is small; the material of the initial sacrificial layer 202 has a better lattice match with the material of the initial channel layer 203, so as to obtain a smooth interface between the initial sacrificial layer 202 and the initial channel layer 203, so that the surface of the first channel layer formed later is flat, which is conducive to obtaining a device with good performance.

[0050] The material of the initial sacrificial layer 202 includes silicon-germanium, and the material of the initial channel layer 203 includes silicon. In this embodiment, the material of the initial sacrificial layer 202 is silicon-germanium, and the material of the initial channel layer 203 is silicon. In other embodiments, the material of the initial channel layer 203 is Ge or GeSi. In other embodiments, the material of the initial sacrificial layer 202 can be ZnS, ZnSe, BeS, or GaP, etc.

[0051] In this embodiment, a hard mask layer 204 is further formed on the surface of the composite layer 201 .

[0052] The material of the hard mask layer 204 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride. In this embodiment, the material of the hard mask layer 204 is silicon oxynitride. The hard mask layer 204 is used to protect the composite layer 201 and prevent damage to the composite layer 201 during subsequent etching. The material of the hard mask layer 204 is different from the material of the first spacer to be formed later, and the material of the first spacer has a greater etching selectivity than the material of the hard mask layer 204, thereby preventing damage to the hard mask layer 204 during the subsequent etching process to form the first spacer.

[0053] In this embodiment, the top layer of the composite layer 201 is the initial channel layer 203 . In other embodiments, the top layer of the composite layer 201 is the initial sacrificial layer.

[0054] Please refer to Figure 4 A plurality of first axial core layer structures 205 are formed on a portion of the composite layer 201 on the first area. The first axial core layer structure 205 includes the first axial core layer 206 and two first sidewalls 207 on the sidewalls of the first axial core layer 206 .

[0055] The material of the first axial core layer 206 includes amorphous silicon; the material of the first axial core layer 206 is different from the material of the first sidewall 207 , and the material of the first axial core layer 206 is different from the material of the surface of the composite layer 201 .

[0056] The method for forming the first axial layer structure 205 includes: forming multiple first axial layers 206 on part of the composite layer 201; forming a first sidewall material layer (not marked in the figure) on the sidewall of the first axial layer 206 and the composite layer 201; etching back the first sidewall material layer to expose the surface of the composite layer 201 and the surface of the first axial layer 206 to form the first axial layer structure 205.

[0057] In this embodiment, the surface of the composite layer 201 is a hard mask layer 204, and therefore the material of the composite layer 201 surface is silicon oxynitride, and the material of the first axial layer 206 is amorphous silicon. In the subsequent etching process to remove the first axial layer 206, to avoid damage to the first sidewall spacer 207 and the material on the surface of the composite layer 201, the material of the first axial layer 206 needs to have a greater etch selectivity than the material on the surface of the composite layer 201; the material of the first axial layer 206 also needs to have a greater etch selectivity than the first sidewall spacer 207.

[0058] The material of the first sidewall spacer 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride oxycarbonate. In this embodiment, the material of the first sidewall spacer 207 is silicon nitride.

[0059] Please refer to Figure 5 , using the first axial layer structure 205 as a mask, etching the composite layer 201 and the substrate 200 to form an initial first fin 208 ; forming a first dielectric material layer 209 on the substrate 200 , the first dielectric material layer 209 is located on the sidewall of the initial first fin 208 .

[0060] In this embodiment, the hard mask layer 204 is etched to form a transitional first hard mask layer 210 .

[0061] The material of the first dielectric material layer 209 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the first dielectric material layer 209 is silicon oxide.

[0062] The first dielectric material layer 209 is formed by a chemical vapor deposition process. In this embodiment, the first dielectric material layer 209 is formed by an HDP CVD (high-density plasma chemical vapor deposition) process. The HDP CVD process uses high-density ion plasma bombardment and sputtering etching to prevent voids during chemical vapor deposition and achieve excellent step coverage.

[0063] Please refer to Figure 6 , remove the first axial layer 206; after removing the first axial layer 206, etch the initial first fin 208 using the first sidewall 207 as a mask to form two separate first fins 211, and a first opening 212 located between the two first fins 211, the first fin 211 including a first bottom structure 213 located on the first area, a plurality of overlapping first sacrificial layers 214 located on the first bottom structure 213, and a first channel layer 215 located between two adjacent first sacrificial layers 214.

[0064] The process of removing the first core layer 206 includes one of a wet etching process and a dry etching process, or a combination of the two. In this embodiment, the process of removing the first core layer 206 is a wet etching process.

[0065] In this embodiment, the transitional first hard mask layer 210 is etched to form a first hard mask layer 216 .

[0066] The first opening 212 is used for subsequently forming a first isolation structure.

[0067] On the one hand, the first fin 211 and the first opening 212 are formed simultaneously by etching in one step using the first sidewall 207 as a mask, which simplifies the production process and does not rely on a patterned layer. The width and position of the first fin 211 and the first opening 212 are not limited by the photolithography technology of pattern transfer, so self-alignment can be achieved to form the first isolation structure, reducing the requirements for the photolithography process. On the other hand, when forming the first opening 212, the first dielectric material layer 209 is used to protect the substrate 200 and the initial first fin sidewall from etching damage. Subsequently, after the first isolation structure is formed, the second isolation structure is formed by etching back the first dielectric material layer 209. The first dielectric material layer 209 also provides material for forming the second isolation structure, reducing the process and saving production costs.

[0068] Please refer to Figure 7 , a first isolation structure 217 is formed in the first opening 212; after the first isolation structure 217 is formed, the first dielectric material layer 209 is etched back to form a second isolation structure 218, and the top surface of the second isolation structure 218 is lower than the top surface of the first fin 218.

[0069] The material of the first isolation structure 217 is an insulating dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the first isolation structure 217 is silicon oxide.

[0070] The first isolation structure 217 is formed by a chemical vapor deposition process. In this embodiment, the first isolation structure 217 is formed by a high-density cyclic evaporation (HDP) CVD process. The advantages of the HDP CVD process are as described above and will not be further elaborated here.

[0071] The second isolation structure 218 is formed by etching back the first dielectric material layer 209, so the material of the second isolation structure 218 is the same as the first dielectric material layer 209. In this embodiment, the material of the second isolation structure 218 is silicon oxide.

[0072] The first isolation structure 217 and the second isolation structure 218 are used for electrical insulation isolation between different devices.

[0073] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8In the top view along the Y direction, a first dummy gate 219 is formed across the first fin 211, and the first dummy gate 219 is located on part of the top surface and part of the sidewall surface of the first fin 211; a first source and drain region 220 is formed in one of the first fins 211 on both sides of the first dummy gate 219; and a second source and drain region 221 is formed in the other first fin 211 on both sides of the first dummy gate 219.

[0074] In this embodiment, the first spacer 207 and the first hard mask layer 216 are removed before forming the first dummy gate 219. In other embodiments, the first hard mask layer is retained and only the first spacer is removed; or both the first spacer and the first hard mask layer are retained.

[0075] The method for forming the first dummy gate 219 includes: forming a first dummy gate material layer (not marked in the figure) on the substrate 200; forming a patterned layer (not marked in the figure) on the first dummy gate material layer; using the patterned layer as a mask, etching the first dummy gate material layer until the surface of the substrate is exposed to form the first dummy gate 219.

[0076] In this embodiment, the surface of the first dummy gate 219 is flush with the first isolation structure 217. In other embodiments, the first dummy gate spans across two adjacent first fins and covers a portion of the surface of the first isolation structure 217.

[0077] The first source / drain region 220 has a first dopant ion, which is either N-type or P-type. The second source / drain region 221 has a second dopant ion, which is either N-type or P-type, and has a different conductivity type from the first dopant ion. The first isolation structure 217 is used to isolate the PMOS and NMOS devices. In this embodiment, the first source / drain region 220 has an N-type dopant ion, while the second source / drain region 221 has a P-type dopant ion.

[0078] In this embodiment, the first source / drain region 220 is formed first and then the second source / drain region 221 is formed. In another embodiment, the second source / drain region 221 is formed first and then the first source / drain region 220 is formed.

[0079] Please refer to Figure 10 An interlayer dielectric layer 223 is formed on the surface of the substrate 200 and the surface of the first fin 211 . The interlayer dielectric layer 223 also covers the sidewalls of the first dummy gate 219 and exposes the top surface of the first dummy gate 219 .

[0080] The interlayer dielectric layer 223 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0081] The material of the interlayer dielectric layer 223 includes silicon oxide.

[0082] In this embodiment, the method for forming the interlayer dielectric layer 223 includes: using a chemical vapor deposition process to form an interlayer dielectric material layer on the surface of the substrate 200, and the interlayer dielectric material layer is also located on the sidewalls and surface of the first pseudo gate 219; using a mechanical chemical polishing process to flatten the interlayer dielectric material layer until the top surface of the first pseudo gate 219 is exposed.

[0083] Please refer to Figure 11 , remove the first dummy gate 219 (such as Figure 10 As shown), a first gate opening 224 is formed in the interlayer dielectric layer 223; the first sacrificial layer 214 (as shown) exposed at the bottom of the first gate opening 224 is removed. Figure 10 As shown in FIG, a first groove 225 is formed between the first channel layers 215 exposed by the first gate opening 224 .

[0084] The process for removing the first dummy gate 219 includes a wet etching process. In this embodiment, the process for removing the first dummy gate 219 is a wet etching process. The method for removing the first dummy gate 219 includes: using a solution including tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process for removing the first dummy gate 219, the first dummy gate 219 can have a large etching selectivity relative to the interlayer dielectric 223 and the first isolation structure 217.

[0085] The process of removing the first sacrificial layer 214 exposed at the bottom of the first gate opening 224 includes a wet etching process.

[0086] Please refer to Figure 12 A first gate 226 is formed in the first gate opening 224 and the first groove 225 on the first region.

[0087] The first gate 226 is made of metal.

[0088] The first gate 226 is formed by an atomic layer deposition process, which has a good step coverage, so that the first gate opening 224 and the first groove 225 are well filled.

[0089] Figures 13 to 26 It is a schematic cross-sectional structural diagram corresponding to each step in a semiconductor structure forming method according to another embodiment of the present invention.

[0090] Please refer to Figure 13 , providing a substrate 300, wherein the substrate 300 includes a first region I and a second region II; forming a composite layer 301 on the substrate 300, wherein the composite layer 301 includes several overlapping initial sacrificial layers 302 and an initial channel layer 303 located between two adjacent initial sacrificial layers 302.

[0091] In this embodiment, a hard mask layer 304 is further formed on the surface of the composite layer 301 .

[0092] The material of the hard mask layer 304 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the hard mask layer 304 is silicon oxynitride. The hard mask layer 304 is used to protect the composite layer 301 and prevent damage to the composite layer 301 during subsequent etching processes.

[0093] Subsequently, a plurality of first axial layer structures are formed on the surface of part of the composite layer 301 on the first area I, wherein the first axial layer structure includes the first axial layer and two first side walls of the first axial layer sidewall; using the first axial layer structure as a mask, the composite layer 301 and the substrate 300 are etched to form an initial first fin.

[0094] In this embodiment, the composite layer 301 is also located on the second region II; before forming the first fin, a plurality of second fins are formed on the second region II. Figures 14 to 18 .

[0095] Please refer to Figure 14 , forming a second axial core layer 305 on the surface of the composite layer 301 on the second region II; forming a second sidewall material layer (not shown in the figure) covering the second axial core layer 305 and the surface of the composite layer 301; etching back the second sidewall material layer to expose the surface of the composite layer 301 and the surface of the second axial core layer 305, forming a second axial core layer structure 307, the second axial core layer structure 307 including the second axial core layer 305 and a second sidewall 306 located on the sidewall of the second axial core layer 305.

[0096] The material of the second axis core layer 305 includes amorphous silicon. In this embodiment, the material of the second axis core layer 305 is amorphous silicon.

[0097] The material of the second axial core layer 305 is different from the material of the second sidewall 306 . The material of the second axial core layer 305 is different from the material of the surface of the composite layer 301 .

[0098] In this embodiment, the surface of the composite layer 301 is a hard mask layer 304, so the material of the composite layer 301 surface is silicon oxynitride, and the material of the second axial layer 305 is amorphous silicon. The second axial layer 305 will subsequently be removed, leaving the two second sidewall spacers on the sidewalls of the second axial layer. To avoid damage to the second sidewall spacers and the material on the surface of the composite layer 301, during the etching process to remove the second axial layer 305, the material of the second axial layer 305 must have a greater etch selectivity than the material on the surface of the composite layer 301; the material of the second axial layer 305 must also have a greater etch selectivity than the second sidewall spacers 306.

[0099] The material of the second sidewall spacer 306 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride oxycarbonate. In this embodiment, the material of the second sidewall spacer 306 is silicon nitride.

[0100] In this embodiment, the second spacer 306 is further located on the surface of the composite layer 301 in the first region I; the first spacer includes the second spacer 306 in the first region and a third spacer located between the first axial layer and the second spacer 306 in the first region I. In another embodiment, the second spacer 306 is further located on the surface of the composite layer 301 in the first region I, and the second spacer 306 in the first region I serves as the first spacer.

[0101] In another embodiment, the method for forming the first core layer structure includes: forming multiple first core layers on a portion of the composite layer; forming a first spacer material layer on the sidewalls of the first core layer and the composite layer; etching back the first spacer material layer to expose the surface of the composite layer and the surface of the first core layer, thereby forming the first core layer structure. The second spacer is formed simultaneously with the first spacer, and the method for forming the first and second spacers includes: the first core layer structure is also located on a portion of the surface of the composite layer in the second region; removing the first core layer in the first region, and forming the first spacer on the surface of the composite layer in the first region; removing the first core layer in the second region, and forming the second spacer on the surface of the composite layer in the second region.

[0102] In this embodiment, the method for forming the first core layer structure is as follows: Figures 15 and 16 .

[0103] Please refer to Figure 15After forming the second axial layer structure 307, an auxiliary layer 308 is formed on the surface of the composite layer 301, and the auxiliary layer 308 is also located on the side wall of the second axial layer structure 307; the second axial layer 305 on the surface of the composite layer 301 on the first area I is removed, and a groove 309 is formed in the second sidewall 306 on the first area I.

[0104] Specifically, in this embodiment, an auxiliary layer 308 is formed on the surface of the hard mask layer 304 on the surface of the composite layer 301 .

[0105] The auxiliary layer 308 is made of a material selected from the group consisting of silicon oxide, amorphous carbon, and photoresist. In this embodiment, the auxiliary layer 308 is made of silicon oxide.

[0106] The material of the auxiliary layer 308 is different from the material of the surface of the composite layer 301 , and the material of the auxiliary layer 308 is different from the material of the second sidewall 306 .

[0107] Subsequently, it is necessary to remove the auxiliary layer 308 and retain the second side wall 306 on the surface of the composite layer 301. In order to avoid damage to the material on the surface of the composite layer 301 and the second side wall 306 during the etching process of removing the auxiliary layer 308, the material of the auxiliary layer 308 has a larger etching selectivity relative to the material of the second side wall 306 during the process of removing the auxiliary layer 308; the auxiliary layer 308 has a larger etching selectivity than the material on the surface of the composite layer 301.

[0108] In this embodiment, the surface of the composite layer 301 is a hard mask layer 304 , the material of the surface of the composite layer 301 is silicon oxynitride, and the material of the auxiliary layer 308 is silicon oxide.

[0109] The process of removing the second axial core layer 305 from the surface of the composite layer 301 in the first region I includes one of dry etching and wet etching, or a combination of the two. In this embodiment, the process of removing the second axial core layer 305 from the surface of the composite layer 301 in the first region I is a wet etching process.

[0110] Please refer to Figure 16 , forming a third spacer 310 on the sidewall of the trench 309 ; and forming the first axial core layer 311 in the third spacer 310 .

[0111] The method for forming the third side wall 310 is: covering the surface of the auxiliary layer 308, the surface of the second axial layer structure 307 and the surface of the groove 309 to form a third side wall material layer (not marked in the figure), and etching the third side wall material layer until the surface of the auxiliary layer 308, the surface of the second axial layer structure 307, and the bottom surface of the groove 309 are exposed.

[0112] The material of the third spacer 310 is an insulating dielectric material, and the material of the third spacer 310 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the third spacer 310 is silicon nitride.

[0113] The first spacer 312 includes the second spacer 306 on the first region I and a third spacer 310 between the first axial layer 311 and the second spacer 306 on the first region I. The first spacer 312 is used as a mask to form a first fin on the first region I.

[0114] The first axis layer structure includes the first axis layer 311 and two first spacers 312 on the sidewalls of the first axis layer 311. The first axis layer structure is used as a mask to form an initial first fin on the first region I later.

[0115] The material of the first core layer 311 includes silicon carbide. In this embodiment, the material of the first core layer 311 is silicon carbide, and the material of the second sidewall spacer 306 and the material of the third sidewall spacer 310 are both silicon nitride.

[0116] The first core layer 311 will subsequently be removed, while the first sidewalls 312 on the surface of the composite layer 304 will remain. To prevent damage to the material on the surface of the composite layer 304 and the first sidewalls 312 during the removal of the first core layer 311, the material of the first core layer 311 is different from the material on the surface of the composite layer 304, and the material of the first core layer 311 is different from the material of the first sidewalls 312. During the removal of the first core layer 311, the material of the first core layer 311 has a greater selectivity than the material on the surface of the composite layer 304, and the first core layer 311 has a greater selectivity than the first sidewalls 312.

[0117] Please refer to Figure 17 After forming the first axis layer structure, the auxiliary layer 308 is removed; and the second axis layer 305 on the second region II is removed.

[0118] The process of removing the auxiliary layer 308 includes one of wet etching and dry etching or a combination of the two. In this embodiment, the process of removing the auxiliary layer 308 is a wet etching process.

[0119] The process of removing the second axis layer 305 on the second region II includes one or both of dry etching and wet etching processes.

[0120] In this embodiment, the processes for removing the auxiliary layer 308 and the second core layer 305 are both dry etching, and the first auxiliary layer 308 and the second core layer 305 are removed in two steps. In other embodiments, the first auxiliary layer 311 and the first core layer 308 are removed simultaneously to reduce the number of steps and lower production costs.

[0121] Please refer to Figure 18 , using the second sidewall 306 as a mask, etching the composite layer 301 and the substrate to form a plurality of mutually discrete second fins 313 located on the second region II; using the first axial layer structure as a mask, etching the composite layer 301 and the substrate 300 to form an initial first fin 318.

[0122] The second fin 313 includes a second bottom structure 314 located on the second region II, a plurality of overlapping second sacrificial layers 315 located on the second bottom structure 314 , and a second channel layer 316 located between two adjacent second sacrificial layers 315 .

[0123] In this embodiment, the hard mask layer 304 on the first region I is etched to form a second hard mask layer 317 .

[0124] In this embodiment, the initial first fin 318 and the second fin 313 are formed simultaneously. The initial first fin 318 is used to subsequently form the first fin, which is formed after the second fin is formed. In other embodiments, the second fin and the first fin can be formed simultaneously.

[0125] In this embodiment, the hard mask layer 304 on the first region I is etched to form an initial first hard mask layer 319 .

[0126] Please refer to Figure 19 , a first dielectric material layer 320 is formed on the substrate 300 , and the first dielectric material layer 320 is located on the sidewall of the initial first fin 318 .

[0127] The first dielectric material layer 320 is also located on the sidewalls of the second fin 313 .

[0128] The material of the first dielectric material layer 320 is an insulating dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the first dielectric material layer 320 is silicon oxide.

[0129] The first dielectric material layer 320 is formed by a chemical vapor deposition process. In this embodiment, the first dielectric material layer 320 is formed by a high-density cyclic chemical vapor deposition (HDP CVD) process. The advantages of the HDP CVD process are not described in detail.

[0130] Please refer to Figure 20 , remove the first axial layer 311; after removing the first axial layer 311, etch the initial first fin 318 using the first sidewall 312 as a mask to form two separate first fins 321, and a first opening 322 located between the two first fins 321, the first fin 321 includes a first bottom structure 323 located on the first area I, several layers of overlapping first sacrificial layers 324 located on the first bottom structure 323, and a first channel layer 325 located between two adjacent first sacrificial layers 324.

[0131] The process of removing the first axial core layer 311 includes one or both of dry etching and wet etching. In this embodiment, the process of removing the first axial core layer 311 is wet etching.

[0132] In this embodiment, the initial first hard mask layer 319 is etched to form a first hard mask layer 326 , and the first hard mask layer 326 is located between the first fin 321 and the first spacer 312 .

[0133] Please refer to Figure 21 , a first isolation structure 327 is formed in the first opening 322; after the first isolation structure 327 is formed, the first dielectric material layer 320 is etched back to form a second isolation structure 328, and the top surface of the second isolation structure 328 is lower than the top surface of the first fin 312.

[0134] In this embodiment, specifically, the top surface of the second isolation structure 328 is flush with the top surface of the first bottom structure 323 .

[0135] The material of the first isolation structure 327 is an insulating dielectric material. In this embodiment, the material of the first isolation structure 327 is silicon oxide.

[0136] The first isolation structure 327 is formed by a chemical vapor deposition process. In this embodiment, the first isolation structure 327 is formed by a high-density cyclic chemical vapor deposition (HDP) CVD process. The advantages of the HDP CVD process are not described in detail.

[0137] The second isolation structure 328 covers the sidewalls of the first bottom structure 323 of the first fin 321 . The second isolation structure 328 also covers the sidewalls of the second bottom structure 314 of the second fin 313 .

[0138] The second isolation structure 328 is formed by etching back the first dielectric material layer 320, so the material of the second isolation structure 328 is the same as the first dielectric material layer 320. In this embodiment, the material of the second isolation structure 328 is silicon oxide.

[0139] The first isolation structure 327 and the second isolation structure 328 are used to electrically isolate different devices. Specifically, the first isolation structure 327 is used as an isolation device for PMOS devices and NMOS devices. Subsequently, P-type doped regions and N-type doped regions will be formed on both sides of the first isolation structure 327, respectively.

[0140] Please refer to Figure 22 and Figure 23 , Figure 23 yes Figure 22 In the top view along the Y direction, a first dummy gate 329 is formed across the first fin 321, and the first dummy gate 329 is located on a portion of the top surface and a portion of the side wall surface of the first fin 321; a second dummy gate 330 is formed across the second fin 313, and the second dummy gate 330 is located on a portion of the top surface and a portion of the side wall surface of the second fin 313.

[0141] In this embodiment, before forming the first dummy gate 329 and the second dummy gate 330, the second sidewall spacer 306 (eg, Figure 21 As shown) and the second hard mask layer 317 (as shown Figure 21 Remove the first sidewall 312 (as shown); Figure 21 ) and the first hard mask layer 326 (as shown Figure 21 In other embodiments, the first hard mask layer and the second hard mask layer are retained, and only the first spacer and the second spacer are removed; or the first spacer, the first hard mask layer, the second spacer, and the second hard mask layer are all retained.

[0142] In this embodiment, the top of the first dummy gate 329 is flush with the top surface of the first isolation structure 327. In other embodiments, the first dummy gate spans across two adjacent first fins and covers a portion of the surface of the first isolation structure 327.

[0143] In this embodiment, the first dummy gate 329 and the second dummy gate 330 are formed simultaneously, and the formation method thereof includes: forming a dummy gate material layer (not marked in the figure) on the surface of the substrate 300, and the dummy gate material layer also covers the top and side walls of the first fin 321 and the second fin 313; forming a patterned layer (not marked in the figure) on the surface of the dummy gate material layer, and the patterned layer exposes the surface of the substrate 300 and exposes part of the top and side walls of the first fin 321 and the second fin 313; etching the dummy gate material layer with the patterned layer to form the first dummy gate 329 and the second dummy gate 330.

[0144] The material of the first dummy gate 329 and the second dummy gate 330 includes silicon. In this embodiment, the material of the first dummy gate 329 and the second dummy gate 330 is polysilicon.

[0145] Please continue to refer to Figure 23 , a first source / drain region 332 is formed in one of the first fins 321 on both sides of the first dummy gate 329 ; a second source / drain region 333 is formed in the other first fin 321 on both sides of the first dummy gate 329 ; and a third source / drain region 331 is formed in the second fin 313 on both sides of the second dummy gate 330 .

[0146] The first source / drain region 332 contains a first dopant ion, which is either an N-type or P-type ion. The second source / drain region 333 contains a second dopant ion, which is either an N-type or P-type ion, and has a different conductivity type from the first dopant ion. The third source / drain region 331 contains a third dopant ion, which is either an N-type or P-type ion. In this embodiment, the second fin 313 is used to form an N-type device, and the third dopant ion is an N-type ion. P-type and N-type dopant regions are formed on both sides of the first isolation structure 327, respectively. The first dopant ion is an N-type ion, and the second dopant ion is a P-type ion.

[0147] Please refer to Figure 24 An interlayer dielectric layer 334 is formed on the surface of the substrate 300 and the surface of the first fin 321. The interlayer dielectric layer 334 is also located on the sidewalls of the first dummy gate 329 and exposes the top surface of the first dummy gate 329. The interlayer dielectric layer 334 is also located on the surface of the second fin 313 and the sidewalls of the second dummy gate 330 and exposes the top surface of the second dummy gate 330.

[0148] The interlayer dielectric layer 334 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0149] The material of the interlayer dielectric layer 334 includes silicon oxide.

[0150] In this embodiment, the method for forming the interlayer dielectric layer 334 includes: using chemical vapor deposition to form an interlayer dielectric material layer (not marked in the figure) on the surface of the substrate 300, and the interlayer dielectric material layer is also located on the side walls and surfaces of the first dummy gate 329 and the second dummy gate 330; using a mechanical chemical polishing process to flatten the interlayer dielectric material layer until the top surfaces of the first dummy gate 329 and the second dummy gate 330 are exposed.

[0151] Please refer to Figure 25 , remove the first dummy gate 329, and form a first gate opening 335 in the interlayer dielectric layer 334; remove the second dummy gate 330, and form a second gate opening 337 in the interlayer dielectric layer 334; remove the first sacrificial layer 324 (such as the first sacrificial layer 324) exposed at the bottom of the first gate opening 335 Figure 24 As shown), a first groove 336 is formed between the first channel layer 325 exposed by the first gate opening 335; the second sacrificial layer 315 exposed at the bottom of the second gate opening 337 is removed (as shown Figure 24 As shown in FIG. 3 , a second groove 338 is formed between the second channel layers 322 exposed by the second gate opening 337 .

[0152] Removing the first dummy gate 329 includes a wet etching process; and removing the second dummy gate 330 includes a wet etching process. In this embodiment, to save process steps, the first dummy gate 329 and the second dummy gate 330 are removed simultaneously using a wet etching process. The method for removing the first dummy gate 329 and the second dummy gate 330 includes: using a solution including tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process of removing the first dummy gate 329 and the second dummy gate 330, both the first dummy gate 329 and the second dummy gate 330 can have a large selectivity.

[0153] The process for removing the first sacrificial layer 324 exposed at the bottom of the first gate opening 335 includes a wet etching process; the process for removing the second sacrificial layer 315 exposed at the bottom of the second gate opening 337 also includes a wet etching process. In this embodiment, the first sacrificial layer 324 and the second sacrificial layer 315 are removed using a single etching step, reducing process steps and saving production costs. The etching process has a high selectivity for both the first sacrificial layer 324 and the second sacrificial layer 315, thereby protecting the first channel layer 325 and the second channel layer 316 from damage.

[0154] The first groove 336 is formed after the first sacrificial layer 324 is removed, and occupies the position of the original first sacrificial layer 324. In this embodiment, the first groove 336 is also located between the first channel layer 325 and the first bottom structure 323.

[0155] Please refer to Figure 25 A first gate 339 is formed in the first gate opening 335 and the first groove 336 on the first region I; and a second gate 340 is formed in the second gate opening 327 and the second groove 328 on the second region II.

[0156] The first gate 339 and the second gate 340 are made of metal.

[0157] The first gate 339 and the second gate 340 are formed by an atomic layer deposition process, which has good step coverage, so that the first gate opening 335 (the second gate opening 327 ) and the first groove 336 (the second groove 328 ) are well filled.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a composite layer on the substrate, the composite layer comprising a plurality of overlapping initial sacrificial layers and an initial channel layer located between two adjacent initial sacrificial layers; forming a second axial core layer on the surface of the composite layer in the first area and the second area; forming a second sidewall material layer covering the second core layer and the surface of the composite layer; Etching back the second sidewall material layer to expose the surface of the composite layer and the surface of the second axial layer, thereby forming a second axial layer structure, wherein the second axial layer structure includes the second axial layer and a second sidewall located on a sidewall of the second axial layer; After forming the second axial core layer structure, forming an auxiliary layer on the surface of the composite layer, wherein the auxiliary layer is also located on the side wall of the second axial core layer structure; removing the second axial core layer on the surface of the composite layer in the first area, and forming a groove in the second sidewall in the first area; forming a third sidewall spacer on the sidewall of the trench; forming a first axial core layer within the third spacer to form a plurality of first axial core layer structures on a portion of the surface of the composite layer on the first region, wherein the first axial core layer structure includes the first axial core layer and two first spacers on the sidewalls of the first axial layer, and the first spacers include: the second spacer on the first region, and a third spacer located between the first axial core layer and the second spacer on the first region; After forming the first core layer structure, removing the auxiliary layer; removing the second core layer to form a plurality of second sidewalls on the surface of the composite layer on the second area; Etching the composite layer and the substrate using the second sidewall as a mask to form a plurality of mutually separated second fins located on the second region; Using the first axial layer structure as a mask, etching the composite layer and the substrate to form an initial first fin; forming a first dielectric material layer on the substrate, wherein the first dielectric material layer is located on a sidewall of the initial first fin; removing the first core layer; After removing the first core layer, etching the initial first fin using the first sidewall as a mask to form two separate first fins and a first opening between the two first fins, wherein the first fin includes a first bottom structure located on the first region, a plurality of overlapping first sacrificial layers located on the first bottom structure, and a first channel layer located between two adjacent first sacrificial layers; forming a first isolation structure in the first opening; After forming the first isolation structure, the first dielectric material layer is etched back to form a second isolation structure, wherein a top surface of the second isolation structure is lower than a top surface of the first fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: The second fin includes a second bottom structure located on the second region, a plurality of overlapping second sacrificial layers located on the second bottom structure, and a second channel layer located between two adjacent second sacrificial layers.

3. The method for forming a semiconductor structure according to claim 2, wherein: The second isolation structure is also located on the sidewall of the second fin, and a top surface of the second isolation structure is flush with a top surface of the second bottom structure.

4. The method for forming a semiconductor structure according to claim 2, wherein: The second fin is formed before forming the first fin.

5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second sidewall spacer is an insulating dielectric material, and the material of the second sidewall spacer includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second axial core layer is different from the material of the surface of the composite layer, and the material of the second axial core layer is different from the material of the second sidewall; the material of the second axial core layer includes amorphous silicon.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the second axis layer includes one of wet etching and dry etching or a combination of the two.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first axial core layer is different from the material of the surface of the composite layer, and the material of the first axial core layer is different from the material of the third sidewall spacer; the material of the first axial core layer includes silicon carbide.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the third spacer is an insulating dielectric material, and the material of the third spacer includes: one or more insulating materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the auxiliary layer is different from the material of the surface of the composite layer, and the material of the auxiliary layer is different from the material of the second sidewall; the material of the auxiliary layer includes one of silicon oxide, amorphous carbon and photoresist.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the auxiliary layer includes one of wet etching and dry etching or a combination of the two.

12. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: forming a first dummy gate across the first fin, the first dummy gate being located on a portion of the top surface and a portion of the sidewall surface of the first fin; and forming a first source and drain region in one of the first fins on both sides of the first dummy gate; forming a second source / drain region in the other first fin on both sides of the first dummy gate; forming an interlayer dielectric layer on the surface of the substrate and the surface of the first fin, wherein the interlayer dielectric layer is also located on the sidewalls of the first dummy gate and exposes the top surface of the first dummy gate; removing the first dummy gate and forming a first gate opening in the interlayer dielectric layer; The first sacrificial layer exposed at the bottom of the first gate opening is removed, and a first groove is formed between the first channel layers exposed by the first gate opening; and a first gate is formed in the first gate opening and the first groove on the first region.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first source / drain region contains first doping ions, which are N-type or P-type ions; the second source / drain region contains second doping ions, which are N-type or P-type ions, and the second doping ions have a different conductivity type from the first doping ions.

14. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: forming a second dummy gate across the second fin, wherein the second dummy gate is located on a portion of a top surface and a portion of a sidewall surface of the second fin; forming a third source and drain region in the second fin portion on both sides of the second dummy gate; The interlayer dielectric layer is also located on the surface of the second fin and the sidewall of the second dummy gate, and exposes the top surface of the second dummy gate; the second dummy gate is removed to form a second gate opening in the interlayer dielectric layer; removing the second sacrificial layer exposed at the bottom of the second gate opening, and forming a second groove between the second channel layers exposed by the second gate opening; A second gate is formed on the second region and in the second gate opening and the second groove.

15. The method for forming a semiconductor structure according to claim 1, wherein: A material of the initial sacrificial layer is different from a material of the initial channel layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the initial sacrificial layer includes silicon germanium, and the material of the initial channel layer includes silicon.

17. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

18. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first isolation structure is an insulating dielectric material, and the material of the first isolation structure includes silicon oxide; the material of the second isolation structure is an insulating dielectric material, and the material of the second isolation structure includes silicon oxide.

19. The method for forming a semiconductor structure according to claim 1, wherein: A top surface of the second isolation structure is flush with a top surface of the first bottom structure.

20. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first axis layer includes one of a wet etching process and a dry etching process or a combination of the two.

21. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first axial core layer is different from the material of the surface of the composite layer, and the material of the first axial core layer is different from the material of the first sidewall; the material of the first axial core layer includes amorphous silicon.

Images