Thin-film transistors and their fabrication methods

Abstract

This application provides a thin-film transistor and a method for fabricating the same. The method includes providing a substrate; forming a gate on the substrate; forming a gate insulating layer on the substrate, such that the gate insulating layer covers the gate; forming an amorphous silicon layer on the gate insulating layer; wherein the ratio of hydrogen to silane is controlled to be greater than or equal to 8; forming a doped layer on the amorphous silicon layer; forming source and drain metal layers on the doped layer; and etching the source and drain metal layers and the doped layer to obtain the source and drain electrodes. This application solves the problem that in existing liquid crystal displays (LCDs), the off-state current of the TFT increases significantly at high temperatures, leading to screen flickering or image distortion, thus affecting display quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor and a preparation method thereof. BACKGROUND

[0002] A thin film transistor (TFT) is a kind of field effect transistor, which includes a source-drain electrode, an active layer (also known as a channel layer), a gate electrode and an insulating layer (also known as a dielectric layer). As a core driving element of an active matrix electronic device, the thin film transistor is widely used in active organic light emitting diode displays and liquid crystal displays.

[0003] According to the difference of semiconductor materials in the TFT, the TFT can be generally divided into amorphous silicon (A-Si) semiconductor TFT, polycrystalline silicon (Poly-Si) semiconductor TFT and oxide semiconductor TFT. Since the amorphous silicon semiconductor TFT has the advantages of simple process, low cost and easy large-area process, etc., the current liquid crystal display mostly uses the amorphous silicon semiconductor TFT; and with the further demand for ultra-narrow frame and cost reduction, the liquid crystal display has been widely used in GDL (Gate driver less) circuit driving technology. However, with the increase of the use temperature of the liquid crystal display, the off-state current of the TFT in the GDL circuit will greatly increase, noise will occur, thereby causing the liquid crystal display to have a flashing screen or a picture difference, and affecting the display quality. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a thin film transistor and a preparation method thereof, by setting the content ratio of silane and hydrogen gas for preparing the amorphous silicon layer to be greater than or equal to 8, the problem that the off-state current of the TFT in the existing liquid crystal display will greatly increase under high temperature, causing the liquid crystal display to have a flashing screen or a picture difference, and affecting the display quality is solved.

[0005] To achieve the above purpose, the technical scheme adopted by the present application is to provide a preparation method of a thin film transistor, comprising:

[0006] providing a substrate;

[0007] forming a gate electrode on the substrate;

[0008] forming a gate insulating layer on the substrate, so that the gate insulating layer covers the gate electrode;

[0009] forming an amorphous silicon layer on the gate insulating layer; wherein the ratio of hydrogen gas to silane is greater than or equal to 8;

[0010] forming a doped layer on the amorphous silicon layer;

[0011] Forming a source-drain metal layer on the doped layer;

[0012] Etching the source-drain metal layer and the doped layer to obtain a source electrode and a drain electrode.

[0013] The preparation method of the thin film transistor provided by the embodiment of the present application controls the content ratio of silane and hydrogen required by the amorphous silicon layer to be greater than or equal to 8 when the amorphous silicon layer is prepared, changes the proportion of the reaction gas for preparing the amorphous silicon layer, increases the content of Si-H bonds, widens the band gap, improves the performance of the amorphous silicon layer, reduces the initial off-state current of the thin film transistor, ensures that the thin film transistor can be in a low-current off state under a high-temperature condition, avoids the occurrence of flickering or image distortion of the liquid crystal display, and improves the display quality.

[0014] Optionally, the etching the source-drain metal layer and the doped layer to obtain a source electrode and a drain electrode comprises:

[0015] Forming a photoresist layer on the source-drain metal layer;

[0016] Patterning the photoresist layer;

[0017] Etching the source-drain metal layer and the doped layer according to the pattern of the photoresist layer to form a source electrode, a drain electrode, and a first channel and a second channel located between the source electrode and the drain electrode.

[0018] Optionally, the length of the first channel and the length of the second channel are both greater than 3 microns.

[0019] Optionally, the orthographic projection of the first channel on the substrate and the orthographic projection of the second channel on the substrate are both located within the orthographic projection of the gate on the substrate.

[0020] Optionally, the orthographic projection of the amorphous silicon layer on the substrate is located within the orthographic projection of the gate on the substrate.

[0021] Optionally, the amorphous silicon layer has a first side surface and a second side surface in the length direction of the first channel;

[0022] The source-drain metal layer covers the first side surface and the second side surface and is connected with the gate insulating layer.

[0023] Optionally, after the etching the source-drain metal layer and the doped layer according to the pattern of the photoresist layer to form a source electrode, a drain electrode, and a first channel and a second channel located between the source electrode and the drain electrode, the method further comprises:

[0024] Forming a passivation layer on the surface of the source electrode, the drain electrode, the first channel, and the second channel.

[0025] The preparation method of the thin film transistor provided by the application has the beneficial effect that, compared with the prior art, the ratio of the content of hydrogen to the content of silane is controlled to be greater than or equal to 8 when the amorphous silicon layer is prepared, so that the content of hydrogen bonds is increased, the content of Si-H bonds in the amorphous silicon layer is increased, the band gap is widened, the performance of the amorphous silicon layer is improved, the initial off-state current of the thin film transistor is reduced, and even if the off-state current of the thin film transistor is increased in a high-temperature state, the thin film transistor can still be in a low-current off state, so that the liquid crystal display is prevented from flickering or having a picture difference, and the display quality is improved.

[0026] The application further provides a thin film transistor prepared according to the method of any one of the above embodiments, comprising a substrate, a gate electrode, a gate insulating layer, an amorphous silicon layer, a doped layer, and a source electrode and a drain electrode; the gate electrode is located on the substrate; the gate insulating layer is located on the substrate and covers the gate electrode; the amorphous silicon layer is located on the gate insulating layer, and the ratio of the content of hydrogen to the content of silane in the amorphous silicon layer is greater than or equal to 8; the doped layer is located on the amorphous silicon layer; and the source electrode and the drain electrode are respectively located on the opposite ends of the doped layer.

[0027] Optionally, the amorphous silicon layer comprises a source region corresponding to the source electrode, a drain region corresponding to the drain electrode, and a first channel region and a second channel region located between the source region and the drain region.

[0028] When the thin film transistor is turned on, the first channel region forms a first conductive channel, the second channel region forms a second conductive channel, and the distance between the source region and the drain region is greater than the sum of the lengths of the first conductive channel and the second conductive channel.

[0029] Optionally, the length of the first channel region and the length of the second channel region are both greater than 3 microns.

[0030] The thin film transistor provided by the application has the beneficial effect that the preparation method of any one of the above embodiments is used, compared with the prior art, the ratio of the content of hydrogen to the content of silane in the amorphous silicon layer of the application is set to be greater than or equal to 8, so that the content of hydrogen bonds is increased, the content of Si-H bonds in the amorphous silicon layer is increased, the band gap is widened, the performance of the amorphous silicon layer is improved, the initial off-state current of the thin film transistor is reduced, and even if the off-state current of the thin film transistor is increased in a high-temperature state, the thin film transistor can still be in a low-current off state, so that the liquid crystal display is prevented from flickering or having a picture difference, and the display quality is improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a flowchart of the preparation method of the thin film transistor provided by Embodiment One of the application.

[0032] Figure 2 is Figure 1 a flow chart of one specific embodiment of step S107 in the method for manufacturing a thin film transistor;

[0033] Figure 3-1 is a device structure schematic diagram of the thin film transistor after step S101 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0034] Figure 3-2 is a device structure schematic diagram of the thin film transistor after step S102 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0035] Figure 3-3 is a device structure schematic diagram of the thin film transistor after step S103 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0036] Figure 3-4 is a device structure schematic diagram of the thin film transistor after step S104 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0037] Figure 3-5 is a device structure schematic diagram of the thin film transistor after step S105 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0038] Figure 3-6 is a device structure schematic diagram of the thin film transistor after step S106 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0039] Figure 3-7 is a device structure schematic diagram of the thin film transistor after step S107 of the method for manufacturing a thin film transistor provided by Embodiment One of the present application;

[0040] Figure 4 is Figure 3-7 a structure schematic diagram of the source, the drain, the first channel and the second channel after a passivation layer is formed on the surfaces thereof in the thin film transistor;

[0041] Figure 5 is a structure schematic diagram of the thin film transistor provided by Embodiment Two of the present application;

[0042] Figure 6 is a structure schematic diagram of the thin film transistor provided by Embodiment Three of the present application;

[0043] Figure 7 is a comparison diagram of the transfer characteristic curves of the thin film transistor of the present application and the thin film transistor in the prior art.

[0044] In the drawings, various reference numerals refer to:

[0045] 10, substrate; 20, gate; 30, gate insulating layer;

[0046] 40, amorphous silicon layer; 41, source region; 42, drain region; 43, first channel region; 44, second channel region; 401, first side surface; 402, second side surface;

[0047] 50, doped layer;

[0048] 60, source-drain metal layer; 61, source electrode; 62, drain electrode; 63, first channel; 64, second channel;

[0049] 70, passivation layer. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0051] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0052] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0053] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0054] It should also be noted that the same reference signs are used to represent the same components or the same parts in the embodiments of the present application. For the same parts in the embodiments of the present application, only one part or component may be labeled with a reference sign in the drawings, and it should be understood that the reference sign is also applicable to other identical parts or components.

[0055] The embodiment of the present application provides a thin film transistor and a preparation method thereof, and solves the problem that the off-state current of the TFT of the existing liquid crystal display is greatly increased at a high temperature, which causes the liquid crystal display to have a flashing screen or a picture difference, and affects display quality.

[0056] Embodiment one

[0057] Figure 1 is a flow chart of the preparation method of the thin film transistor provided by the embodiment one of the present application; referring to Figure 1 The preparation method of the thin film transistor provided by the embodiment one of the present application comprises the following steps:

[0058] S101, providing a substrate 10.

[0059] Figure 3-1 is a device structure schematic diagram after step S101 is completed. The substrate 10 can be prepared by using a material commonly used in the field, such as glass or plastic. In the embodiment, the side of the substrate 10 on which the device is prepared is taken as the upper side, and the opposite side is taken as the lower side.

[0060] S102, forming a gate 20 on the substrate 10.

[0061] Figure 3-2 is a device structure schematic diagram after step S102 is completed. The gate 20 can be prepared by using a physical vapor deposition (PVD) process. In the embodiment, the gate 20 can be prepared by using a magnetron sputtering process. Specifically, a whole layer structure is first deposited on the substrate 10, and then the layer structure is patterned, and finally the required gate 20 structure is prepared. The material of the gate 20 can be one or a combination of multiple conductive materials such as aluminum and copper.

[0062] S103, forming a gate insulating layer 30 on the substrate 10, so that the gate insulating layer 30 covers the gate 20.

[0063] Figure 3-3 is a device structure schematic diagram after step S103 is completed. The material of the gate insulating layer 30 can be silicon oxide or silicon nitride. The material of the gate insulating layer 30 can also be a combination of silicon oxide and silicon nitride. It can be understood that the gate insulating layer 30 can also be prepared by using other materials known to those skilled in the art. The gate insulating layer 30 can be formed by using a plasma enhanced chemical vapor deposition (PECVD) method.

[0064] S104, forming an amorphous silicon layer 40 on the gate insulating layer 30; wherein the ratio of hydrogen to silane is greater than or equal to 8.

[0065] Figure 3-4 The device structure schematic diagram after step S104 is shown in FIG. 4. Amorphous silicon (a-Si) is a form of elemental silicon. Amorphous silicon does not have a complete diamond cell, and its purity is not high, but its melting point, density and hardness are significantly lower than those of crystalline silicon. The amorphous silicon layer 40 (a-Si layer) as an active layer can also be formed by continuous deposition using a plasma enhanced chemical vapor deposition (PECVD) method.

[0066] During the deposition process, the ratio of hydrogen to silane is greater than or equal to 8, which can increase the content of hydrogen bonds, increase the content of Si-H bonds in the amorphous silicon layer 40, widen the band gap, and improve the performance of the amorphous silicon layer 40. The initial off-state current of the thin film transistor is reduced, so that even if the off-state current of the thin film transistor increases at high temperature, the thin film transistor can be kept in a low current off state, avoiding the occurrence of flashing or picture difference in the liquid crystal display, and improving the display quality.

[0067] S105, forming a doped layer 50 on the amorphous silicon layer 40.

[0068] Figure 3-5 The device structure schematic diagram after step S105 is shown in FIG. 5. The doped layer 50 is formed above the amorphous silicon layer 40, and the doped layer 50 can be an N+ type doped amorphous silicon layer. In this embodiment, the doped layer 50 is formed by continuous deposition using a plasma enhanced chemical vapor deposition (PECVD) method.

[0069] S106, forming a source-drain metal layer 60 on the doped layer 50.

[0070] Figure 3-6 The device structure schematic diagram after step S106 is shown in FIG. 6. The source-drain metal layer 60 can also be prepared by a physical vapor deposition (PVD) process. For example, the source-drain metal layer 60 can be prepared by a magnetron sputtering process. The source-drain metal layer 60 can be prepared from conductive materials such as aluminum, copper and molybdenum.

[0071] S107, etching the source-drain metal layer 60 and the doped layer 50 to obtain a source electrode 61 and a drain electrode 62.

[0072] Figure 3-7The device structure diagram after step S107 is completed. The thin film transistor includes an active region and a passive region, wherein the passive region surrounds the active region. The active region is used to set the source and drain of the thin film transistor and the like. In the etching process, the source and drain metal layer 60 above the passive region and the channel region of the thin film transistor need to be removed, and only the metal layer of the source and drain region is retained. At the same time, the semiconductor layer above the passive region of the thin film transistor also needs to be removed, that is, the doped layer 50 and the amorphous silicon layer 40 on the passive region are etched. In addition, the doped layer 50 above the channel region of the thin film transistor also needs to be completely etched.

[0073] The preparation method of the thin film transistor described above controls the ratio of hydrogen and silane to be greater than or equal to 8 when preparing the amorphous silicon layer 40, increases the content of hydrogen bonds, increases the content of Si-H bonds in the amorphous silicon layer 40, widens the band gap, and thus improves the performance of the amorphous silicon layer 40, reduces the initial off-state current of the thin film transistor, so that even if the off-state current of the thin film transistor increases in a high temperature state, the thin film transistor can be ensured to be in a low current off state, the probability of screen flashing or picture difference of the liquid crystal display in a high temperature state is reduced, and the display quality is improved.

[0074] In the related art, the ratio of hydrogen and silane when preparing the amorphous silicon layer 40 is less than 8, or nitrogen and silane are added for reaction, and the embodiment of the present application not only changes the reaction gas for preparing the amorphous silicon layer 40, but also controls the ratio of hydrogen and silane to be greater than or equal to 8, Figure 7 is a comparison diagram of the transfer characteristic curve of the thin film transistor of the embodiment of the present application and the thin film transistor in the prior art, and the No. 1 curve located above Figure 7 is the transfer characteristic curve of the thin film transistor in the prior art, and the No. 2 curve located below Figure 7 is the transfer characteristic curve of the thin film transistor of the embodiment of the present application. According to Figure 7 It can be clearly seen that the current Id at Vg=0V, that is, the initial off-state current, is small. When the off-state current rises by the same amplitude in a high temperature state, the initial off-state current of the embodiment of the present application is small, which means that the value of the off-state current after the off-state current increases in a high temperature state will also be small, and the phenomenon of excessive off-state current will not occur.

[0075] Further, referring to Figure 2 , step S107 includes the following steps:

[0076] S1071, forming a photoresist layer on the source and drain metal layer 60.

[0077] S1072, patterning the photoresist layer.

[0078] First, a whole layer of photoresist is deposited on the source-drain metal layer 60. Second, the substrate 10 coated with the photoresist layer is exposed and developed using a gray-tone mask or a half-tone mask to form a photoresist layer including a photoresist reserved area, a photoresist semi-reserved area and a photoresist removed area. The gray-tone mask includes a completely opaque area, a semi-transparent area and a completely transparent area, wherein the completely opaque area corresponds to the photoresist reserved area, i.e. the source 61 and the drain 62 area of the active region of the thin film transistor; the semi-transparent area corresponds to the photoresist semi-reserved area, i.e. the channel region of the thin film transistor; and the completely transparent area corresponds to the photoresist removed area, i.e. the passive region of the thin film transistor.

[0079] S1073, etching the source-drain metal layer 60 and the doped layer 50 according to the pattern of the photoresist layer to form the source 61, the drain 62 and the first channel 63 and the second channel 64 between the source 61 and the drain 62.

[0080] The source-drain metal layer 60 and the doped layer 50 are etched using the photoresist layer as a mask by wet etching and dry etching. The wet etching and the dry etching can be realized by using conventional processes.

[0081] First, the first wet etching is used to remove the source-drain metal layer 60 under the photoresist removed area, i.e. the passive region, while the source-drain metal layer 60 of the active region is reserved. The first wet etching process does not etch other layers such as the doped layer 50 under the source-drain metal layer 60. The specific etching process is a common technique in the art, which is not described here.

[0082] Second, the first dry etching is used to remove the doped layer 50 under the photoresist removed area, i.e. the passive region, while the doped layer 50 of the active region is reserved. The first dry etching process does not etch the amorphous silicon layer 40 under the doped layer 50. The specific etching process is a common technique in the art, which is not described here.

[0083] Third, the second wet etching is used to remove the residual photoresist layer and the source-drain metal layer 60 under the photoresist semi-reserved area, i.e. above the channel region, where the photoresist semi-reserved area has two, i.e. the channel region has two, which are the first channel region 43 and the second channel region 44, so that the source-drain metal layer 60 is reserved between the source 61, the drain 62 and the two channel regions. The second wet etching process does not etch other layers such as the doped layer 50 outside the source-drain metal layer 60. The specific etching process is a common technique in the art, which is not described here.

[0084] Next, a second dry etching process is used to remove the doped layer 50 of the two photoresist semi-retained regions. After the removal of the doped layer 50 above the first channel region 43 and the source / drain metal layer 60, the first channel 63 is formed. After the removal of the doped layer 50 above the second channel region 44 and the source / drain metal layer 60, the second channel 64 is formed.

[0085] According to steps S101 to S107 and steps S1071 to S1073 of the above-described method for fabricating thin-film transistors, a thin-film transistor can be fabricated. (Refer to...) Figure 3-7 The thin-film transistor fabricated by the method provided in Embodiment 1 of this application has two channels, and the length L1 of the first channel 63 and the length L2 of the second channel 64 are both greater than 3 micrometers.

[0086] It should be noted that the thin-film transistor fabrication method provided in Example 1 can fabricate a dual-channel thin-film transistor. The dual-channel design can increase the carrier transport distance and make the transport process more "wavering". Therefore, it can suppress the increase of the off-state current. By suppressing the increase of the off-state current on the basis of the initial decrease of the off-state current, the off-state current of the thin-film transistor at high temperature will not be too large. This ensures that the thin-film transistor can also be in a low-current off-state at high temperature, avoiding screen flickering or image distortion in the liquid crystal display and improving the display quality.

[0087] The length L1 of the first channel 63 and the length L2 of the second channel 64 are both set to be greater than 3 micrometers. In this way, the sum of the lengths of the first channel 63 and the second channel 64 will be greater than 6 micrometers. Increasing the channel length can effectively improve the stability of the thin film transistor, help suppress the rise of the off-state current, and improve the image retention problem.

[0088] Optional, see reference Figure 3-7 The orthographic projection of the first channel 63 on the substrate 10 and the orthographic projection of the second channel 64 on the substrate 10 are both located within the orthographic projection of the gate 20 on the substrate 10.

[0089] It should be noted that the material of the gate 20 can be one or a combination of conductive materials such as aluminum and copper. Therefore, the gate 20 has the function of shielding light. With the above configuration, the gate 20 can block light from shining on the areas of the amorphous silicon layer 40 corresponding to the first channel 63 and the second channel 64, respectively. Since the amorphous silicon layer 40 is highly sensitive to light and easily affected by light, the influence of light on the areas of the amorphous silicon layer 40 corresponding to the first channel 63 and the second channel 64 can be effectively reduced, which can at least improve the light stability of the thin film transistor.

[0090] Further reference Figure 3-7 The orthographic projection of the amorphous silicon layer 40 on the substrate 10 lies within the orthographic projection of the gate 20 on the substrate 10.

[0091] It should be noted that the preparation method of the thin film transistor of the embodiment of the present application increases the content of Si-H bond in the amorphous silicon layer 40 of the thin film transistor, but the Si-H bond is a weak bond and is unstable and easy to decompose under light. Therefore, the above setting can make the gate 20 completely block the light vertically irradiated onto the amorphous silicon layer 40, reduce the decomposition of the Si-H bond in the amorphous silicon layer 40 by light, and further improve the light stability of the thin film transistor, and further improve the stability of the thin film transistor in a high-temperature environment, so that the on-state current of the thin film transistor has a reduced rising amplitude in a high-temperature state and does not appear excessively large.

[0092] Optionally, referring to Figure 3-4 and Figure 3-6 , the amorphous silicon layer 40 has a first side surface 401 and a second side surface 402 in the length direction of the first channel 63; the source-drain metal layer 60 covers the first side surface 401 and the second side surface 402 and is connected with the gate insulating layer 30.

[0093] It should be noted that through the above setting, the source-drain metal layer 60 covers the first side surface 401 and the second side surface 402 of the amorphous silicon layer 40, and the orthographic projection of the amorphous silicon layer 40 on the substrate 10 is located in the orthographic projection of the gate 20 on the substrate 10, that is, the gate 20 helps the amorphous silicon layer 40 to block the light from below, and the source-drain metal layer 60 helps the amorphous silicon layer 40 to block the light from the horizontal direction, so as to avoid the side surface of the amorphous silicon layer 40 from being irradiated by light, thereby reducing the irradiation of light on the amorphous silicon layer 40 as a whole, ensuring the stability of the device characteristics of the thin film transistor, and reducing the rising amplitude of the on-state current of the thin film transistor in a high-temperature state and preventing the phenomenon of excessively large.

[0094] Further, the source-drain metal layer 60 is connected with the gate insulating layer 30, so as to ensure that the first side surface 401 and the second side surface 402 of the amorphous silicon layer 40 are completely surrounded by the source-drain metal layer 60, and the side surface of the amorphous silicon layer 40 is maximally prevented from being irradiated by light.

[0095] It can be understood that after the source 61, the drain 62, and the first channel 63 and the second channel 64 located between the source 61 and the drain 62 are formed in step S1073, a passivation layer 70 needs to be formed on the surface of the source 61, the drain 62, the first channel 63 and the second channel 64, and the passivation layer 70 is opened and electrodes are prepared, so as to finally obtain the thin film transistor.

[0096] Referring to Figure 4 , Figure 4is a schematic view of the structure after forming the passivation layer 70 on the surfaces of the source 61, the drain 62, the first channel 63 and the second channel 64; the passivation layer 70 can protect the source 61, the drain 62, the first channel 63 and the second channel 64 from being damaged, and the surface of the passivation layer 70 can be flat, which can facilitate the subsequent preparation of electrodes on the passivation layer 70.

[0097] Embodiment Two

[0098] With reference to Figure 5 , the embodiment two of the present application provides a thin film transistor prepared by the method of the foregoing embodiment. Specifically, the thin film transistor of the embodiment two of the present application comprises a substrate 10, a gate 20, a gate insulating layer 30, an amorphous silicon layer 40, a doped layer 50, and a source 61 and a drain 62; the gate 20 is located on the substrate 10; the gate insulating layer 30 is located on the substrate 10 and covers the gate 20; the amorphous silicon layer 40 is located on the gate insulating layer 30, and the ratio of the hydrogen content to the silane content in the amorphous silicon layer 40 is greater than or equal to 8; the doped layer 50 is located on the amorphous silicon layer 40; and the source 61 and the drain 62 are respectively located on the opposite ends of the doped layer 50.

[0099] The substrate 10 can be prepared from materials known in the art, such as glass or plastic. In the present embodiment, the side of the substrate 10 on which the device is prepared is referred to as the upper side, and the opposite side is referred to as the lower side. The material of the gate 20 can be one or a combination of more than one of conductive materials such as aluminum or copper. The material of the gate insulating layer 30 can be silicon nitride or silicon oxide, or a combination of silicon nitride and silicon oxide. It can be understood that the gate insulating layer 30 can also be prepared from other materials known to those skilled in the art.

[0100] In the present embodiment two, the ratio of the hydrogen content to the silane content in the amorphous silicon layer 40 is greater than or equal to 8, which can increase the content of hydrogen bonds in the amorphous silicon layer 40, increase the content of Si-H bonds in the amorphous silicon layer 40, widen the band gap, and thus improve the performance of the amorphous silicon layer 40, reduce the initial off-state current of the thin film transistor, increase the off-state current of the thin film transistor in a high-temperature state, and ensure that the thin film transistor is in a low-current off state, thereby avoiding the occurrence of flickering or image distortion in the liquid crystal display and improving the display quality.

[0101] Optionally, with reference to Figure 5 , the amorphous silicon layer 40 comprises a source region 41 corresponding to the source 61, a drain region 42 corresponding to the drain 62, and a first channel region 43 and a second channel region 44 located between the source region 41 and the drain region 42; when the thin film transistor is turned on, the first channel region 43 forms a first conductive channel, the second channel region 44 forms a second conductive channel, and the distance between the source region 41 and the drain region 42 is greater than the sum of the lengths of the first conductive channel and the second conductive channel.

[0102] In the conventional design, the amorphous silicon layer 40 is a channel region between the source region 41 corresponding to the source electrode 61 and the drain region 42 corresponding to the drain electrode 62, that is, the thin film transistor has only one channel, and when the thin film transistor is turned on, the entire channel region between the source electrode 61 and the drain electrode 62 forms a conductive channel. In the on and off states of the thin film transistor, the effective length of the channel region and the conductive channel is the same, that is, the extension length from the side close to the source electrode to the side close to the drain electrode, which cannot simultaneously optimize the on-state current and the off-state current. Because in order to optimize the characteristics of the thin film transistor, a large on-state current and a small off-state current are required, a large on-state current requires a conductive channel with a large width-length ratio in the on state, and a small off-state current requires a channel region with a small width-length ratio in the off state, which is a contradictory relationship.

[0103] The amorphous silicon layer 40 of the second embodiment of the present application has a first channel region 43 and a second channel region 44, and the first channel region 43 and the second channel region 44 are spaced apart. When the thin film transistor is turned on, the first channel region 43 forms a first conductive channel, and the second channel region 44 forms a second conductive channel, rather than the region between the source region 41 and the drain region 42 forming a conductive channel. The distance between the source region 41 and the drain region 42 is greater than the sum of the lengths of the first conductive channel and the second conductive channel, so that the width-length ratio of the region between the source region 41 and the drain region 42 is smaller than the width-length ratio of the conductive channel. The small width-length ratio of the region between the source region 41 and the drain region 42 can obtain a small off-state current, and the large width-length ratio of the conductive channel can obtain a large on-state current, which achieves the purpose of simultaneously optimizing the on-state current and the off-state current, and improves the performance of the thin film transistor.

[0104] It should be noted that the length of the first channel region 43 refers to the extension length of the first channel region 43 from the side close to the source electrode 61 to the side close to the drain electrode 62. The direction from the side close to the source electrode 61 to the side close to the drain electrode 62 of the first channel region 43 is defined as the first direction, and the width of the first channel region 43 refers to the extension direction of the first channel region 43 in the second direction, wherein the second direction is perpendicular to the first direction. The length of the conductive channel refers to the extension length of the conductive channel in the first direction, and the width of the conductive channel refers to the extension length of the conductive channel in the second direction. The length of the second channel region 44 refers to the extension length of the second channel region 44 in the first direction, and the width of the second channel region 44 refers to the extension length of the second channel region 44 in the second direction.

[0105] Further, the length L1 of the first channel region 43 and the length L2 of the second channel region 44 are both greater than 3 microns. Since the first channel region 43 corresponds to the first channel 63 and the second channel region 44 corresponds to the second channel 64, the sum of the lengths of the first channel 63 and the second channel 64 is equal to the sum of the lengths of the first channel region 43 and the second channel region 44, i.e. greater than 6 microns. Increasing the length of the channel can effectively improve the stability of the thin film transistor, and is conducive to inhibiting the rising amplitude of the off-state current and improving the image sticking problem.

[0106] Embodiment Three

[0107] Reference Figure 6 On the basis of the above-mentioned embodiment two, the amorphous silicon layer 40 has a first side surface 401 and a second side surface 402 in the length direction of the first channel region 43 in the embodiment three of the present application; the source electrode 61 covers the first side surface 401, the drain electrode 62 covers the second side surface 402, and the source electrode 61 and the drain electrode 62 are both connected with the gate insulating layer 30.

[0108] It should be noted that, through the above-mentioned setting, the source electrode 61 covers the first side surface 401 of the amorphous silicon layer 40, the drain electrode 62 covers the second side surface 402 of the amorphous silicon layer 40, and the source electrode 61 and the drain electrode 62 can help the amorphous silicon layer 40 block light coming from the horizontal direction, so as to avoid the side surface of the amorphous silicon layer 40 from being irradiated by light, thereby the irradiation of light on the amorphous silicon layer 40 can be reduced as a whole, the stability of the device characteristics of the thin film transistor is ensured, the rising amplitude of the off-state current of the thin film transistor under high temperature state is reduced, and the phenomenon of excessively large will not occur.

[0109] Further, the source electrode 61 and the drain electrode 62 are both connected with the gate insulating layer 30, so as to ensure that the first side surface 401 of the amorphous silicon layer 40 is completely surrounded by the source electrode 61, and the second side surface 402 of the amorphous silicon layer 40 is completely surrounded by the drain electrode 62, so as to maximize the guarantee that the side surface of the amorphous silicon layer 40 is not irradiated by light.

[0110] Optionally, in addition to the side of the amorphous silicon layer 40 not being irradiated by light, the orthographic projection of the amorphous silicon layer 40 on the substrate 10 can be located within the orthographic projection of the gate 20 on the substrate 10, i.e. the gate 20 helps the amorphous silicon layer 40 to block light from below. Since the Si-H bond is a weak bond, it is easy to decompose under light, and is unstable, therefore the gate 20 helps the amorphous silicon layer 40 to block light from below, and the source 61 and the drain 62 help the amorphous silicon layer 40 to block light from the horizontal direction, so that the amorphous silicon layer 40 is not irradiated by light in all directions, the influence of light irradiation on the amorphous silicon layer 40 is reduced, the stability of the device characteristics of the thin film transistor is ensured, the rise amplitude of the off-state current of the thin film transistor under high temperature is reduced, and the phenomenon of excessive rise is avoided, the thin film transistor can also maintain a low current off state under high temperature, and the liquid crystal display is prevented from appearing a flashing screen or a picture anomaly.

[0111] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a thin film transistor, characterized by comprising the steps of: The method comprises: ​ providing a substrate (10); forming a gate (20) on the substrate (10); forming a gate insulating layer (30) on the substrate (10), so that the gate insulating layer (30) covers the gate (20); forming an amorphous silicon layer (40) on the gate insulating layer (30); wherein the ratio of hydrogen to silane is greater than or equal to 8; forming a doped layer (50) on the amorphous silicon layer (40); forming a source-drain metal layer (60) on the doped layer (50); etching the source-drain metal layer (60) and the doped layer (50) to obtain a source (61), a drain (62), and a first channel (63) and a second channel (64) between the source (61) and the drain (62); the length of the first channel (63) and the length of the second channel (64) are both greater than 3 microns, and the orthographic projection of the first channel (63) on the substrate (10) and the orthographic projection of the second channel (64) on the substrate (10) are both located within the orthographic projection of the gate (20) on the substrate (10).

2. The method of claim 1, wherein, The etching the source-drain metal layer (60) and the doped layer (50) to obtain a source (61), a drain (62), and a first channel (63) and a second channel (64) between the source (61) and the drain (62) comprises: forming a photoresist layer on the source-drain metal layer (60); patterning the photoresist layer; etching the source-drain metal layer (60) and the doped layer (50) according to the pattern of the photoresist layer to form a source (61), a drain (62), and a first channel (63) and a second channel (64) between the source (61) and the drain (62).

3. The method of claim 2, wherein: the orthographic projection of the amorphous silicon layer (40) on the substrate (10) is located within the orthographic projection of the gate (20) on the substrate (10).

4. The method of claim 3, wherein: the amorphous silicon layer (40) has a first side (401) and a second side (402) in the length direction of the first channel (63); the source-drain metal layer (60) covers the first side (401) and the second side (402), and is connected with the gate insulating layer (30).

5. The method according to claim 3 or 4, characterized in that, After the etching the source-drain metal layer (60) and the doped layer (50) according to the pattern of the photoresist layer to form a source (61), a drain (62), and a first channel (63) and a second channel (64) between the source (61) and the drain (62), the method further comprises: forming a passivation layer (70) on the surface of the source (61), the drain (62), the first channel (63), and the second channel (64).

6. A thin film transistor, characterized by comprising: The method of any one of claims 1-5, comprising: a substrate (10); a gate (20) on the substrate (10); a gate insulating layer (30) located on the substrate (10) and covering the gate (20); an amorphous silicon layer (40) located on the gate insulating layer (30), a ratio of a hydrogen content to a silane content in the amorphous silicon layer being greater than or equal to 8; a doped layer (50) located on the amorphous silicon layer (40); a source (61) and a drain (62) located on opposite ends of the doped layer (50), respectively; the amorphous silicon layer (40) includes a source region (41) corresponding to the source (61), a drain region (42) corresponding to the drain (62), and a first channel region (43) and a second channel region (44) located between the source region (41) and the drain region (42), lengths of the first channel region (43) and the second channel region (44) are both greater than 3 microns; when the thin film transistor is turned on, the first channel region (43) forms a first conductive channel, the second channel region (44) forms a second conductive channel, and a distance between the source region (41) and the drain region (42) is greater than a sum of lengths of the first conductive channel and the second conductive channel.

Images