Semiconductor structure and method of forming the same

Abstract

Methods include providing a semiconductor structure including a fin projecting from a substrate, wherein the fin includes a plurality of first semiconductor layers and a plurality of second semiconductor layers; recessing the fin to form a source / drain recess; forming a source / drain structure in the source / drain recess; trimming the source / drain structure; depositing a dielectric layer to cover the source / drain structure; forming a contact hole in the dielectric layer to expose the source / drain structure; and forming a metal contact in the contact hole.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor structures, and more particularly to contact structures. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (such as the number of interconnects per unit chip area) typically increases as geometric dimensions (such as the smallest components or lines produced by the manufacturing process) shrink. Shrinking dimensions generally facilitates increased production capacity and reduced associated costs. However, shrinking dimensions also increases the complexity of handling and manufacturing integrated circuits. To achieve these advancements, the methods for handling and manufacturing integrated circuits must also evolve similarly.

[0003] In recent years, multi-gate transistors have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and mitigating short-channel effects. One such multi-gate transistor is the fin field-effect transistor (FET). The name fin FET comes from the fin-like structure extending from the substrate, which can be used to form the FET channel. Other multi-gate transistors, such as fully wound gate transistors (WWTs), can be used to address some setup-related performance challenges of fin FETs. The name of a fully wound gate transistor device comes from the fact that the gate structure extends completely around the channel region to contact the four sides of the channel. WWTs are compatible with existing complementary metal-oxide-semiconductor (CMOS) processes, and their structure maintains gate control and mitigates short-channel effects even with significant size reduction. Generally, WWTs are implemented when fin FETs cannot meet performance requirements. However, the fabrication methods for WWTs face challenges, and existing methods simultaneously address both fabrication and performance challenges. For example, when the separation between active device regions is reduced to meet the design requirements of smaller technology nodes, high parasitic capacitance can cause low device speeds (e.g., resistive-capacitive delays). While methods for reducing parasitic capacitance in integrated circuits generally achieve the intended purpose, they still cannot meet all the requirements. Summary of the Invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising providing a semiconductor structure including fins protruding from a substrate, wherein the fins include a plurality of first semiconductor layers and a plurality of second semiconductor layers interleaved in a vertical direction, and wherein the material composition of the first semiconductor layers is different from the material composition of the second semiconductor layers; recessing the fins to form source / drain recesses; forming source / drain structures in the source / drain recesses; trimming the source / drain structures; depositing a dielectric layer to cover the source / drain structures; forming contact holes in the dielectric layer to expose a portion of the source / drain structures; and depositing metal material in the contact holes to form metal contacts landing on the source / drain structures.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: interleaving a first semiconductor layer and a second semiconductor layer to form a semiconductor stack on a substrate, wherein the first semiconductor layer and the second semiconductor layer have different material compositions; patterning the semiconductor stack to form a fin; forming a dummy gate stack on the fin; forming a source / drain recess in the fin adjacent to the dummy gate stack; epitaxially depositing a source / drain structure in the source / drain recess; processing the top of the source / drain structure; removing the processed top of the source / drain structure to form a reshaped source / drain structure; depositing an interlayer dielectric layer on the reshaped source / drain structure; forming a contact hole in the interlayer dielectric layer to expose the reshaped source / drain structure; and forming a metal plug in the contact hole to contact the reshaped source / drain structure.

[0006] Another embodiment of the present invention provides a semiconductor structure comprising a semiconductor substrate; a fin comprising a stack of semiconductor layers and located on the semiconductor substrate; a source / drain structure adjacent to the fin; and a source / drain contact landing on the source / drain structure. The source / drain structure has an arcuate upper surface, wherein a first portion of the arcuate upper surface is higher than the upper surface of the fin, and wherein a second portion of the arcuate upper surface is lower than the upper surface of the fin. Attached Figure Description

[0007] Figure 1A , 1B 1C is a flowchart of a method for forming a semiconductor device containing an adjusted source / drain structure in one or more embodiments of the present invention.

[0008] Figure 2A This is a three-dimensional perspective view of a portion of a semiconductor device in one or more embodiments of the present invention.

[0009] Figure 2B This is one or more embodiments of the present invention. Figure 2A A top plan view of the semiconductor device shown.

[0010] Figure 3In one or more embodiments of the present invention, the semiconductor device is in Figure 1A , 1B A three-dimensional perspective view of the intermediate stage of the method shown in 1C.

[0011] Figure 4A , 5A 6A, 7A, 8A, 9A, 10A, 11A, 12A, 12C, 12D, 13, 14, 15, 16, 17, 18A, 19A, 20A, 20C, and 20D are examples of semiconductor devices in one or more embodiments of the present invention. Figure 1A , 1B And / or during the intermediate stages of the method shown in 1C, along Figure 2A And / or the sectional view of section line AA' shown in 2B.

[0012] Figure 4B , 5B 6B, 7B, 8B, 9B, 10B, 11B, 12B, 18B, 19B, and 20B are examples of semiconductor devices in one or more embodiments of the present invention. Figure 1A , 1B And / or during the intermediate stages of the method shown in 1C, along Figure 2A And / or the sectional view of section line BB' shown in 2B.

[0013] Explanation of reference numerals in the attached figures:

[0014] AA',BB': Section lines

[0015] h0, h1, h2, h3, h4, h5, h6: Height

[0016] I, II: Regions

[0017] w1, w2, w3: Width

[0018] 100: Method

[0019] 102,104,106,108,110,112,113a,113b,115,116,118,120,122: Steps

[0020] 114: Adjustment Steps

[0021] 114a, 114a': Surface treatment steps

[0022] 114b, 114b': Etching steps

[0023] 200: Device

[0024] 202: Substrate

[0025] 203: Trench

[0026] 204: Epitaxial Stacking

[0027] 206, 208: Epitaxial layer

[0028] 207: Gap

[0029] 210: Fin-like structures

[0030] 212,274: Hard mask (mask) layer

[0031] 214: Oxide layer

[0032] 216: Nitride layer

[0033] 220: Shallow trench isolation structure

[0034] 226: Dummy Gate Stack

[0035] 233,243: Partial

[0036] 234: Gate spacer

[0037] 237, 239: Source / Drain Layers

[0038] 238, 241: Source / Drain Structure

[0039] 240: Interlayer dielectric layer

[0040] 242: Contact Etching Stop Layer

[0041] 246: Source / Drain Recess

[0042] 252: Spacer layer

[0043] 270: Multi-layer masking unit

[0044] 272: Bottom anti-reflective coating

[0045] 277: Photosensitive layer

[0046] 280: Metal gate stack

[0047] 290: Source / Drain Contact

[0048] 602: Opening Detailed Implementation

[0049] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity.

[0050] The different embodiments or examples provided below can implement different structures of the present invention. The specific components and arrangements described below are intended to simplify the scope of the invention and not to limit it. For example, a description of a first component forming on a second component includes embodiments where the two are in direct contact, or embodiments where there are additional components spaced between them that are not in direct contact. Furthermore, spatial relative terms such as "below," "under," "lower," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustrations. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the illustrated direction.

[0051] Furthermore, when a numerical value or range is described using terms such as "about," "approximately," or similar expressions, it includes + / - 10% of the stated value unless otherwise specified. For example, the term "about 5 nm" encompasses a size range between 4.5 nm and 5.5 nm. Additionally, while the same reference numerals may be repeated in various embodiments of the invention for brevity, elements with the same reference numerals in different embodiments and / or configurations do not necessarily have the same correspondence.

[0052] This invention generally relates to semiconductor devices and their fabrication methods, and more particularly to field-effect transistors (FETs) such as three-dimensional fully wrapped gate field-effect transistors (which can also be considered as nanostructure FETs or nanosheet FETs) in memory cells and / or standard logic cells of integrated circuit structures. Generally, fully wrapped gate FETs comprise multiple vertically stacked sheets (such as nanosheets), wires (such as nanowires), or rods (such as nanorods) in the channel region of the FET, thereby achieving preferred gate control, lower leakage current, and improved size reduction capabilities required for various integrated circuit applications. Fully wrapped gate FETs are more attractive than single-gate devices because they offer greater control over short-channel effects and drive capability. However, in some cases, fully wrapped gate FETs may face problems such as parasitic capacitance in the dielectric components between active regions. While many design options can be used to reduce parasitic capacitance, they still cannot meet all requirements. Therefore, there is a need for improved methods of fabricating fully wrapped gate FETs that reduce parasitic capacitance. These embodiments relate to methods for adjusting the source / drain structure to reduce parasitic capacitance between the source / drain structure and adjacent components without compromising other design requirements such as resistance. The invention includes multiple embodiments. Different embodiments may have different advantages, and no single embodiment need to have a particular advantage. The following description uses one or more fully wound gate field-effect transistors as examples of multi-gate transistors to illustrate various embodiments of the invention. However, it should be understood that the embodiments of the invention are not limited to a specific type of device and can be used with other multi-gate transistors such as fin field-effect transistors.

[0053] Figure 1A ,1B Together with 1C, a flowchart of a method 100 for forming a semiconductor apparatus 200 is shown in various embodiments of the present invention. Method 100 is for illustrative purposes only and is not intended to limit the embodiments of the invention to the extent not actually described in the claims. Additional steps may be provided before, during, and after method 100, and additional embodiments of the method may substitute, omit, or interchange some of the stated steps. Method 100 will be used in conjunction with Figures 3 to 20D This is an explanation. Figure 2A , 2B Various cross-sectional views of the apparatus 200 shown in Figure 3 during an intermediate step of method 100. For example, Figure 4A , 5A 6A, 7A, 8A, 9A, 10A, 11A, 12A, 12C, 12D, 13, 14, 15, 16, 17, 18A, 19A, 20A, 20C, and 20D are devices 200 along... Figure 2A , 2B And / or the sectional view of section AA' shown in Figure 3 (which is along the length of the channel area), and Figure 4B , 5B 6B, 7B, 8B, 9B, 10B, 11B, 12B, 18B, 19B, and 20B are devices 200 along... Figure 2A , 2B And / or a cross-sectional view of the section BB' shown in Figure 3 (in the source / drain region perpendicular to the length direction of the channel region).

[0054] Device 200 may be an intermediate device or part thereof used in the manufacture of integrated circuits, and may include static random access memory and / or other logic circuitry, passive components such as resistors, capacitors, or inductors, and active components such as fully wound gate field-effect transistors, fin field-effect transistors, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other transistors. In these embodiments, device 200 may include one or more fully wound gate field-effect transistors. Embodiments of the present invention are not limited to any particular number of devices or device regions or any particular device arrangement. Additional structures may be added to device 200, and other embodiments of device 200 may replace, adjust, or omit some of the following structures.

[0055] like Figure 1A and 3As shown, step 102 of method 100 provides a semiconductor substrate 202. The substrate 202 may comprise semiconductor elements (single elements) such as silicon, germanium, and / or other suitable materials; semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; and semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, gallium arsenide phosphide, and / or other suitable materials. The substrate 202 may be a single-layer material with a uniform composition. In other embodiments, the substrate 202 may comprise multiple material layers having similar or different compositions suitable for manufacturing integrated circuit devices.

[0056] In some embodiments, substrate 202 includes field-effect transistors, and various doped regions, such as source / drain regions, are located within or on substrate 202. The doped regions may be doped with n-type dopants such as phosphorus or arsenic and / or p-type dopants such as boron or boron difluoride, depending on design requirements. The doped regions may be formed directly on substrate 202, within a p-type well structure, an n-type well structure, a dual-well structure, or in a raised structure. The formation methods for the doped regions may include implanting dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0057] like Figure 1A and 3 As shown, step 104 of method 100 forms an epitaxial stack 204, which includes interleaved epitaxial layers 208 and 206. Epitaxial layers 208 and 206 may each comprise a semiconductor material such as silicon, germanium, silicon carbide, silicon-germanium, germanium-tin, silicon-germanium-tin, silicon-germanium-silicon carbide, other suitable semiconductor materials, or combinations thereof, with the composition of epitaxial layer 206 differing from that of epitaxial layer 208. In this example, epitaxial layer 208 may contain silicon, and epitaxial layer 206 may contain germanium. In these embodiments, epitaxial layer 208 comprises silicon, and epitaxial layer 206 comprises silicon-germanium. In some examples, epitaxial stack 204 may comprise a total of two to ten pairs of interleaved epitaxial layers 208 and 206. Other configurations are also possible, depending on specific design requirements.

[0058] In some embodiments, the thickness of each epitaxial layer 206 may be from about 2 nm to about 6 nm, such as 3 nm in a specific example. Each epitaxial layer 206 may have a substantially uniform thickness. In some embodiments, the thickness of each epitaxial layer 208 may be from about 6 nm to about 12 nm, such as about 9 nm in a specific example. In some embodiments, the epitaxial layers 208 in the stack may each have a substantially uniform thickness. As detailed below, the epitaxial layer 208 may serve as a channel region for a subsequently formed multi-gate device, and the thickness of the epitaxial layer 208 is selected based on device performance considerations. Finally, the epitaxial layer 206 in the channel region may be removed to define the vertical distance between adjacent channel regions used by the subsequently formed multi-gate device, and the thickness of the epitaxial layer 206 is selected based on device performance considerations. In summary, the epitaxial layer 206 may also be considered as a non-channel layer (or sacrificial layer), and the epitaxial layer 208 may also be considered as a channel layer.

[0059] For example, the method for epitaxially growing the layered structure of epitaxial stack 204 may be molecular beam epitaxy, metal-organic chemical vapor deposition, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer (such as epitaxial layer 208) and the substrate 202 comprise the same material. In some embodiments, the grown epitaxial layers 206 and 208 comprise materials different from the material of the substrate 202. As described above, in at least some examples, epitaxial layer 206 comprises an epitaxially grown silicon-germanium layer, while epitaxial layer 208 comprises an epitaxially grown silicon layer. In some other embodiments, epitaxial layers 206 and 208 may each comprise other materials such as germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium phosphide indium, and / or gallium arsenide indium phosphide) or combinations thereof. As described above, the material selection for epitaxial layers 206 and 208 can provide different oxidation properties and etching selectivity. In some embodiments, epitaxial layers 206 and 208 are substantially undoped (e.g., the added dopant concentration is about 0 cm⁻¹). -3 To approximately 1x10 17 cm -3 For example, doping is not intentionally carried out during the epitaxial growth process.

[0060] like Figure 1A , 4AAs shown in Figure 4B, step 106 of method 100 employs a series of photolithography and etching processes to pattern the epitaxial stack 204 to form fin units such as fins 210. For example, the photolithography process may include forming a photomask layer on the epitaxial stack 204, exposing a photoresist layer to a pattern, performing a post-exposure baking process, and developing the exposed photoresist layer to form patterned mask units (not shown). The patterned mask units are then used as etching masks to etch the epitaxial stack 204 to retain the fins 210 protruding from the substrate 202 and spaced by trenches 203. The etching process may include dry etching, wet etching, reactive ion etching, other suitable processes, or combinations thereof. The patterned mask units can then be removed from the epitaxial stack 204, and the removal method may employ any suitable process such as ashing and / or photoresist stripping.

[0061] In some embodiments, the fin 210 may be fabricated using a dual-patterning or multi-patterning process. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or cores can then be used to etch the epitaxial stack 204 to form the fin 210.

[0062] In some embodiments, a hard mask layer 212 may be formed on the epitaxial stack 204 prior to patterning the fins 210. In some embodiments, the hard mask layer 212 comprises a nitride layer deposited by chemical vapor deposition and / or other suitable techniques. In some embodiments, the hard mask layer 212 comprises thermally grown oxide, oxide deposited by chemical vapor deposition, and / or oxide deposited by atomic layer deposition. In some embodiments, the hard mask layer 212 comprises an oxide layer 214 (such as a silicon oxide pad oxide layer) and a nitride layer 216 (such as a silicon nitride pad nitride layer) formed on the oxide layer 214. The oxide layer 214 may serve as an adhesion layer between the epitaxial stack 204 and the nitride layer 216, and may also serve as an etch stop layer for etching the nitride layer 216.

[0063] Various other embodiments of the method may also be employed to form fins on a substrate, including defining fin regions (e.g., defined by a mask or isolation region) and epitaxially growing an epitaxial stack 204 in the form of fin 210. In some embodiments, the method of forming fin 210 may include a trimming process to reduce the width of fin 210. The trimming process may include a wet etching process and / or a dry etching process.

[0064] like Figure 1A , 5AAs shown in Figure 5B, step 108 of method 100 forms a shallow trench isolation structure 220 between the fins 210. In some embodiments, a dielectric layer is first deposited on the substrate 202 to fill the trench 203. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials. In various examples, the dielectric layer deposition method may be a chemical vapor deposition process, a sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, and / or other suitable processes. In some embodiments, an annealing apparatus 200 may be used after the dielectric layer is deposited to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (with the subsequently formed shallow trench isolation structure 220) may comprise a multilayer structure, such as having one or more layers.

[0065] In some embodiments forming isolation structures such as shallow trench isolation structures, the deposited dielectric layer can be thinned and planarized by a chemical mechanical polishing (CMP) process after deposition. In some embodiments, the hard mask layer 212 can serve as a CMP stop layer. Figure 5B In the example shown, the shallow trench isolation structure 220 is sandwiched between fins 210 and can then be recessed to expose the fins 210. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and / or a combination thereof. The hard masking layer 212 may be removed before, during, and / or after recessing the shallow trench isolation structure 220. For example, the method for removing the hard masking layer 212 may be a wet etching process using phosphoric acid or other suitable etchant. In some embodiments, the hard masking layer 212 may be removed using the same etchant used to recess the shallow trench isolation structure 220. In some embodiments, the recess depth (e.g., controlling the etching time) may be controlled to adjust the height of the exposed fins 210. In the embodiment described, the height may be adjusted to expose all layers of the epitaxial stack 204.

[0066] like Figure 1A , 6AAs shown in Figure 6B, step 110 of method 100 forms one or more dummy gate stacks (or replacement gate stacks) 226 on fin 210. Each dummy gate stack 226 may include a dummy gate (not shown) located on a dummy gate dielectric layer and / or interface layer (not shown), whichever is formed as appropriate. The formation of the dummy gate stack 226 may be a series of deposition and patterning processes. For example, a polysilicon layer may be deposited on substrate 202, followed by patterning of the polysilicon layer by a series of photolithography and etching processes to form the dummy gate stack 226. To perform patterning processes and protect the dummy gate stack 226 in subsequent fabrication processes, a hard mask layer (not shown) may be formed on the dummy gate stack 226. In some embodiments, the dummy gate stack 226 may subsequently be replaced with a metal gate stack. The region of fins 210 below the dummy gate stack 226 can be considered as a channel region, while the region of fins 210 between the dummy gate stacks 226 can be considered as a source / drain region. A portion of the fins 210 in the source / drain region can then be recessed to form an opening, which is used to grow the source / drain structure thereon.

[0067] like Figure 6A and 6B As shown, method 100 then forms a gate spacer 234 on the dummy gate stack 226. A spacer material layer is compliantly deposited on the top and sidewalls of the dummy gate stack 226, followed by etching back the spacer material layer to form the gate spacer 234 (which can also be considered an outer spacer, as opposed to an inner spacer described later). The term "compliant" as used herein simply refers to layers having substantially the same thickness in different regions. The spacer material layer may comprise dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonoxynitride, silicon carbonitride, and / or combinations thereof. In some embodiments, the gate spacer 234 comprises multiple layers, such as primary spacer walls, liner layers, and the like. For example, the spacer material layer can be formed by depositing dielectric material on the dummy gate stack 226, and the process used can be chemical vapor deposition, sub-pressure chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, physical vapor deposition or other suitable processes.

[0068] Following method 100, an isotropic etching process can be performed to expose portions of the fins 210 adjacent to and not covered by the dummy gate stack 226 (such as portions in the source / drain regions). This isotropic etching process can completely remove portions of the spacer material layer directly located on the dummy gate stack 226. Portions of the spacer material layer on the sidewalls of the dummy gate stack 226 can be retained to form gate spacers (or outer spacers) 234. In the described embodiment, the distance between two gate spacers 234 on adjacent dummy gate stacks 226 is width w1.

[0069] like Figure 7A and 7B As shown, method 100 forms a source / drain recess 246 in the fin 210 adjacent to the dummy gate stack 226. In some embodiments, method 100 performs an etching process that selectively removes portions of the fin 210 in the source / drain region without removing or substantially not removing the dummy gate stack 226 and the gate spacer 234. Thus, width w1 can be transferred to the source / drain recess 246, as... Figure 7A As shown. In Figure 7A In the illustrated embodiment, the sidewalls of epitaxial layers 206 and 208 and the upper surface of the substrate 202 are exposed in the source / drain recess 246. In some embodiments, the retained bottom of the fin 210 does not contain the epitaxial stack 204 and has an arcuate upper surface, such as... Figure 7B As shown. In some embodiments, the etching process is a dry etching process or a wet etching process, which uses a suitable etchant to remove the silicon (e.g., epitaxial layer 208) and silicon-germanium (e.g., epitaxial layer 206) of the epitaxial stack 204. In some non-limiting examples, the dry etchant may be a chlorine-containing etchant such as chlorine gas, silicon tetrachloride, boron trichloride, other chlorine-containing gases, or combinations thereof. A cleaning process may then be performed using hydrofluoric acid solution or other suitable solutions to clean the source / drain recesses.

[0070] like Figure 7A and 7B As shown, method 100 can selectively remove portions of epitaxial layer 206 by a suitable etching process to form gaps 207 between epitaxial layers 208, thereby suspending portions of epitaxial layer 208. As described above, epitaxial layer 208 comprises silicon and epitaxial layer 206 comprises silicon-germanium. In summary, the etching process can selectively remove portions of silicon-germanium without removing or substantially removing silicon. In some embodiments, the etching process is an isotropic etching process (such as a dry etching process or a wet etching process), and the etching time can control the amount of epitaxial layer 206 removed. In one embodiment, method 100 can selectively remove portions of epitaxial layer 206, and the removal method can be a wet etching process using hydrofluoric acid and / or ammonium hydroxide as etchants, which can first oxidize portions of epitaxial layer 206 to form silicon-germanium oxide, and then remove the silicon-germanium oxide.

[0071] like Figure 8A and 8B As shown, method 100 deposits a spacer layer 252 on device 200. In many embodiments, the spacer layer 252 is compliantly formed on device 200 to cover the dummy gate stack 226, gate spacer 234, and fins 210 (including epitaxial layers 206 and 208). Figure 8AAs shown, spacer layer 252 can fill the gaps 207 between epitaxial layers 208. In some embodiments, the spacer layer 252 can be deposited by any suitable method such as atomic layer deposition to achieve any suitable thickness. In some examples, spacer layer 252 can contain any suitable dielectric material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon carbide, other suitable dielectric materials, or combinations thereof.

[0072] Then as Figure 9A and 9B As shown, method 100 removes a portion of the spacer layer 252 during an etching process, leaving only a portion of the spacer layer 252 on the sidewall of the epitaxial layer 206. The retained portion of the spacer layer 252 can then be considered as an inner spacer. Inner spacers such as the spacer layer 252 can be provided to facilitate subsequent fabrication steps for forming multi-gate devices. In some examples, inner spacers such as the spacer layer 252 are provided to isolate the subsequently formed source / drain structure from the metal gate stack. In some embodiments, the etching process is an isotropic etching process, and the amount of spacer layer 252 removed can be controlled by the etching process time. In some examples, the thickness of the spacer layer 252 removed by the etching process can be from about 3 nm to about 7 nm. The embodiments of the present invention are, of course, not limited to this size range.

[0073] like Figure 1A , 10A As shown in Figure 10B, step 112 of method 100 forms a source / drain structure 238 in a source / drain recess 246. The source / drain structure 238 may include multiple epitaxial semiconductor layers, such as source / drain layers 237 and 239. The source / drain layer 237 may be selectively grown from the semiconductor surface exposed in the source / drain recess 246. In these embodiments, the source / drain layer 237 is formed on the sidewalls of the epitaxial layer 208 and the upper surface of the substrate 202 exposed in the source / drain recess 246 (e.g., ...). Figure 10AAbove the epitaxial layer 208 (as shown), a portion of the source / drain recess 246 is filled. A portion of the source / drain layer 237, growing from the sidewall of the bottom epitaxial layer 208, may merge with another portion of the source / drain layer 237, growing from the upper surface of the substrate 202, to fill the bottom gap 207 and leave the remaining gap 207 (without the source / drain layer 237). In some embodiments, the inner spacers such as spacer layers 252 in each gap 207 contact the source / drain layer 237. In these embodiments, a portion of the source / drain layer 237 is above the upper surface of the top epitaxial layer 208 (hereinafter referred to as the fin top). In other words, the fin top is between the top surface of the source / drain layer 237 and the substrate 202. In these embodiments, the source / drain layer 237, growing from the top epitaxial layer 208, may contact the gate spacer 234, but the embodiments of the invention are of course not limited to this arrangement. In some embodiments, the source / drain layer 237 is substantially undoped or has a doping concentration less than that of the subsequently formed source / drain layer 239, in order to improve the substrate leakage current performance, as detailed below.

[0074] like Figure 11A and 11B As shown, method 100 forms a source / drain layer 239 on the source / drain layer 237 to fill the remaining gap 207 and the remainder of the source / drain recess 246. In this embodiment, the top of the source / drain layer 239 extends above the top of the fin and lies between the gate spacers 234. The source / drain layer 239 contacts the gate spacers 234 and shares a common edge defined by a height h0. In other words, the top of the source / drain layer 239 laterally extends across the gap between the two gate spacers 234. The source / drain structure 238 is configured in this way to accommodate subsequent source / drain structure adjustment steps. These configurations are, of course, merely illustrative and not limiting to the embodiments of the invention. For example, the source / drain layer 239 may not contact the gate spacers 234. In these embodiments, the source / drain layer 239 covers the previously formed source / drain layer 237, so that the source / drain layer 237 is not exposed in the gaps between the gate spacers. However, the embodiments of the present invention are not limited to this arrangement. For example, the source / drain layer 239 may not completely cover the source / drain layer 237, so that a portion of the source / drain layer 237 is exposed in the gaps between the gate spacers. Figure 11AIn the illustrated embodiment, the top of the source / drain structure above the fin is an inverted U-shape (or valley shape), comprising a portion of the source / drain layer 237 and a portion of the source / drain layer 239. In some embodiments, the top of the source / drain structure is defined by width w1 and height h1. In these embodiments, the height h1 (measured along the z-direction from the top of the fin) may be from about 5 nm to about 15 nm, while the width w1 may be from about 12 nm to about 25 nm.

[0075] The source / drain structure 238 (including source / drain layers 237 and 239) can be formed by any suitable method, such as molecular beam epitaxy, chemical vapor deposition (e.g., vapor phase epitaxy, metal-organic chemical vapor deposition, and / or ultra-high vacuum chemical vapor deposition), other suitable epitaxial growth processes, or combinations thereof. The epitaxial growth process may employ gas-phase and / or liquid-phase precursors, which can interact with the composition of the substrate 202. In some embodiments, adjacent source / drain structures 238 grown on adjacent fins 210 may be separated from each other, such as... Figure 11B As shown. In other embodiments, adjacent source / drain structures 238 may be combined together (not shown). The source / drain structure 238 may comprise germanium, silicon, gallium arsenide, aluminum gallium arsenide, silicon germanium, gallium arsenide phosphide, silicon phosphide, or other suitable materials. During epitaxial processing, dopant species (such as p-type dopants like boron or boron difluoride, n-type dopants like phosphorus or arsenic, and / or other suitable dopant combinations thereof) may be introduced to dope the source / drain structure 238 in situ. If the source / drain structure 238 is not doped in situ, a planting process (such as a junction planting process) may be performed to dope the source / drain structure 238.

[0076] In some embodiments, the source / drain layer 239 differs from the source / drain layer 237 in the doping concentration. In some examples, the source / drain layer 239 contains a higher doping concentration than the source / drain layer 237. In some embodiments, the source / drain layer 237 comprises silicon germanium, and the germanium concentration is from about 10% to about 20%. The source / drain layer 239 comprises silicon germanium, and the germanium concentration is from about 40% to about 60%. In these embodiments, the source / drain layer 237 and / or the source / drain layer 239 comprises boron. In some examples, the boron concentration in the source / drain layer 237 is about 1.7 x 10⁻⁶. -20 To approximately 3.7x10 -20 In some examples, the boron concentration in the source / drain layer 239 is approximately 3 x 10⁻⁶. -21 Approximately 7x10 -21 In some embodiments, the source / drain layer 237 comprises silicon boride, and the boron concentration is approximately 1.7 x 10⁻⁶. -20 To approximately 3.7x10 -20In some examples, the source / drain layer 239 has a gradient dopant concentration, wherein the dopant concentration gradually increases from the bottom to the top of the source / drain layer 239, but the embodiments of the present invention are not limited to this configuration. Furthermore, silicides or germanium silicides can be formed on the source / drain structure 238. For example, a metal layer can be deposited on the source / drain structure 238, followed by annealing the metal layer to react with the silicon in the source / drain structure to form a metal silicide such as a nickel silicide. Unreacted metal layers can be removed after annealing.

[0077] Generally, subsequent processes forming the source / drain contacts may alter the morphology of the source / drain structure (e.g., the top of the source / drain structure above the fin), which can be considered a landing effect. For example, the top of the source / drain structure may press downwards toward the substrate and / or outwards toward the adjacent gate spacer. In cases where the height h1 is too large, the source / drain structure during landing may laterally compress the adjacent spacer, thereby increasing the height h0 and the contact area between the source / drain structure and the gate spacer. This increased contact area further increases the parasitic capacitance between the source / drain structure and the gate spacer, resulting in resistive-capacitive delay and low device processing speed. On the other hand, in cases where the source / drain structure is too low (e.g., the height h1 is too small or the source / drain structure is lower than the top of the fin), the subsequent formation of the source / drain contact will press the source / drain structure even lower (e.g., lower than the top of the fin), creating a gap between the epitaxial layers 208 on both sides of the source / drain structure. This gap can block the current path, thus increasing the resistance of the device 200.

[0078] This invention relates to a method for adjusting the source / drain structure to reduce parasitic capacitance without compromising other design requirements such as device resistance. Specifically, the top morphology of the source / drain structure can be adjusted to accommodate the subsequent formation of source / drain contacts on the source / drain structure, thereby reducing parasitic capacitance without causing unintentional damage to the device 200 (such as increased resistance).

[0079] like Figure 1A , 1B As shown in 12A and 12B, the adjustment step 114 of method 100 then adjusts (or trims, reshapes) the morphology of the source / drain structure 238. The adjustment step 114 includes a surface treatment step 114a (or 114a') and a subsequent etching step 114b (or 114b') to remove the treated surfaces of the source / drain structure 238, such as... Figure 1BAs shown. Surface treatment step 114a (or 114a') chemically alters the characteristics of the upper surface of the source / drain structure without altering or substantially altering adjacent components (such as gate spacer 234 and dummy gate stack 226). Compared to the untreated upper surface, the treated upper surface exhibits higher etch selectivity relative to nearby components in subsequent etching processes. In some examples, the selectivity of the treated upper surface is approximately 100 times higher than that of the untreated upper surface. The treated surface may be retained as a surface portion of the source / drain structure 238. Afterwards, adjustment step 114 may be followed by etching step 114b (or 114b') to selectively remove the treated upper surface of the source / drain structure, thereby physically altering the morphology of the source / drain structure 238, such as reducing the height h1 and / or width w1 of the top of the source / drain structure 238. During the etching process, the unprocessed portion beneath the processed surface of the source / drain structure and adjacent components (such as gate spacer 234 and dummy gate stack 226) can remain intact or substantially intact.

[0080] like Figure 1B In the embodiments shown, the surface treatment step 114a (or 114a') in adjustment step 114 is a plasma treatment (such as a decoupled plasma treatment), which may employ an environment of ammonia, nitrogen, helium, and / or oxygen. In some examples, the surface treatment step 114a included in adjustment step 114 employs an oxygen environment. Therefore, surface treatment step 114a can be considered as surface oxidation. During plasma treatment, oxygen radicals can react with the upper surface composition (such as silicon) of the source / drain structure 238 to produce individual oxides (such as silicon oxide), thereby forming the treated surface. In other examples, adjustment step 114 includes a surface treatment step 114a' employing a nitrogen environment. Therefore, surface treatment step 114a' can be considered as surface nitriding. During plasma treatment, nitrogen radicals can react with the composition such as silicon to produce individual nitrides such as silicon nitride, thereby forming the treated surface. However, these steps are of course only illustrative and not limited to the embodiments of the present invention. In some embodiments, the power of the decoupled plasma treatment may be from about 500 watts to 2000 watts. In some embodiments, the operating temperature of the decoupled plasma system may be from about 200°C to about 400°C.

[0081] like Figure 1BAs shown, the etching step 114b (or 114b') in adjustment step 114 may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. In some examples, the dry etching process may be carried out using oxygen-containing gases, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or bromoform), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. In other examples, the wet etching process may include etching in dilute hydrofluoric acid, potassium hydroxide solution, ammonia, solutions containing hydrofluoric acid, nitric acid, and / or acetic acid, or other suitable wet etchants.

[0082] In a specific example, the treated surface after oxidation may include silicon oxide (as in surface treatment step 114a), while the subsequent etching step (as in etching step 114b) may apply an etchant gas containing hydrofluoric acid and ammonia at a temperature of 45°C. The low temperature maintains the high etch selectivity of the etchant for nitrides. The chemical reaction of the etching is as follows:

[0083] 10HF + 2SiO2 + 2NH3 → SiF4↑ + 4H2O↑ + (NH4)2SiF6

[0084] Byproducts such as ammonium hexafluorosilicate can remain in a solid state. After an etching step (such as etching step 114b), the temperature can be increased to decompose the byproducts, for example, by raising the temperature to approximately 80°C. The chemical reaction for decomposition is as follows:

[0085] (NH4)2SiF6→ SiF4↑ + 2NH3↑ + 2HF↑

[0086] After removing the byproducts, the untreated portion of the source / drain structure 238 beneath the treated surface can be exposed. The upper surface of the source / drain structure 238 can be adjusted (or reshaped) by removing the surface portion through an etching step (such as etching step 114b).

[0087] In other examples, the surface treated after nitriding (such as surface treatment step 114a') comprises silicon nitride, and subsequent etching steps (such as etching step 114b') can be performed by applying an etchant gas containing hydrofluoric acid and ammonia at a temperature of 45°C. The low temperature maintains the high etch selectivity of the etchant for oxides. The chemical reaction of the etching is as follows:

[0088] 16HF + NH3+ Si3N4 → NH3↑ + SiF4↑ + (NH4)2SiF6

[0089] Byproducts such as ammonium hexafluorosilicate can remain in a solid state. After an etching step (such as etching step 114b'), the temperature can be increased to decompose the byproducts, for example, by raising the temperature to approximately 80°C. The chemical reaction for decomposition is as follows:

[0090] (NH4)2SiF6→ SiF4↑ + 2NH3↑ + 2HF↑

[0091] After removing byproducts, the untreated portion of the source / drain structure 238 beneath the treated surface can be exposed. The upper surface of the source / drain structure 238 can be adjusted (or reshaped) by removing the surface portion through an etching step (such as etching step 114b').

[0092] like Figure 1B In the embodiments shown, adjustment step 114 includes one or more repeated surface treatment steps (such as surface treatment steps 114a or 114a') followed by etching steps (such as etching steps 114b or 114b'). The number of repetitions depends on a predetermined value for the height of the source / drain structure 238. To precisely control the morphology of the source / drain structure, each repetition may use milder conditions than the previous repetition to avoid unintentionally over-etching the source / drain structure. The initial repetitions are stronger to accelerate the process time of adjustment step 114. Subsequent repetitions are weaker to avoid over-etching the source / drain structure when the desired morphology is achieved. For example, the surface treatment depth in each surface treatment step 114a (or 114a') is less than the surface treatment depth in the previous surface treatment step 114a (or 114a'). In summary, the surface depth removed by each etching step 114b (or 114b') is less than the surface depth removed by the previous etching step 114b (or 114b'). In some embodiments, the surface depth can be controlled by the etchant's time, flow rate, temperature, concentration, and / or flow rate. In these embodiments, each repeated surface treatment and subsequent etching process can remove a thickness of approximately 1 nm to approximately 3 nm.

[0093] like Figure 12A , 12C As shown in 12D, the surface treatment step 114a (or 114a') and the etching step 114b (or 114b') are repeated twice in the adjustment step 114 of the source / drain structure 238, as indicated by the dashed lines. In some embodiments, the first repetition may include the surface treatment step 114a and the etching step 114b, while the second repetition may include the surface treatment step 114a' and the etching step 114b', so that each repetition achieves a different adjustment level. Figure 12A An enlarged view of part 233 of the device 200 shown is as follows: Figure 12C and 12DAs shown, this illustrates the adjustment step 114 of the source / drain structure 238 and its various components. The first removable region I (between the two dashed lines) is repeated, reducing the height h1 to height h2 while maintaining the same width w1 for the source / drain structure. The second removable region II (between the lower dashed line and the upper surface of the adjusted source / drain structure 238) is repeated, where adjustment step 114 reduces not only the height h2 to height h3 but also the width w1 to width w2. As... Figure 12D In other embodiments shown, the second repetition only reduces the height h2 to the height h3, while the width w2 remains the same as the width w1. In other words, adjustment step 114 (including the first and second repetitions) does not reduce the width w1 of the source / drain structure.

[0094] It is worth noting that the second surface treatment step 114a (or 114a') in the second repetition is milder than the first surface treatment step 114a (or 114a') in the first repetition. For example, the second surface treatment 114a (or 114a') has lower power, shorter time, or lower temperature than the first surface treatment 114a (or 114a'). Similarly, the second etching step 114b (or 114b') in the second repetition is weaker than the first etching step 114b (or 114b') in the first repetition. For example, the second etching step 114b (or 114b') uses a lower concentration and / or lower flow rate of etchant, a shorter time, and / or a lower temperature than the first etching step 114b (or 114b'). As a result, the height reduction in the second repetition is less than the height reduction in the first repetition, thereby avoiding over-etching of the source / drain structure during the second repetition. The two regions I and II, and the corresponding two repeated surface treatment and etching processes, are used for illustrative purposes and not to limit the embodiments of the invention to any number of repetitions of step 114. For example, the number of repetitions can be 1 to 10.

[0095] like Figure 12C and 12D As shown, adjusting the source / drain structure 238 can remove a portion of the source / drain layer 239 and / or a portion of the source / drain layer 237. For example... Figure 12C As shown, the source / drain layer 237 may be exposed again in the gap between the gate spacers, but the embodiments of the present invention are of course not limited to this arrangement. For example, the source / drain layer 239 after adjusting the source / drain structure 238 can still cover the source / drain layer 237, such as... Figure 12DAs shown. In these embodiments, the top of the adjusted source / drain structure 238 between the gate spacers 234 is inverted V-shaped (or horn-shaped), and its height h3 is less than the height h1 of the U-shaped top of the original source / drain structure. In some examples, the height h3 is about 30% to about 50% of the height h1. In some examples, the height h3 is equal to or less than about 10 nm. Figure 12C In the illustrated embodiment, the adjusted source / drain structure does not contact the gate spacer 234. Figure 12D In other embodiments shown, the adjusted source / drain structures (such as source / drain layers 237 and / or source / drain layers 239) can still contact the gate spacer 234. The height h6 of the common surface (or common edge) between the adjusted source / drain structure 238 and the gate spacer 234 is less than the original height h0. In these embodiments, the width w2 of the top of the adjusted source / drain structure above the fin is equal to or less than the width w1, depending on the endpoint of adjustment step 114. In some examples, the width w2 is equal to or greater than 50% of the width w1. In some examples, the width w2 is equal to the width w1. In some examples, the width w2 is about 14 nm to about 21 nm. The aforementioned ratios h3 / h1 and w2 / w1 help to mitigate the aforementioned landing effect. For example, if the ratios are less than a given range, the source / drain structure 238 may be over-etched, thereby increasing the resistance of the current path. On the other hand, if the ratio is greater than a given range, the source / drain structure 238 may be under-etched, resulting in an increase in parasitic capacitance between the source / drain junction and the gate stack.

[0096] Method 100 can complete the task. Figure 1B The adjustment step 114 shown is performed. Figure 1A Subsequent steps, such as step 116, are performed to form the interlayer dielectric layer 240. In other embodiments, method 100 may include other embodiments that modify step 114, such as those combined with... Figure 1C and Figures 13 to 17 The details are described below. Other embodiments of adjusting step 114 may selectively adjust specific source / drain structures (such as narrower and taller source / drain structures) with respect to the patterning process, while the remaining source / drain structures (such as wider and shorter source / drain structures) remain intact.

[0097] like Figure 1A , 1C13. Before adjusting step 114, step 112 of method 100 may form source / drain structures 238 and 241 with uneven upper surfaces. The unevenness of the upper surfaces of source / drain structures 238 and 241 may originate from different source / drain recess widths (or gate spacing), resulting in a greater vertical growth rate and a higher upper surface for the source / drain structure in the narrower source / drain recess (such as source / drain structure 238). The top of source / drain structure 238, which is above the top of the fin, has a height h1 and a width w1. The top of source / drain structure 241, which is above the top of the fin, has a height h4 and a width w3, wherein the height h1 is greater than the height h4 and the width w1 is less than the width w3. In some embodiments, the width w3 is from about 18 nm to about 25 nm. If the same adjustment step 114 of source / drain structure 238 is performed on source / drain structure 241, the height of source / drain structure 241 is reduced and the landing effect is degraded (e.g., by increasing resistance). In this example, a shield is applied to source / drain structure 241 to protect it from adjustment, while in adjustment step 114, source / drain structure 238 can be adjusted to reduce parasitic capacitance and accommodate the landing effect.

[0098] like Figure 1C and 14 As shown, step 113a of adjusting step 114 can form a multilayer masking unit 270 on the device 200. In some embodiments, the multilayer masking unit 270 is a three-layer masking unit, which may include a base antireflective coating 272, a hard masking layer 274 on the base antireflective coating 272, and a photosensitive layer 277 on the hard masking layer 274. In some embodiments, the base antireflective coating 272 is a carbon-containing organic material, including benzene and / or hydroxyl groups. In some embodiments, the hard masking layer 274 may be a single-layer structure, or a multilayer structure each containing different compositions. In some embodiments, the hard masking layer 274 may be a polymer layer, which may be formed by spin-coating a solution containing a suitable polymer dissolved in a solvent to form the hard masking layer 274 on the base antireflective coating 272. In some embodiments, the photosensitive layer 277 includes a photosensitive material that undergoes a property change upon exposure to light such as ultraviolet light, deep ultraviolet light, and / or extreme ultraviolet light.

[0099] like Figure 1C and 15As shown, step 113b of adjustment step 114 involves patterning the multilayer mask unit 270 to expose the source / drain structure 238 in the opening 602. In some embodiments, the patterning process includes exposing the photosensitive layer 277 with a photomask, performing a post-exposure baking process, developing the exposed photosensitive layer 277, and then using the patterned photosensitive layer 277 as an etching mask to etch the hard mask layer 274 and the bottom anti-reflective coating 272. The patterned multilayer mask unit 270 is then used as a mask for subsequent adjustment processes of the source / drain structure 238.

[0100] like Figure 1C and 16 As shown, the surface treatment step 114a and etching step 114b, which are adjusted step 114, are performed (as shown in the figure). Figure 1B (As detailed above), to selectively adjust the morphology of the source / drain structure 238 exposed in the opening 602, while the multilayer masking unit 270 covers the source / drain structure 241 and other nearby components (such as the dummy gate stack 226 and the gate spacer 234) to maintain its integrity. Figure 1C As shown, one or more surface treatment steps 114a and etching steps 114b can be performed as needed to obtain the desired morphology. In each embodiment, surface treatment step 114a and etching step 114b can be replaced by surface treatment step 114a' and etching step 114b', respectively.

[0101] like Figure 1C and 17 As shown, after adjusting the source / drain structure 238 in step 114, step 115 can remove the patterned multilayer masking unit 270. Removing the multilayer masking unit 270 exposes the source / drain structure 241 and / or other nearby components (such as the dummy gate stack 226 and gate spacers 234). Removing the patterned multilayer masking unit 270 can be performed using photoresist stripping, plasma ashing, and / or other suitable processes. Adjusting step 114 can reduce the height of the source / drain structure 238. In this embodiment, the recessed upper surface of the source / drain structure 238 is still higher than the upper surface of the adjacent source / drain structure 241, but this effectively mitigates the landing effect. In various other embodiments, the recessed upper surface of the source / drain structure 238 may be flush with or lower than the upper surface of the adjacent source / drain structure 241. Furthermore, in the aforementioned embodiment, after adjustment step 114, the source / drain layer 237 of the source / drain structure 238 is exposed, so that the source / drain layer 239 of the source / drain structure 238 does not contact the gate spacer 234, while the source / drain layer 239 of the source / drain structure 241 still covers the source / drain layer 237 of the source / drain structure 241, thus maintaining contact between the source / drain layer 239 and the gate spacer 234. In other embodiments, the source / drain layer 239 does not contact the gate spacer 234. Figure 1B The adjustment step 114 is similar. Figure 1C The other adjustment step 114 can be performed after the patterned multilayer masking unit 270 is removed. Figure 1A The subsequent steps shown, such as forming an interlayer dielectric layer, are related to step 116.

[0102] like Figure 1A , 18A As shown in 18B, step 116 of method 100 then forms an interlayer dielectric layer 240 on the substrate. In some embodiments, a contact etch stop layer 242 may also be formed prior to the formation of the interlayer dielectric layer 240. In some examples, the contact etch stop layer includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The contact etch stop layer 242 may be formed by a plasma-assisted chemical vapor deposition process and / or other suitable deposition or oxidation processes. In some embodiments, the interlayer dielectric layer 240 may comprise an oxide of tetraethoxysilane, undoped silicate glass, or doped silicon oxide (such as borosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, and / or other suitable dielectric materials). The interlayer dielectric layer 240 may be deposited by a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 240, the semiconductor device 200 may undergo a high thermal budget process to anneal the interlayer dielectric layer.

[0103] In some examples, a planarization process may be performed after depositing the interlayer dielectric layer to remove excess dielectric material. For example, the planarization process may include a chemical mechanical polishing (CMP) process that removes the interlayer dielectric layer 240 (and the contact etch stop layer, if present) on the dummy gate stack 226 and planarizes the upper surface of the semiconductor device 200. In some embodiments, the CMP process may expose the gate layer of the dummy gate stack 226.

[0104] like Figure 19A and 19B As shown, step 118 of method 100 replaces the dummy gate stack 226 and epitaxial layer 206 with a metal gate stack 280. The method of replacing the metal gate stack 280 may include removing the dummy gate stack 226 from device 200 to form a gate trench (not shown). Using a wafer forming process or a wafer release process, the epitaxial layer 206 is removed from the epitaxial stack to form an opening between the epitaxial layers 208. A metal gate stack is formed in the gate trench and the opening, such that the metal gate stack 280 covers each epitaxial layer 208 (or is interleaved with each epitaxial layer 208).

[0105] In the described embodiment, the metal gate stack 280 includes a gate dielectric layer (not shown) and a metal gate (not shown) located on the gate dielectric layer. The gate dielectric layer may comprise a dielectric material with a high dielectric constant, such as hafnium oxide, lanthanum oxide, other suitable materials, or combinations thereof. The metal gate may comprise at least one work function metal layer and a substrate conductive layer located thereon. The work function metal layer may be a p-type or n-type work function metal layer. Examples of work function metals may include titanium nitride, tantalum nitride, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, titanium, aluminum tantalum carbide, aluminum titanium nitride, tantalum carbide, tantalum carbonitride, silicon tantalum nitride, manganese, zirconium, other suitable work function metals, or combinations thereof. The substrate conductive layer may comprise copper, tungsten, aluminum, cobalt, ruthenium, other suitable materials, or combinations thereof. The metal gate stack 280 may further include other material layers (not shown), such as an interface layer located on the surface of the epitaxial layer 208, a capping layer, a barrier layer, other suitable layers, or combinations thereof. Various methods may be used to form the multiple layers of the metal gate stack 280, including atomic layer deposition, chemical vapor deposition, physical vapor deposition, plating, other suitable methods, or combinations thereof. After forming the substrate conductor layer, one or more chemical mechanical polishing processes may be performed to remove excess material from the upper surface of the interlayer dielectric layer 240, thereby planarizing the device 200.

[0106] Then as Figure 1A , 20A As shown in Figure 20B, step 120 of method 100 forms source / drain contacts 290 on source / drain structure 238. The source / drain contacts 290 may each comprise any suitable conductive material, such as cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, and / or other suitable conductive materials. Method 100 may form source / drain contact openings (or trenches, not shown) in interlayer dielectric layer 240 via a series of patterning and etching processes, followed by deposition of conductive material in the source / drain contact openings. Suitable deposition methods may include chemical vapor deposition, atomic layer deposition, physical vapor deposition, plating, and / or other suitable processes. In some embodiments, a silicide layer (not shown) may be formed between source / drain structure 238 and source / drain contacts 290. The silicide layer may comprise nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. The silicide layer may be formed on the source / drain structure 238, and its formation may be achieved through a series of deposition, thermal, and etching processes. In this embodiment, the bottom of the source / drain contact 290 extends into the top of the source / drain structure 238.

[0107] Figure 20C and 20D yes Figure 20AAn enlarged view of portion 243 of the device 200 is shown to illustrate various components following the formation of the source / drain contact 290. Forming (or landing) the source / drain contact 290 can further reduce the height of the source / drain structure 238. In these embodiments, the height h5 measured from the apex of the source / drain structure 238 to the top of the fin is less than the height h3. In some examples, the height h5 is from about 1 nm to about 5 nm. The range of height h5 provides a favorable balance between contact resistance and parasitic capacitance. In these embodiments, the source / drain structure 238 does not contact the gate spacer 234 because the adjustment step precedes the step of forming the source / drain contact 290. In these embodiments, the source / drain structure 238 has an arcuate upper surface, the first portion of which conforms to the bottom profile of the source / drain contact 290, while the second portion (containing the source / drain layers 239 and 237) conforms to the profile of the contact etch stop layer 242. The first part, including the bottom of the source / drain junction, is lower than the top of the fin, while the second part is higher than the top of the fin. Figure 20C In some of the examples shown, the first part is a concave shape, with its midpoint curving downwards (e.g., concave to the source / drain structure 238). Figure 20D In some other examples shown, the first part is a convex shape, with its midpoint bulging upwards to the bottom of the source / drain contact 290.

[0108] like Figure 1A As shown, step 122 of method 100 performs additional fabrication steps on device 200. For example, the additional fabrication steps on device 200 may include forming a multilayer interconnect structure (not shown) thereon. The multilayer interconnect may include various interconnect structures (such as vias and conductive lines) located in dielectric layers (such as etch stop layers and interlayer dielectric layers). In some embodiments, vias are vertical interconnect structures disposed with contacts of interconnect device layers, such as source / drain contacts or gate contacts (not shown), and conductive lines, or different conductive lines for interconnects. Conductive lines are horizontal interconnect structures. The etch stop layers and interlayer dielectric layers of the multilayer interconnect may have substantially the same composition as the aforementioned contact etch stop layer 242 and interlayer dielectric layer 240, respectively. The vias and conductive lines can each contain any suitable conductive material, such as cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, metal silicides, other suitable conductive materials, or combinations thereof, and can be formed by a series of patterning and deposition processes. Furthermore, the vias and conductive lines can each additionally contain a barrier layer containing titanium nitride and / or tantalum nitride.

[0109] One or more embodiments of the present invention can provide numerous advantages to semiconductor devices and their formation methods, but are not limited thereto. For example, embodiments of the present invention provide a method for adjusting the source / drain structure to reduce parasitic capacitance and source / drain junction landing effects. Surface treatment and subsequent etching processes can be modified to precisely control the adjustment of the source / drain structure. Devices with adjusted source / drain structures can reduce parasitic capacitance without sacrificing other device performance, such as resistance. Furthermore, the method implements a patterning process to avoid affecting other source / drain structures when selectively adjusting a selected source / drain structure.

[0110] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising providing a semiconductor structure including fins protruding from a substrate, wherein the fins include a plurality of first semiconductor layers and a plurality of second semiconductor layers interleaved in a vertical direction, and wherein the material composition of the first semiconductor layers is different from the material composition of the second semiconductor layers; recessing the fins to form source / drain recesses; forming source / drain structures in the source / drain recesses; trimming the source / drain structures; depositing a dielectric layer to cover the source / drain structures; forming contact holes in the dielectric layer to expose a portion of the source / drain structures; and depositing metal material in the contact holes to form metal contacts landing on the source / drain structures.

[0111] In some embodiments, the step of modifying the source / drain structure includes: treating the upper surface of the source / drain structure to change the chemical properties of the upper surface; and removing the treated upper surface of the source / drain structure.

[0112] In some embodiments, the step of treating the upper surface employs plasma oxidation, plasma nitriding, or a combination thereof to oxidize, nitrid, or a combination thereof on the upper surface of the source / drain structure.

[0113] In some embodiments, the step of modifying the source / drain structure reduces the top height of the source / drain structure by approximately 30% to 50%.

[0114] In some embodiments, the method further includes forming an inner spacer on the sidewall of the second semiconductor layer exposed in the source / drain recess, wherein the step of forming the source / drain structure includes: forming a first epitaxial layer in the source / drain recess on the first semiconductor layer; and forming a second epitaxial layer on the first epitaxial layer to contact the inner spacer, thereby filling the source / drain recess.

[0115] In some embodiments, the method further includes: forming a displacement gate stack on the fin; and forming a gate spacer on the sidewall of the displacement gate stack, wherein the step of forming the source / drain structure causes the source / drain structure to contact the gate spacer.

[0116] In some embodiments, the process of modifying the source / drain structure results in the modified source / drain structure not contacting the gate spacer.

[0117] In some embodiments, the step of modifying the source / drain structure results in the top of the modified source / drain structure being higher than the upper surface of the fin, and the height of the top being less than about 10 nm.

[0118] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: interleaving a first semiconductor layer and a second semiconductor layer to form a semiconductor stack on a substrate, wherein the first semiconductor layer and the second semiconductor layer have different material compositions; patterning the semiconductor stack to form a fin; forming a dummy gate stack on the fin; forming a source / drain recess in the fin adjacent to the dummy gate stack; epitaxially depositing a source / drain structure in the source / drain recess; processing the top of the source / drain structure; removing the processed top of the source / drain structure to form a reshaped source / drain structure; depositing an interlayer dielectric layer on the reshaped source / drain structure; forming a contact hole in the interlayer dielectric layer to expose the reshaped source / drain structure; and forming a metal plug in the contact hole to contact the reshaped source / drain structure.

[0119] In some embodiments, the source / drain recess is a first source / drain recess and the source / drain structure is a first source / drain structure, wherein the method further includes: forming a second source / drain recess in the fin to be adjacent to the dummy gate stack; forming a second source / drain structure in the second source / drain recess, wherein the width of the second source / drain structure is greater than the width of the first source / drain structure and the height of the second source / drain structure is less than the height of the first source / drain structure; and covering the second source / drain structure with a masking unit before processing the top of the first source / drain structure, thereby avoiding processing the second source / drain structure.

[0120] In some embodiments, the step of covering the second source / drain structure includes: depositing a masking unit on a substrate; patterning the masking unit to expose the first source / drain structure; and removing the patterned masking unit after the process of removing the first source / drain structure has finished.

[0121] In some embodiments, the step of processing the top of the first source / drain structure includes performing multiple decoupling plasma processing processes and multiple etching processes on the top of the first source / drain structure, wherein each decoupling plasma processing process is followed by an etching process to remove the decoupling plasma-processed top of the first source / drain structure.

[0122] In some embodiments, the top thickness processed by each decoupling process is less than the top thickness processed by the previous decoupling process.

[0123] In some embodiments, the etching conditions used in each etching process are milder than those used in the previous etching process.

[0124] In some embodiments, the decoupled plasma treatment process includes decoupled plasma oxidation and / or decoupled plasma nitriding.

[0125] In some embodiments, the step of forming the metal plug causes the top of the reshaped source / drain structure to be inserted into the metal plug.

[0126] Another embodiment of the present invention provides a semiconductor structure comprising a semiconductor substrate; a fin comprising a stack of semiconductor layers and located on the semiconductor substrate; a source / drain structure adjacent to the fin; and a source / drain contact landing on the source / drain structure. The source / drain structure has an arcuate upper surface, wherein a first portion of the arcuate upper surface is higher than the upper surface of the fin, and wherein a second portion of the arcuate upper surface is lower than the upper surface of the fin.

[0127] In some embodiments, the source / drain structure includes a first layer conforming to the bottom profile of the source / drain junction, and a second layer located on the sidewall of the stack of semiconductor layers, wherein the composition of the second layer is different from that of the first layer.

[0128] In some embodiments, the semiconductor structure further includes: a metal gate stack located on and covering the stack of semiconductor layers; and a gate spacer located on the sidewall of the metal gate stack, wherein the source / drain structure does not contact the gate spacer.

[0129] In some embodiments, a portion of the source / drain structure protrudes into the source / drain contact.

[0130] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the concept and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: A semiconductor structure is provided, comprising a fin protruding from a substrate, wherein the fin comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers interleaved in a vertical direction, and wherein the material composition of the plurality of first semiconductor layers is different from the material composition of the plurality of second semiconductor layers. A displacement gate is stacked on the fin; A gate spacer is formed on the sidewall of the replaced gate stack; The fin is recessed to form a source / drain recess; A source / drain structure is formed in the source / drain recess; Modify the source / drain structure; Deposit a dielectric layer to cover the source / drain structure; A contact hole is formed in the dielectric layer to expose a portion of the source / drain structure; as well as A metal material is deposited in the contact hole to form a metal contact landing on the source / drain structure, wherein the source / drain structure is separated from the gate spacer by the dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, wherein the step of trimming the source / drain structure includes: The upper surface of the source / drain structure is treated to alter its chemical properties; as well as Remove the top surface of the source / drain structure.

3. The method for forming a semiconductor structure as claimed in claim 2, wherein the step of processing the upper surface employs plasma oxidation, plasma nitriding, or a combination thereof, to oxidize, nitrid, or a combination thereof on the upper surface of the source / drain structure.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of trimming the source / drain structure reduces the top height of the source / drain structure by 30% to 50%.

5. The method for forming a semiconductor structure as claimed in claim 1, further comprising forming a plurality of inner spacers on the sidewalls of the plurality of second semiconductor layers exposed in the source / drain recess, wherein the step of forming the source / drain structure includes: A first epitaxial layer is formed on the plurality of first semiconductor layers exposed in the source / drain recess; as well as A second epitaxial layer is formed on the first epitaxial layer to contact the plurality of inner spacers, thereby filling the source / drain recess.

6. The method of forming a semiconductor structure as claimed in claim 1, wherein the step of forming the source / drain structure causes the source / drain structure to contact the gate spacer.

7. The method of forming a semiconductor structure as claimed in claim 6, wherein the step of adjusting the source / drain structure causes the adjusted source / drain structure to not contact the gate spacer.

8. The method of forming a semiconductor structure as claimed in claim 6, wherein the step of trimming the source / drain structure causes the top of the adjusted source / drain structure to be higher than the upper surface of the fin, and the height of the top of the adjusted source / drain structure is less than 10 nm.

9. A method for forming a semiconductor structure, comprising: Multiple first semiconductor layers and multiple second semiconductor layers are stacked alternately to form a semiconductor stack on a substrate, wherein the multiple first semiconductor layers and the multiple second semiconductor layers have different material compositions; The semiconductor stack is patterned to form a fin-like structure; A dummy gate is formed on the fin; A gate spacer is formed on the sidewall of the dummy gate stack; A source / drain is formed in the fin to be adjacent to the dummy gate stack; An epitaxial source / drain structure is deposited in the source / drain depression; Treat the top of this source / drain structure; Remove the top of the processed source / drain structure to form a reshaped source / drain structure; A dielectric layer is deposited on the reshaped source / drain structure; A contact hole is formed in the interlayer dielectric layer to expose the reshaped source / drain structure; as well as A metal plug is formed in the contact hole to contact the reshaped source / drain structure.

10. The method for forming a semiconductor structure as claimed in claim 9, wherein the source / drain recess is a first source / drain recess and the source / drain structure is a first source / drain structure, wherein the method further comprises: A second source / drain is formed in the fin to be adjacent to the dummy gate stack; A second source / drain structure is formed in the second source / drain recess, wherein the width of the second source / drain structure is greater than the width of the first source / drain structure, and the height of the second source / drain structure is less than the height of the first source / drain structure. as well as Before processing the top of the first source / drain structure, the second source / drain structure is covered with a masking unit to avoid processing the second source / drain structure, wherein the reshaped source / drain structure is separated from the gate spacer by the interlayer dielectric layer.

11. The method of forming a semiconductor structure as claimed in claim 10, wherein the step of covering the second source / drain structure comprises: The masking unit is deposited on the substrate; The masking unit is patterned to expose the first source / drain structure; as well as After removing the top of the first source / drain structure, the patterned masking unit is removed.

12. The method of forming a semiconductor structure as claimed in claim 10, wherein the step of processing the top of the first source / drain structure includes performing multiple decoupling plasma processing processes and multiple etching processes on the top of the first source / drain structure, wherein each of the decoupling plasma processing processes is followed by each of the etching processes to remove the decoupling plasma-processed top of the first source / drain structure.

13. The method for forming a semiconductor structure as claimed in claim 12, wherein the top thickness of each of the plurality of decoupled plasma processing processes is less than the top thickness of the previous plurality of decoupled plasma processing processes.

14. The method for forming a semiconductor structure as claimed in claim 12, wherein the etching conditions used in each of the plurality of etching processes are milder than the etching conditions used in the previous plurality of etching processes.

15. The method for forming a semiconductor structure as claimed in claim 12, wherein the plurality of decoupled plasma processing processes include decoupled plasma oxidation and / or decoupled plasma nitriding.

16. The method of forming a semiconductor structure as claimed in claim 9, wherein the step of forming the metal plug causes the top of the reshaped source / drain structure to penetrate the metal plug.

17. A semiconductor structure comprising: A semiconductor substrate; A fin-like structure comprising a stack of multiple semiconductor layers and located on the semiconductor substrate; A source / drain structure is adjacent to the fin, wherein the source / drain structure has an arcuate upper surface, wherein a first portion of the arcuate upper surface is higher than the upper surface of the fin, and wherein a second portion of the arcuate upper surface is lower than the upper surface of the fin. An interlayer dielectric layer is located on the source / drain structure; A source / drain contact is formed in the interlayer dielectric layer and landed on the source / drain structure; A metal gate stack is located on the stack of the plurality of semiconductor layers and covers the stack of the plurality of semiconductor layers; as well as A gate spacer is located on the sidewall of the metal gate stack, wherein the source / drain structure is separated from the gate spacer via the interlayer dielectric layer.

18. The semiconductor structure of claim 17, wherein the source / drain structure includes a first layer conforming to the bottom profile of the source / drain junction, and a second layer located on the sidewall of the stack of the plurality of semiconductor layers, wherein the second layer has a different composition from the first layer.

19. The semiconductor structure of claim 17, wherein the source / drain structure is not in contact with the gate spacer.

20. The semiconductor structure of claim 17, wherein a portion of the source / drain structure protrudes into the source / drain junction.

Images