Display substrate and display device

Abstract

The embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate and a planarization layer, a heat dissipation layer, a light-emitting device and a thin film transistor arranged on the base substrate; the planarization layer is located on the side of the thin film transistor away from the base substrate; the first electrode of the light-emitting device is connected to the drain electrode of the thin film transistor through a via hole on the planarization layer; the heat dissipation layer is located between the first electrode and the planarization layer and contacts the first electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] An organic light emitting diode (OLED) device is an electroluminescent device based on organic semiconductor materials. Existing OLED devices have poor heat dissipation performance during use, which affects the light output efficiency of the OLED device and causes energy loss. Summary of the invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, including: a base substrate, and a planarization layer, a heat dissipation layer, a light emitting device, and a thin film transistor arranged on the base substrate;

[0005] The planarization layer is located on a side of the thin film transistor away from the substrate;

[0006] The first electrode of the light emitting device is connected to the drain electrode of the thin film transistor through a via hole on the planarization layer;

[0007] The heat dissipation layer is located between the first electrode and the planarization layer, and contacts the first electrode.

[0008] In some embodiments, the thermal conductivity of the heat dissipation layer is greater than the thermal conductivity of the planarization layer and is not less than the thermal conductivity of the first electrode.

[0009] In some embodiments, the number of the light-emitting devices is multiple; the display substrate further includes a pixel defining layer, the pixel defining layer is located on a side of the first electrode away from the base substrate, and has multiple openings, and the light-emitting devices are arranged in the openings one by one;

[0010] The thermal conductivity of the heat dissipation layer is greater than the thermal conductivity of the pixel defining layer.

[0011] In some embodiments, the heat dissipation layer is a whole layer structure and has a plurality of hollow portions, and the first electrode is connected to the drain electrode of the thin film transistor through the hollow portions;

[0012] The heat dissipation layer is made of insulating material.

[0013] In some embodiments, at least a portion of the heat dissipation layer is located within the via.

[0014] In some embodiments, the thermal conductivity of the heat dissipation layer is between 150 W / (mK) and 450 W / (mK).

[0015] In some embodiments, the material of the heat dissipation layer includes at least one or more of BeO, Al2O3, polyurethane, and rubber.

[0016] In some embodiments, a ratio of a thickness of the heat dissipation layer to a thickness of the first electrode is between 0.75 and 1.25.

[0017] In a second aspect, an embodiment of the present disclosure provides a display device including the display substrate described in the first aspect.

[0018] In some embodiments, the display substrate further includes a plurality of pixel circuits, the pixel circuits correspond to the light emitting devices one by one, and include a plurality of thin film transistors, and the light emitting device is connected to at least one thin film transistor in the corresponding pixel circuit;

[0019] The display device further includes: a driving structure for providing a driving signal to the pixel circuit; the driving signal includes a light emitting control signal, the light emitting control signal is in an invalid level state in a non-light emitting phase of the pixel circuit, and is in a valid level state in a light emitting phase of the pixel circuit;

[0020] The ratio of the duration of the effective level state to the duration of the invalid level state is between 7 / 3 and 9. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0022] Figure 1 is a structural schematic diagram of a display panel;

[0023] Figure 2 It is a structural schematic diagram of a display substrate;

[0024] Figure 3 is a schematic structural diagram of another display substrate;

[0025] Figure 4 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0027] Figure 6 A planar structural diagram of a heat dissipation layer provided in an embodiment of the present disclosure;

[0028] Figure 7A schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0029] Figure 8 for Figure 7 A driving timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0030] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] The display substrate includes a plurality of light-emitting devices, each of which corresponds to a pixel circuit, which is used to provide a driving current to the light-emitting device to drive the light-emitting device to emit light. During the display process of the display substrate, the display brightness of the light-emitting device can be increased by increasing the driving current. Generally, when the driving current passes through the light-emitting device, about 3 to 5% of the energy is converted into light energy, and the remaining energy of about 90% or more is converted into heat. Therefore, increasing the driving current will generate more heat in the display substrate.

[0034] When the light-emitting device is an OLED device, the material of its light-emitting functional layer has a greater resistance than other metal wires, so the light-emitting material of the light-emitting device is the main source of heat in the display substrate. In addition, when the display substrate is a dedicated vehicle-mounted display substrate, the heat generated is more difficult to dissipate, affecting the light-emitting efficiency and service life of the display substrate.

[0035] In some embodiments, the heat dissipation structure is generally configured using the following structure to achieve a heat dissipation effect for the display substrate.

[0036] Figure 1 is a schematic diagram of the structure of a display panel, such as Figure 1 As shown, a heat dissipation film 12 is arranged on the OLED display substrate 11. The heat dissipation film has mesh-shaped grooves, and the grooves are filled with adhesive 14. The heat dissipation film 12 is attached to the back of the OLED display substrate 11 through the adhesive 14. The attached surface of the heat dissipation film 12 not filled with adhesive 14 can directly contact the OLED display substrate 11, thereby achieving the purpose of heat dissipation. However, in this heat dissipation method, the heat generated by the light-emitting device needs to pass through multiple layers of materials, which limits the heat dissipation speed and leads to poor heat dissipation effect of the display substrate.

[0037] Figure 2 is a schematic diagram of the structure of a display substrate, such as Figure 2 As shown, a heat dissipation film 24 is added to the side of the encapsulation layer 23 (including the first encapsulation layer 231 and the second encapsulation layer 232) of the display substrate close to the light-emitting device to improve the heat dissipation performance of the display substrate. Although this heat dissipation method can increase the heat dissipation area above the light-emitting device 22 arranged on the first substrate 21, it will affect the light extraction efficiency of the light-emitting device 22 and cause energy loss.

[0038] Figure 3 is a schematic diagram of the structure of another display substrate, such as Figure 3 As shown, a heat dissipation film 37 is provided on the side of the base substrate 31 of the display substrate away from the light emitting device 30. During the display process of the display substrate, the light emitting functional layer 34 of the light emitting device 30 generates heat, which is thermally diffused outward through the cathode 35, the encapsulation layer 36 and the base substrate 31 in the thickness direction of the display substrate, and thermally diffused outward through the adjacent pixel defining layer 32 and the anode 33 on the vertical plane in the thickness direction of the display substrate. It should be noted that although the above-mentioned heat dissipation film 37 can increase the heat conduction speed of the outer layer of the display substrate, that is, increase the heat dissipation speed, the heat dissipation film 37 is relatively thick because its material includes a composite material of metal material, graphite material, rubber material, etc., so there is a certain thermal resistance in the thickness direction of the display substrate when it dissipates heat, resulting in an unsatisfactory heat dissipation effect of the display substrate.

[0039] In order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a display substrate, which improves the heat dissipation effect of the display substrate by arranging a heat dissipation layer at a position close to the light-emitting device.

[0040] Figure 4 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, an embodiment of the present disclosure provides a display substrate, including: a base substrate 1 and a planarization layer 2, a heat dissipation layer 3, a thin film transistor 4 and a light emitting device 5 arranged on the base substrate 1.

[0041] Among them, the planarization layer 2 is located on the side of the thin film transistor 4 away from the base substrate 1; the light-emitting device 5 includes a first electrode 51, a second electrode 53 and a light-emitting functional layer 52 located therebetween, and the first electrode 51 is connected to the drain 41 of the thin film transistor 4 through a via hole on the planarization layer 2; the heat dissipation layer 3 is located between the first electrode 51 and the planarization layer 2, and is in contact with the first electrode 51, thereby reducing the number of film layers between the light-emitting device 5 and the heat dissipation layer 3, and improving the heat dissipation speed and heat dissipation effect of the display substrate.

[0042] In addition, the light-emitting device 5 in the embodiment of the present disclosure is a top-emitting light-emitting device. Optionally, the first electrode 51 is a reflective electrode made of a metal material, and the second electrode 53 is a transparent electrode made of a transparent conductive material (for example, indium tin oxide). Then, the heat dissipation layer 3 is arranged between the first electrode 51 and the planarization layer 2, which will not affect the light emission of the light-emitting device 5.

[0043] In some embodiments, the thermal conductivity of the heat dissipation layer 3 is greater than the thermal conductivity of the planarization layer 2, so that the heat dissipation layer 3 can diffuse the heat generated by the light-emitting device 5 toward the direction close to the base substrate 1; the thermal conductivity of the heat dissipation layer 3 is not less than the thermal conductivity of the first electrode 51, so that the heat dissipation layer 3 can diffuse the heat generated by the light-emitting device 5 in a direction parallel to the base substrate 1 to reduce the temperature of the display substrate during light-emitting display.

[0044] In some embodiments, Figure 4 As shown, there are multiple light-emitting devices 5 in the display substrate; the display substrate also includes a pixel defining layer 6, which is located on the side of the first electrode 51 away from the base substrate 1 and has multiple openings, and the light-emitting devices 5 are arranged in the openings one by one; the thermal conductivity of the pixel defining layer is smaller than the thermal conductivity of the heat dissipation layer 3, so that the heat dissipation layer 3 can diffuse the heat generated by the light-emitting device 5 away from the base substrate 1, so as to reduce the temperature of the display substrate during light-emitting display.

[0045] like Figure 4As shown, the light emitting device 5 further includes a light emitting functional layer 52 and a second electrode 53 located on a side of the first electrode 51 away from the base substrate 1, and the light emitting functional layer 52 and the second electrode 53 are sequentially arranged in a direction away from the base substrate 1. The above-mentioned light emitting devices 5 are arranged in the openings one by one, specifically, a part of the first electrode 51 is exposed by the opening, the light emitting functional layer 52 is arranged in the opening, and the second electrodes 53 of the plurality of light emitting devices 5 can form an integrated structure.

[0046] In one example, the first electrode 51 may be an anode, and the second electrode 53 may be a cathode. In addition, the light-emitting functional layer 52 may include: a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence.

[0047] Figure 5 A schematic diagram of the structure of another display substrate provided in an embodiment of the present disclosure, Figure 6 A planar structure diagram of a heat dissipation layer provided in an embodiment of the present disclosure, in some embodiments, such as Figure 5 , 6 As shown, the heat dissipation layer 3 is a whole layer structure and has a plurality of hollow portions 3a, and the first electrode 51 is connected to the drain electrode 41 of the thin film transistor 4 through the hollow portions 3a. By setting the heat dissipation layer 3 as a whole layer structure between the first electrode 51 and the planarization layer 2, the heat dissipation area of ​​the heat dissipation layer 3 is increased, so that the heat generated by the light emitting device 5 can be evenly diffused, thereby improving the heat dissipation effect of the display substrate.

[0048] In addition, when the heat dissipation layer 3 is a whole-layer structure, the heat dissipation layer 3 is set to be an insulating material to avoid short circuits between different first electrodes 51 .

[0049] In some embodiments, the material of the heat dissipation layer 3 includes at least one or more of BeO, Al2O3, and polyurethane, and may also be other rubber materials having good thermal conductivity and insulation properties, so that the heat dissipation layer 3 can effectively diffuse heat without affecting the luminous effect of the display substrate.

[0050] When the material of the heat dissipation layer 3 is an inorganic material such as Al2O3, it can be formed by a physical vapor deposition process, and the hollow portion 3a can be etched out by a dry etching process to facilitate the connection between the first electrode 51 and the drain of the thin film transistor 4; when the material of the heat dissipation layer 3 is a rubber material, it can be formed by a glue coating process, and the rubber film layer can be patterned by exposure, development and etching processes to form a heat dissipation layer 3 having a hollow portion 3a.

[0051] In some embodiments, Figure 5As shown, at least a portion of the heat dissipation layer 3 is located in the via hole of the planarization layer 2, that is, the heat dissipation layer 3 is also provided on the side wall of the via hole of the planarization layer 2 to maximize the contact area between the heat dissipation layer 3 and the first electrode 51 and improve the heat dissipation effect of the heat dissipation layer 3.

[0052] Optionally, the greater the thickness of the heat dissipation layer 3, the better the heat dissipation effect. However, the heat dissipation layer 3 in the embodiment of the present disclosure is arranged between the first electrode 51 and the planarization layer 2. If the thickness of the heat dissipation layer 3 is too large, it will affect the connection between the first electrode 51 and the drain 41. Therefore, in the embodiment of the present disclosure, the ratio of the thickness of the heat dissipation layer 3 to the thickness of the first electrode 51 is set between 0.75 and 1.25, thereby ensuring the connection reliability between the first electrode 51 and the drain 41 while improving the heat dissipation effect of the display substrate.

[0053] In some embodiments, the thermal conductivity of the heat dissipation layer 3 is between 150W / (mK) and 450W / (mK). Optionally, the thermal conductivity of the heat dissipation layer 3 can be any one of 150W / (mK), 200W / (mK), 250W / (mK), 300W / (mK), 350W / (mK), 400W / (mK), and 450W / (mK).

[0054] The thermal conductivity described in the embodiments of the present disclosure is a coefficient reflecting the thermal conductivity of a material, and is specifically defined as the amount of heat transferred by the material through a unit heat conduction surface in a unit time under a unit temperature gradient (temperature drops by 1K within a length of 1m).

[0055] In some embodiments, Figure 5 As shown, the display substrate may further include an encapsulation layer 7 located on the side of the second electrode 53 away from the base substrate 1, so as to isolate water vapor, protect the various film layers in the display substrate from corrosion, and improve the protection effect of the various film layers in the display area. The encapsulation layer 7 may include an inorganic encapsulation layer and an organic encapsulation layer, for example, the encapsulation layer 7 includes a first inorganic encapsulation layer and a second inorganic encapsulation layer and an organic encapsulation layer located therebetween.

[0056] like Figure 4 , 5As shown, the thin film transistor 4 includes a gate 44, an active layer 43, a source 42 and a drain 41. Taking the thin film transistor 4 as an example, the gate 44 is located on the side of the active layer 43 away from the substrate 1, and the source 42 and the drain 41 are located on the side of the gate 44 away from the substrate 1. The material of the active layer 43 may include, for example, inorganic semiconductor materials (for example, polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials. The active layer 43 includes a channel portion and a source connection portion and a drain connection portion located on both sides of the channel portion. The source connection portion is connected to the source 42 of the thin film transistor, and the drain connection portion is connected to the drain 41 of the thin film transistor. Both the source connection portion and the drain connection portion may be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than the channel portion. The channel portion is directly opposite to the gate electrode 44 of the thin film transistor. When the voltage signal loaded on the gate electrode 44 reaches a certain value, a carrier path is formed in the channel portion, so that the source electrode 42 and the drain electrode 41 of the thin film transistor are turned on.

[0057] like Figure 2 , 3 As shown, the display substrate further includes: a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2 and an interlayer insulating layer ILD. The buffer layer BUF is located between the base substrate 1 and the thin film transistor 4, and is used to prevent or reduce the diffusion of metal atoms and / or impurities from the base substrate 1 into the active layer 43 of the thin film transistor. The buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be formed as a multilayer or a single layer.

[0058] The first gate insulating layer GI1 is located between the active layer 43 and the gate electrode 44 of the thin film transistor; the second gate insulating layer GI2 and the interlayer insulating layer ILD are located between the gate electrode 44 and the source electrode 42 of the thin film transistor, and the interlayer insulating layer ILD is located on the side of the second gate insulating layer GI2 away from the substrate 1. The materials of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may include silicon compounds or metal oxides, and may be formed into a single layer or multiple layers, which is not limited in the embodiments of the present disclosure.

[0059] The gate electrode layer is arranged on the side of the first gate insulating layer GI1 away from the substrate 1. The gate electrode layer includes the gate 44 of each thin film transistor, the first electrode plate of the capacitor, and the second electrode plate of the capacitor. The second electrode plate of the capacitor (not shown in the figure) is arranged on the side of the second gate insulating layer GI2 away from the substrate 1, and is connected to the source 42 of the thin film transistor, and its material can be the same as the material of the first electrode plate. The material of the gate electrode layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate electrode layer may include gold, gold alloy, silver, silver alloy, aluminum, aluminum alloy, aluminum nitride, tungsten, tungsten nitride, copper, copper alloy, nickel, chromium, chromium nitride, molybdenum, molybdenum alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, tin oxide, indium oxide, gallium oxide, indium tin oxide, indium zinc oxide, etc. The gate electrode layer may have a single layer or multiple layers.

[0060] In addition, if Figure 4 , 5 As shown, the display substrate may further include a passivation layer (not shown) between the drain electrode 41 of the thin film transistor 4 and the planarization layer 2, and the first electrode 51 will be connected to the drain electrode 41 through a via hole penetrating the passivation layer and the planarization layer 2. The material of the passivation layer may include, for example, silicon oxynitride, silicon oxide, silicon nitride, etc.

[0061] The embodiment of the present disclosure also provides a display device, comprising the above-mentioned display substrate.

[0062] In some embodiments, the display substrate further includes a plurality of pixel circuits, which correspond to the light-emitting devices 5 one by one, and include a plurality of thin film transistors 4, and the light-emitting devices 5 are connected to at least one thin film transistor 4 in the corresponding pixel circuit. The pixel circuit includes at least a switching transistor and a driving transistor, and may also include structures such as a threshold compensation transistor and a storage capacitor.

[0063] The display device also includes a driving structure for providing a driving signal for the pixel circuit; the driving signal includes a reset signal, a light-emitting control signal, etc. mentioned below, and the light-emitting control signal is in an invalid level state in the non-light-emitting stage of the pixel circuit and is in a valid level state in the light-emitting stage of the pixel circuit.

[0064] Among them, the transistor used above can be a thin film transistor 4 or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present invention, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first electrode is the source of the P-type transistor, the second electrode is the drain of the P-type transistor, and the source and drain are turned on when the gate inputs a low level; when an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and the source and drain are turned on when the gate inputs a high level. Among them, the transistors in the above-mentioned pixel circuits are all explained by taking N-type transistors as examples. It can be thought that the use of P-type transistors is something that a person skilled in the art can easily think of without paying creative labor, so it is also within the protection scope of the embodiment of the present invention.

[0065] Figure 7 A schematic diagram of a pixel circuit provided by an embodiment of the present disclosure, in one example, as Figure 7 As shown, the pixel circuit includes: a first reset transistor T1, a second reset transistor T7, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first capacitor Cst, a second capacitor C2 and a light emitting device D.

[0066] Specifically, the gate of the first reset transistor T1 is connected to the reset signal terminal Reset, the source is connected to the initialization signal terminal Vint, and the drain is connected to the first node N1; the first node N1 is the connection point between the first reset transistor T1, the driving transistor T3, the first capacitor Cst, and the threshold compensation transistor T2. The gate of the second reset transistor T7 is connected to the reset signal terminal Reset, the source is connected to the initialization signal terminal Vint, and the drain is connected to the anode of the light-emitting device D. The gate of the data writing transistor T4 is connected to the scanning signal terminal Gate, the source is connected to the data signal terminal Data, and the drain is connected to the source of the driving transistor T3. The gate of the driving transistor T3 is connected to the first node N1, the source is connected to the drain of the data writing transistor T4 and the drain of the first light-emitting control transistor T5, and the drain is connected to the source of the threshold compensation transistor T2 and the source of the second light-emitting control transistor T6. One end of the first capacitor Cst is connected to the first power supply voltage terminal VDD, and the other end is connected to the first node N1. One end of the second capacitor C2 is connected to the first power supply voltage terminal VDD, and the other end is connected to the source of the driving transistor T3. The gate of the threshold compensation transistor T2 is connected to the scanning signal terminal Gate, the source is connected to the drain of the driving transistor T3, and the drain is connected to the first node N1. The gate of the first light-emitting control transistor T5 is connected to the light-emitting control terminal EM, the source is connected to the first power supply voltage terminal VDD, and the drain is connected to the source of the driving transistor T3. The gate of the second light-emitting control transistor T6 is connected to the light-emitting control terminal EM, the source is connected to the drain of the driving transistor T3, and the drain is connected to the anode of the light-emitting device D. The anode of the light-emitting device D is connected to the drain of the second light-emitting control transistor T6 and the drain of the second reset transistor T7, and the cathode is connected to the second power supply voltage terminal VSS.

[0067] The following describes the working process of the pixel circuit by taking the transistors in the pixel circuit as P-type transistors as an example. At this time, the effective level refers to the low level, and the invalid level refers to the high level. Figure 8 for Figure 7 A driving timing diagram of the pixel circuit shown in FIG. Figure 8 As shown, the working process of the pixel circuit is divided into: a non-luminous stage and a luminous stage S3, wherein the non-luminous stage includes a reset stage S1 and a data writing stage S2.

[0068] In the reset stage S1, a low-level signal is input to the reset signal terminal Reset, and the first reset transistor T1 and the second reset transistor T7 are turned on under the control of the low-level signal. The initialization signal (low-level signal) input to the initialization signal terminal Vint is used to reset the first node N1 and the anode of the light-emitting device D, respectively, so that the first node N1 and the anode of the light-emitting device D are restored to a lower potential, thereby preventing the high-level data signal input from the previous frame of the display from interfering with the first node N1 and the anode of the light-emitting device D, thereby affecting the accuracy of the data signal input this time.

[0069] In the data writing stage S2, the scanning signal terminal Gate inputs a low-level signal, the data writing transistor T4 is turned on under the control of the low-level signal, and the data signal is written into the source of the driving transistor T3, and the first capacitor Cst and the second capacitor C2 store the data signal. At the same time, the threshold compensation transistor T2 is turned on under the control of the low-level signal, and the driving transistor T3 is turned on under the control of the data signal stored in the first capacitor Cst and the second capacitor C2, so that the gate and drain of the driving transistor T3 are connected, and the driving transistor T3 is in a self-saturated state. At this time, the first node N1 is written with the data signal and the threshold voltage of the driving transistor T3, so as to realize the compensation of the threshold voltage of the driving transistor T3.

[0070] In the light-emitting stage S3, a low-level signal is input to the switch control signal terminal EM, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the low-level signal. The driving transistor T3 can convert the voltage of the first power supply voltage terminal VDD into a driving current, so that the light-emitting device D between the first power supply voltage terminal VDD and the second power supply voltage terminal VSS forms a current loop, driving the light-emitting device D to emit light.

[0071] like Figure 8 As shown, the switch control signal terminal EM inputs the light-emitting control signal, which is a low-level signal in the light-emitting stage S3, and the duration of the low-level signal is t2. At this time, the light-emitting device D is in the light-emitting state. In this stage, the light-emitting device generates heat Q, and the heat Q can be expressed by formula 1; the light-emitting control signal is a high-level signal in the reset stage S1 and the data writing stage S2, and its invalid level state duration is t1. This stage is the heat dissipation time of the display substrate.

[0072] Q=I 2 Rt2 Formula 1

[0073] Among them, I is the driving current, R is the resistance generated by the light-emitting device, and t2 is the light-emitting time.

[0074] It can be seen from the above formula that the luminous duration t2 is proportional to the heat Q generated by the light-emitting device. Therefore, reducing the effective level state duration t2 of the light-emitting control signal within a unit period can reduce the duration of heat generated by the light-emitting device, thereby reducing the heat generated by the light-emitting device; at the same time, reducing the effective level state duration t2 within the unit period can increase the invalid level state duration t1, that is, increase the heat dissipation time t1 of the display substrate, thereby improving the heat dissipation effect of the display substrate.

[0075] Table 1 shows the heat dissipation parameters of the display substrates in multiple examples, where, as shown in Table 1, with Example 1 as a reference, Examples 2-8 show parameters such as the equilibrium temperature rise of t2 / (t1+t2) at different ratios of 50%-90%. It should be noted that the structures of the display substrates used in Examples 1-8 are all that a heat dissipation film is provided on the side of the base substrate away from the light-emitting device, for example Figure 3 The display substrate structure shown in .

[0076] It can be concluded from the data of Examples 1-8 in Table 1 that when the effective level state duration ratio t2 / (t1+t2) of the light emitting control signal in a unit period is between 70% and 90%, the effect of reducing the balanced temperature rise can be achieved to varying degrees compared with the comparative example. In addition, as shown in the data of Example 6, although its balanced temperature rise is also lower than that of the comparative example, its driving current is 151% of the driving current of the comparative example, and its driving current is greater than the current shown in Example 5, but the balanced temperature rise is greater than the temperature shown in Example 5. Therefore, when t2 / (t1+t2) is 65%, a certain degree of energy waste is caused.

[0077] It should be noted that the unit cycle temperature rise in Table 1 refers to the temperature change caused by the heat generated by the display substrate in a unit cycle, and the equilibrium temperature rise refers to the temperature of the display substrate after heat dissipation in the invalid level state for a period of time t1.

[0078] Table 1

[0079]

[0080]

[0081] It can be determined from the data of Examples 1-8 in Table 1 that when the ratio t2 / (t1+t2) of the effective level state duration to the unit period is between 70% and 90%, that is, the ratio of the effective level state duration to the invalid level state duration is between 7 / 3 and 9, the equilibrium temperature rise of the display substrate can be reduced, that is, the temperature rise of the display substrate caused by the heat generated by the light-emitting device when emitting light can be effectively reduced.

[0082] Based on the above experimental results, the ratio of the duration of the effective level state to the duration of the invalid level state of the light emitting control signal provided by the embodiment of the present disclosure is between 7 / 3 and 9.

[0083] The display device provided by the embodiment of the present disclosure, on the one hand, has a heat dissipation layer 3 of a whole structure disposed between the first electrode 51 of the light-emitting device 5 and the planarization layer 2 on its display substrate, which reduces the number of film layers between the light-emitting device 5 and the heat dissipation layer 3, and increases the contact area between the heat dissipation layer 3 and the first electrode 51; on the other hand, the effective level state duration t2 of the pixel circuit in a unit cycle is reduced to reduce the duration of the heat generated by the light-emitting device 5, and the invalid level state duration t1 is increased to increase the heat dissipation duration. As shown in Table 1, based on Example 5, the display device provided by the embodiment of the present disclosure can reduce the equilibrium temperature rise to 15°C, further improving the heat dissipation effect of the display device.

[0084] In addition, since the heat dissipation space of the vehicle-mounted display device is small, the requirements for its heat dissipation capacity are relatively high. The display device provided by the embodiment of the present disclosure optimizes the driving timing of the pixel circuit of the display substrate on the one hand, and adjusts the structure of the display substrate on the other hand, and finally reduces the equilibrium temperature rise to 15°C. Therefore, the display device provided by the embodiment of the present disclosure is particularly suitable for vehicle-mounted display devices and can meet the requirements for the heat dissipation capacity of the display device.

[0085] The above-mentioned display device can be: electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator and any other product or component with display function, which is not limited in the present disclosure.

[0086] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A base substrate and a planarization layer, a heat dissipation layer, a light emitting device and a thin film transistor arranged on the base substrate; The planarization layer is located on a side of the thin film transistor away from the substrate; The first electrode of the light emitting device is connected to the drain electrode of the thin film transistor through a via hole on the planarization layer; The heat dissipation layer is located between the first electrode and the planarization layer, and contacts the first electrode; At least a portion of the heat dissipation layer is located in the via hole.

2. The display substrate according to claim 1, characterized in that: The thermal conductivity of the heat dissipation layer is greater than the thermal conductivity of the planarization layer and is not less than the thermal conductivity of the first electrode.

3. The display substrate according to claim 1, characterized in that: The number of the light-emitting devices is multiple; the display substrate further includes a pixel defining layer, the pixel defining layer is located on a side of the first electrode away from the base substrate, and has a plurality of openings, and the light-emitting devices are arranged in the openings one by one; The thermal conductivity of the heat dissipation layer is greater than the thermal conductivity of the pixel definition layer.

4. The display substrate according to claim 1, characterized in that: The heat dissipation layer is a whole layer structure and has a plurality of hollow parts, and the first electrode is connected to the drain electrode of the thin film transistor through the hollow parts; The heat dissipation layer is made of insulating material.

5. The display substrate according to any one of claims 1 to 4, characterized in that: The thermal conductivity of the heat dissipation layer is between 150W / (mK) and 450W / (mK).

6. The display substrate according to any one of claims 1 to 4, characterized in that: The material of the heat dissipation layer includes at least one or more of BeO, Al2O3, polyurethane and rubber.

7. The display substrate according to any one of claims 1 to 4, characterized in that: The ratio of the thickness of the heat dissipation layer to the thickness of the first electrode is between 0.75 and 1.

25.

8. A display device, characterized in that: The display device comprises: a display substrate as described in any one of claims 1-7.

9. The display device according to claim 8, characterized in that: The display substrate further includes a plurality of pixel circuits, each of which corresponds to the light-emitting device on a one-to-one basis and includes a plurality of thin film transistors, and the light-emitting device is connected to at least one thin film transistor in a corresponding pixel circuit; The display device further includes: A driving structure for providing a driving signal for the pixel circuit; the driving signal comprises a light emitting control signal, the light emitting control signal is in an invalid level state during a non-light emitting phase of the pixel circuit, and is in a valid level state during a light emitting phase of the pixel circuit; The ratio of the duration of the effective level state to the duration of the invalid level state is between 7 / 3 and 9.

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