Chip units, chip components and 3D chips

Abstract

The embodiments of the present application provide a chip unit, a chip assembly, and a 3D chip, wherein the chip unit includes: a substrate layer; a metal layer, the metal layer including a first surface and a second surface arranged opposite to each other, the second surface of the metal layer being arranged on the substrate layer; a metal layer through-hole assembly arranged in the metal layer, the metal layer through-hole assembly including: a first conductor, a second conductor, and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed in the metal layer, the second conductor being connected to the first conductor via the conductor connection hole so that a signal can be transmitted to the first surface through the substrate layer; a substrate through-hole, provided in the substrate layer; and a lead connected to the first conductor and / or the second conductor. The chip unit can make the wiring method of the chip unit more flexible, in particular, it can reduce the area occupied by the leads on the front of the chip unit, making the layout and arrangement of the leads simpler.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip unit, a chip component and a 3D chip. Background Art

[0002] With the advancement of chip technology and the increasing demand for information technology, 3D chips are increasingly appearing in the integrated circuit industry. Due to signal transmission requirements, signal connections in 3D chips must pass through the entire chip. These connections are achieved through perforations from the front to the back of the chip, primarily using through-silicon vias (TSVs).

[0003] Because TSVs must penetrate the entire chip, not only through the various materials that make up the stacked circuits but also through the very thick silicon substrate, they place high demands on the etching technology used to create the vias. Furthermore, the TSVs are large in diameter and length, resulting in a significant increase in chip area, high parasitic resistance and capacitance parameters, a long manufacturing cycle, and high costs. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0005] In view of this, according to the first aspect of an embodiment of the present application, a chip unit is proposed, comprising: a substrate layer; a metal layer, the metal layer comprising a first surface and a second surface arranged opposite to each other, the second surface of the metal layer being arranged on the substrate layer; a metal layer through-hole component, arranged in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed in the metal layer, the second conductor being connected to the first conductor through the conductor connection hole, so that the signal can be transmitted to the first surface through the substrate layer; a substrate through-hole, opened on the substrate layer and connected to the second conductor; a lead, connected to the first conductor and / or the second conductor.

[0006] In a first possible implementation manner of the first aspect, the chip unit further includes: a metal filling layer disposed on the substrate through hole and / or the first conductor, and the lead is connected to the metal filling layer.

[0007] In a second possible implementation of the first aspect, the chip unit further includes: a substrate conductor member, disposed within the substrate layer; the substrate through hole includes a bottom through hole and an intermediate connecting hole, the bottom through hole being opened at the bottom of the substrate and connected to the substrate conductor member, the intermediate connecting hole being located between the substrate conductor member and the second conductor member, the substrate conductor member being connected to the second conductor member through the intermediate connecting hole; wherein the lead is connected to the second conductor member through the substrate conductor member.

[0008] In a third possible implementation of the first aspect, the intermediate connecting hole is processed along the direction from the first surface to the substrate layer.

[0009] In a fourth possible implementation of the first aspect, the lead is connected to the second conductor through the substrate conductor.

[0010] In a fifth possible implementation of the first aspect, the chip unit further includes: a conductor dielectric filling layer filled in the substrate through-hole.

[0011] In a sixth possible implementation of the first aspect, the chip unit further includes: a heat dissipation layer covering the conductive dielectric filling layer.

[0012] In a seventh possible implementation manner of the first aspect, the chip unit further includes: a conductive dielectric filling layer made of a metal material and / or a heat dissipation layer made of a metal material.

[0013] In an eighth possible implementation of the first aspect, the metal layer through-hole assembly further includes: an on-chip conductor part, arranged in the metal layer, located between the first conductor part and the second conductor part; wherein, there are multiple conductor connection holes, the second conductor part is connected to the on-chip conductor part through some of the multiple conductor connection holes, and the on-chip conductor part is connected to the first conductor part through some of the multiple conductor connection holes.

[0014] In a ninth possible implementation of the first aspect, there are multiple on-chip conductor parts, the multiple on-chip conductor parts are spaced apart between the first conductor part and the second conductor part, and adjacent on-chip conductor parts are connected through some of the multiple conductor connection holes.

[0015] In a tenth possible implementation of the first aspect, a conductor connection hole is provided between two adjacent on-chip conductor parts.

[0016] In an eleventh possible implementation manner of the first aspect, a conductor connection hole is provided between the first conductor component and an adjacent on-chip conductor component.

[0017] In a twelfth possible implementation manner of the first aspect, a conductor connection hole is provided between the second conductor component and an adjacent on-chip conductor component.

[0018] In a thirteenth possible implementation manner of the first aspect, a difference between the number of the conductor connection holes and the number of the conductor connection pieces is 1.

[0019] In a fourteenth possible implementation of the first aspect, the cross-section of the substrate through hole along the substrate height direction is a polygon, and the length of the first side of the polygon close to the metal layer is smaller than the length of the second longest side of the polygon away from the metal layer.

[0020] In a fifteenth possible implementation of the first aspect, a cross-section of the substrate through-hole along a height direction of the substrate is trapezoidal.

[0021] In a sixteenth possible implementation of the first aspect, the short side of the trapezoid is located on a side of the substrate layer close to the metal layer, and the long side of the trapezoid is located on a side of the substrate layer far from the metal layer.

[0022] In a seventeenth possible implementation of the first aspect, the substrate through hole is truncated cone-shaped.

[0023] In the eighteenth possible implementation of the first aspect, the truncated cone includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer close to the metal layer, and the second end face is located on the side of the substrate layer away from the metal layer.

[0024] In a nineteenth possible implementation manner of the first aspect, the conductor connection hole is columnar.

[0025] According to a second aspect of an embodiment of the present application, a chip assembly is provided, comprising: a chip unit according to any of the above technical solutions; the leads of the chip unit are connected to the second conductor, and the chip unit is connected to the substrate through the leads.

[0026] In a first possible implementation manner of the second aspect, the substrate through-hole of the chip unit is filled with a heat dissipation medium layer, and the chip unit is connected to the substrate through the heat dissipation medium layer.

[0027] According to a third aspect of an embodiment of the present application, a 3D chip is provided, comprising: at least two stacked chip units of any of the above-mentioned technical solutions; at least two chip units include a first chip unit, and when the substrate layer of the first chip unit is set on a substrate, one end of the lead of the first chip unit is connected to the second conductor of the first chip unit, and the other end is connected to the substrate.

[0028] In a first possible implementation of the third aspect, the substrate through hole of the first chip unit is filled with a heat dissipation medium layer. When the substrate layer of the first chip unit is arranged on the substrate, the first chip unit is connected to the substrate through the heat dissipation medium layer.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] 1) The chip unit provided in the embodiments of the present application has a substrate through-hole formed in the substrate layer; a first conductor is formed on the first surface of the metal layer, and a second conductor is formed on the second surface of the metal layer, the first conductor and the second conductor being connected via a conductor connection hole in the metal layer; the second surface of the metal layer is disposed on the substrate layer, and the substrate through-hole is connected to the second conductor. During operation of the chip unit, a signal access terminal can be disposed within the substrate through-hole and connected to the second conductor, and the signal can be transmitted to the first conductor through the conductor connection hole; the signal access terminal can also be connected to the first conductor, connected to the second conductor through the conductor connection hole, and then output through the substrate through-hole. This configuration allows the signal to pass through the chip unit, thereby manufacturing a 3D chip and realizing its functions. The chip unit provided in the embodiment of the present application realizes signal transmission through the chip unit by sequentially connecting the first conductor part, the conductor connection hole, and the second conductor part from the top to the bottom of the chip unit. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole on the substrate and form a conductor connection hole in the metal layer to realize signal transmission through the chip unit. This greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit, and reducing production costs.

[0031] 2) In the chip unit provided in the embodiments of the present application, leads are connected to the first conductor and / or the second conductor, and the first conductor and the second conductor are connected via conductor connection holes. Thus, the leads enable signal input into the metal layer, signal extraction from the metal layer via the leads, and transmission of external signals through the substrate layer and the metal layer. This allows the chip unit to extract leads from the front and / or back of the chip unit, making the wiring of the chip unit more flexible, particularly reducing the area of ​​the front of the chip unit occupied by the leads, and simplifying the layout and arrangement of the leads. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 is a schematic structural diagram of a chip in an example;

[0034] Figure 2 A schematic structural diagram of a chip unit provided in the first embodiment of the present application;

[0035] Figure 3 A schematic structural diagram of a chip unit provided in the second embodiment of the present application;

[0036] Figure 4 A schematic structural diagram of a chip unit provided in the third embodiment of the present application;

[0037] Figure 5 A schematic structural diagram of a chip unit provided in a fourth embodiment of the present application;

[0038] Figure 6 A schematic structural diagram of a chip unit provided in a fifth embodiment of the present application;

[0039] Figure 7 A schematic structural diagram of a chip unit provided in a sixth embodiment of the present application;

[0040] Figure 8 A schematic structural diagram of a chip unit provided in a seventh embodiment of the present application;

[0041] Figure 9 A schematic structural diagram of a switching circuit of a chip unit provided in one embodiment of the present application;

[0042] Figure 10 A schematic structural diagram of a switching circuit of a chip unit provided in yet another embodiment of the present application;

[0043] Figure 11 A schematic structural diagram of a driving circuit of a chip unit provided in one embodiment of the present application;

[0044] Figure 12 A schematic structural diagram of a conversion circuit of a chip unit provided in one embodiment of the present application;

[0045] Figure 13 A schematic diagram of the structure of an arithmetic circuit of a chip unit provided in one embodiment of the present application;

[0046] Figure 14 A schematic structural diagram of a chip assembly provided in one embodiment of the present application;

[0047] Figure 15 A schematic diagram of the structure of a 3D chip provided in one embodiment of the present application;

[0048] Figure 16 A schematic structural diagram of a chip unit provided for the eighth embodiment of the present application;

[0049] in, Figures 1 to 16 The corresponding relationship between the reference numerals and component names is as follows:

[0050] 100' through silicon via, 200' metal layer, 300' substrate layer;

[0051] 100 chip units; 200 chip components; 3003D chips;

[0052] 1 substrate layer, 2 metal layer, 3 first conductor, 4 second conductor, 5 substrate through hole, 6 conductor connection hole, 7 intra-chip conductor, 8 substrate conductor, 9 functional circuit, 10 lead, 11 metal filling layer, 12 conductor dielectric filling layer, 13 heat dissipation layer, 14 substrate, 15 first chip unit, 16 connection conductor, 17 metal layer through-hole assembly;

[0053] 501 bottom through hole, 502 middle connecting hole;

[0054] 601 first through hole, 602 second through hole, 60N Nth through hole;

[0055] 701 first inner conductor, 702 second inner conductor, 70M Mth inner conductor;

[0056] 901 switching circuit, 9011 first switching module, 9012 second switching module, 9013 third switching module, 9014 fourth switching module;

[0057] 902 drive circuit, 9021 drive module;

[0058] 903 conversion circuit, 9031 parallel-to-serial conversion module;

[0059] 904 operation circuit, 9041 operation module. DETAILED DESCRIPTION

[0060] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0062] like Figure 1 As shown, in some examples, signal transmission through the chip unit can be achieved by opening a through-silicon via 100' (TSV) that penetrates the metal layer 200' and the substrate layer 300'. However, because the TSV 100' needs to pass through the entire chip unit, the diameter and length (or height) of the TSV 100' are relatively large, which leads to high etching requirements, a very large chip area, large resistance and capacitance parasitic parameters, a long manufacturing cycle, and high cost.

[0063] In response to the above problems, the embodiments of the present application provide a chip unit, a chip assembly and a 3D chip, which solve the problems that the chip through-hole structure has high requirements for etching technology, occupies a very large chip area, has large resistance parasitic parameters and capacitance parasitic parameters, has a long manufacturing cycle and high cost.

[0064] like Figure 2 and Figure 3 As shown, according to one aspect of an embodiment of the present application, a chip unit 100 is proposed, comprising: a substrate layer 1 , a metal layer 2 , a metal layer through-hole component 17 , a substrate through-hole 5 and a lead 10 .

[0065] The metal layer through-hole assembly 17 includes a first conductor 3 , a second conductor 4 and a conductor connection hole 6 .

[0066] Among them, there are substrate layer 1; metal layer 2, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; a first conductor 3 is formed on the first surface of the metal layer 2; a second conductor 4 is formed on the second surface of the metal layer 2; a substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 of the metal layer 2; an intra-chip connection hole conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the intra-chip connection hole conductor connection hole 6, so that the signal can be transmitted to the first surface through the substrate layer 1; a lead 10 is connected to the first conductor 3 and / or the second conductor 4. It should be noted here that the metal layer 2 refers to the part above the substrate layer 1; the second surface of the metal layer 2 refers to the side close to the substrate layer 1, and the first surface of the metal layer 2 refers to the side away from the substrate layer 1, and the following parts are the same.

[0067] It should be noted that the metal layer 2 refers to the combination of different metal layers and metal layer connection holes inside the chip, which are arranged on the substrate layer 1. Figures 2 to 8 The first conductor part 3 and the second conductor part 4 as well as all the conductor connection holes 6 and the on-chip conductor parts 7 therebetween.

[0068] like Figure 2 and Figure 3 As shown, in the chip unit 100 provided in the embodiment of the present application, during operation, the signal access end can be set in the substrate through hole 5 and connected to the second conductor part 4, and the signal can be transmitted to the first conductor part 3 through the conductor connection hole 6; based on the same principle, the signal access end can also be connected to the first conductor part 3, connected to the second conductor part 4 through the on-chip conductor connection hole 6, and then the signal is output through the substrate through hole 5. Such a setting can allow the signal to pass through the chip unit 100, which is convenient for the formation and construction of the 3D chip 300, that is, it is convenient to form a 3D chip by stacking the chip units.

[0069] like Figure 2 and Figure 3 As shown, the chip unit 100 provided in the embodiment of the present application realizes that the signal passes through the chip unit 100 by sequentially connecting the first conductor part 3, the intra-chip conductor connection hole 6, and the second conductor part 4 from the top to the bottom of the chip unit 100. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole 5 on the substrate and realize the intra-chip conductor connection hole 6 in the metal layer through hole 2, which greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer through hole 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit 100, and reducing the production cost.

[0070] In some examples, such as Figure 16 As shown, there can be multiple conductor connection holes 6. Figure 3 The middle dots represent the conductor connection holes that are partially omitted. Figure 3 The middle conductor connection hole 6 includes a first through hole 601 , a second through hole 602 , and an Nth through hole 60N. The first conductor 3 is connected to the second conductor 4 through the first through hole 601 , the second through hole 602 , and the Nth through hole 60N in sequence.

[0071] In some examples, the chip unit 100 may be a component composed of multiple planar chips, or may be a single planar chip.

[0072] In some examples, the first conductor 3 may be a metal wire or a metal surface formed on the first surface of the metal layer 2 ; the second conductor 4 may be a metal wire or a metal surface formed on the second surface of the metal layer 2 .

[0073] In some examples, the conductor connection hole 6 may include a through hole and a connection column, wherein the through hole is opened in the metal layer 2 and the connection column is a metal column filled in the through hole. The first conductor 3 and the second conductor 4 can be connected by the metal column to achieve signal transmission.

[0074] In some examples, it is understood that the thickness of the substrate layer 1 is generally greater than the thickness of the metal layer 2. Figures 2 to 4 and Figures 10 to 14 The thickness of the middle metal layer 2 is greater than that of the substrate layer 1 in order to clearly show the internal structure of the metal layer 2 .

[0075] In some examples, by setting the first conductor 3 and the second conductor 4 in the metal layer 2, a circuit can be set in the metal layer 2, the circuit can be connected to the first conductor 3 and the second conductor 4, and a signal can be transmitted to the circuit through the first conductor 3 and the second conductor 4. The circuit can further process the signal, making the circuit layout in the metal layer 2 more flexible.

[0076] like Figure 2 and Figure 3As shown, in the chip unit 100 provided in the embodiment of the present application, the leads 10 are connected to the first conductor 3 and / or the second conductor 4, and the first conductor 3 and the second conductor 4 are connected via the conductor connection hole 6. In this way, the leads 10 are used to input signals into the metal layer 2, to lead signals from the metal layer 2 via the leads 10, and to transmit external signals through the substrate layer 1 and the metal layer 2. The chip unit 100 can lead out the leads 10 via the front surface of the chip unit 100 and / or the back surface of the chip unit 100, making the wiring method of the chip unit 100 more flexible, especially reducing the area of ​​the front surface of the chip unit 100 occupied by the leads 10, saving the area of ​​the metal layer 2 on the front surface of the chip unit 100, and making the layout and arrangement of the leads 10 simpler.

[0077] The front side of the chip unit 100 refers to the first surface of the metal layer 2 , and the back side of the chip unit 100 refers to the side of the substrate layer 1 facing away from the second surface.

[0078] like Figure 2 and Figure 3 As shown, in some examples, the chip unit 100 further includes: a metal filling layer 11 disposed on the substrate through hole 5 and / or the first conductor 3 , and the lead 10 is connected to the metal filling layer 11 .

[0079] like Figure 2 and Figure 3 As shown, in this embodiment, a metal filling layer 11 is further included. The arrangement of the metal filling layer 11 facilitates the arrangement of the lead 10 and makes the fixation of the lead 10 more stable.

[0080] In some examples, when the lead 10 is connected to the metal filling layer 11 , the lead 10 and the metal filling layer 11 constitute a pad structure.

[0081] It can be understood that, in the chip unit 100 provided in the embodiment of the present application, since the leads 10 can be led out from both the front and back sides of the chip unit 100, the layout of the leads 10 can be performed based on the different types of the leads 10, for example, the data signal can be led out from the first conductor 3; the command signal can be led out from the second conductor 4.

[0082] In some examples, the chip unit 100 also includes: a substrate conductor part 8, which is arranged in the substrate layer 1; the substrate through hole 5 includes a bottom through hole 501 and an intermediate connecting hole 502, the bottom through hole 501 is opened at the bottom of the substrate layer 1 and is connected to the substrate conductor part 8, the intermediate connecting hole 502 is located between the substrate conductor part 8 and the second conductor part 4, and the substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connecting hole 502.

[0083] In some examples, the lead 10 is connected to the second conductor 4 through the substrate conductor 8 ; and / or the lead 10 is connected to the first conductor 3 .

[0084] like Figure 4 and Figure 5 As shown, the substrate conductor 8 is disposed in the substrate layer 1. The substrate through-hole 5 includes a bottom through-hole 501 and a middle connecting hole 502.

[0085] like Figure 4 and Figure 5 As shown, during the operation of the chip unit 100, the input end of the signal can be set in the bottom through hole 501 and connected to the substrate conductor part 8, the substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connection hole 502, and the second conductor part 4 is connected to the first conductor part 3; the input end of the signal can also be connected to the first conductor part 3, the first conductor part 3 is connected to the second conductor part 4, and the second conductor part 4 is then connected to the substrate conductor part 8 through the intermediate connection hole 502. This arrangement allows the signal to pass through the chip unit 100, facilitating the formation and construction of the 3D chip 300.

[0086] In some examples, the middle connection hole 502 is processed along the direction of the first surface toward the substrate layer 1.

[0087] like Figure 4 and Figure 5 As shown, the substrate conductor 8 is arranged in the substrate, dividing the substrate through hole 5 into a bottom through hole 501 and an intermediate connection hole 502. The intermediate connection hole 502 is processed along the first surface toward the substrate layer 1 to facilitate the opening of the intermediate connection hole 502. Figure 2 or Figure 3 The substrate through hole 5 can reduce the length and diameter of the substrate through hole 5, thereby reducing the difficulty of the etching process, reducing the area of ​​the metal layer 2 chip occupied (the plane area of ​​the chip), reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit, and reducing the production cost.

[0088] It should be noted that, in practice, the first conductor 3 , the second conductor 4 and the multiple on-chip conductors 7 are different metal layers in the chip, and the conductor connection holes 6 are connection through holes between different metal layers.

[0089] It is understood that in the entire chip unit 100, the thickness of the substrate is usually very large, so the height of the substrate through-hole is much greater than the height of the conductor connection hole 6. By adding a buried metal layer (i.e., the substrate conductor 8), the height of the bottom through-hole 501 can be greatly reduced.

[0090] like Figure 4 and Figure 5As shown, in this embodiment, the substrate layer 1 typically needs to be thinned before perforation. In this embodiment, by providing the substrate conductor 8, the substrate layer 1 does not need to be thinned very much, and even the substrate interface can be thinned to achieve the bottom through-hole 501. Furthermore, because the bottom through-hole 501 does not need to pass through the entire substrate layer 1, perforation time is shortened, costs are reduced, and the yield and reliability of the perforation are also improved.

[0091] like Figure 4 and Figure 5 As shown, in this embodiment, the substrate through hole 5 is divided into a bottom through hole 501 and an intermediate connection hole 502 by the substrate conductor 8, which further reduces the depth of the bottom through hole 501 and facilitates the opening of the bottom through hole 501.

[0092] like Figure 4 and Figure 5 As shown, in this embodiment, when the lead 10 is led out through the back surface of the chip unit 100, the lead 10 can be connected to the substrate conductor 8, and the substrate conductor 8 is connected to the second conductor 4 through the middle connection hole 502. In this way, it is possible to input signals into the metal layer 2, lead signals from the metal layer 2 through the lead 10, and transmit external signals through the substrate layer 1 and the metal layer 2. This allows the chip unit 100 to lead out the lead 10 through the front surface of the chip unit 100 and / or the back surface of the chip unit 100.

[0093] In some examples, the middle connection hole 502 may be a connection hole formed by an etching process.

[0094] In some examples, the middle connection hole 502 may include a through hole and a connection column disposed in the through hole, wherein the connection column is a metal column. The second conductor 4 and the substrate conductor 8 may be connected via the metal column.

[0095] like Figure 6 and Figure 7 As shown, in some examples, the chip unit 100 further includes: a conductor dielectric filling layer 12 filled in the substrate through hole 5 .

[0096] like Figure 6 and Figure 7 As shown, in this embodiment, a conductive dielectric filling layer 12 is further included. The heat dissipation dielectric is filled in the substrate through-hole 5. The heat generated in the metal layer 2 can be transferred to the heat dissipation dielectric layer, and the heat can be dispersed through the heat dissipation dielectric layer. In this way, the chip unit 100 can be cooled and cooled, thereby improving the performance of the chip unit 100.

[0097] like Figure 6 and Figure 7As shown, in some examples, the substrate through hole 5 includes a closed end and a flared end, and the closed end is located on one side of the second conductor part 4. Such a setting can, on the one hand, improve the heat dissipation effect of the conductor dielectric filling layer 12 and facilitate the filling of the conductor dielectric filling layer 12; on the other hand, it is convenient for the lead 10 to be connected to the second conductor part 4 or the substrate conductor part 8.

[0098] like Figure 6 and Figure 7 As shown, in some examples, the chip unit 100 further includes: a heat dissipation layer 13 covering the conductive dielectric filling layer 12 .

[0099] like Figure 6 and Figure 7 As shown, in this embodiment, a heat dissipation layer 13 is further included. By covering the heat dissipation medium layer with the heat dissipation layer 13, the heat dissipation effect can be further improved.

[0100] like Figure 6 and Figure 7 As shown, in some examples, part of the heat dissipation layer 13 is covered on the substrate layer 1, so that the cross-sectional area of ​​the heat dissipation layer 13 is larger than the cross-sectional area of ​​the conductor dielectric filling layer 12, which can further improve the heat dissipation effect and facilitate the connection of the heat dissipation layer 13 to other fixing parts. In some examples, the fixing part can be a substrate 14.

[0101] In some examples, the chip unit 100 further includes: a conductor dielectric filling layer 12 made of a metal material and / or a heat dissipation layer 13 made of a metal material.

[0102] In this embodiment, the conductor dielectric filling layer 12 is made of metal material, so that the conductor dielectric filling layer 12 has the heat dissipation effect while taking into account the signal transmission ability. The lead 10 can be connected to the conductor dielectric filling layer 12, or the lead 10 can be omitted and the conductor dielectric filling layer 12 can be directly used as a signal transmission port.

[0103] In this embodiment, the heat dissipation layer 13 is made of metal material, so that the heat dissipation layer 13 has the heat dissipation effect while taking into account the signal transmission ability. The lead 10 can be connected to the conductor medium filling layer 12, or the lead 10 can be omitted and the heat dissipation layer 13 can be directly used as the signal transmission port.

[0104] In some examples, the chip unit 100 also includes: an on-chip conductor part 7, which is arranged in the metal layer through-hole 2 and is located between the first conductor part 3 and the second conductor part 4; wherein, there are multiple on-chip conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple on-chip conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple on-chip conductor connection holes 6.

[0105] This embodiment further includes an intra-chip conductor 7, disposed between the first conductor 3 and the second conductor 4. The second conductor 4 is connected to the intra-chip conductor 7 via an intra-chip conductor connection via 6, and the intra-chip conductor 7 is connected to the first conductor 3 via the intra-chip conductor connection via 6. During operation of the chip unit 100, an external signal input terminal can be disposed within the substrate through-hole 5 and transmitted to the second conductor 4. The second conductor 4 is then connected to the intra-chip conductor 7 and then connected to the first conductor 3. An external signal input terminal can also be connected to the first conductor 3 and then transmitted to the second conductor 4 via the intra-chip conductor connection via 6 and the intra-chip conductor 7. This configuration allows signals to pass through the chip unit 100, facilitating the formation and construction of the 3D chip 300.

[0106] In this embodiment, an intra-chip conductor part 7 is further included, and the intra-chip conductor part 7 is arranged between the first conductor part 3 and the second conductor part 4, so that the first conductor part 3 and the second conductor part 4 can be connected to the intra-chip conductor part 7 through multiple intra-chip conductor connection holes 6, further shortening the length of the intra-chip conductor connection hole 6, and reducing the diameter of the intra-chip conductor connection hole 6, further reducing the difficulty of the etching process, reducing the area occupied by the metal layer through-hole 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit 100, and reducing the production cost.

[0107] In some examples, such as Figure 16 As shown, there may be multiple conductor connection holes 6 and multiple conductor parts 7 on the chip. Figure 3 The middle dots represent the conductor connection holes and conductor parts on the chip that are partially omitted. Figure 3 The conductor connection holes 6 include a first through-hole 601, a second through-hole 602, and finally an Nth through-hole 60N. The on-chip conductive component 7 includes a first on-chip conductive component 701, a second on-chip conductive component 702, and finally an Mth on-chip conductive component 70M. One side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 4 via the first through-hole 601, and the other side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 702 via the second through-hole 602. This arrangement is repeated, with adjacent on-chip conductive components connected via the conductor connection holes, until the Mth on-chip conductive component 70M is connected to the first conductive component 3 via the Nth through-hole 60N. This connects the first conductive component 3 to the second conductive component 4, enabling signal transmission through the chip unit 100. M = N-1.

[0108] In some examples, the intra-chip conductor connection hole 6 can include a through-hole and a connection pillar. The through-hole is provided in the metal layer through-hole 2, and the connection pillar is a metal pillar filled in the through-hole. The first conductor 3 and the intra-chip conductor 7 can be connected via the metal pillar; the second conductor 4 and the intra-chip conductor 7 can be connected via the metal pillar; and adjacent intra-chip conductors 7 can be connected via the metal pillar.

[0109] In some examples, the on-chip conductor 7 may be a metal line or a metal surface formed in the metal layer through-hole 2 .

[0110] It is understandable that Figures 2 to 8 The three dots in FIG. 1 represent omitted on-chip conductor members 7 and / or on-chip conductor connection holes 6 .

[0111] In some examples, there are multiple on-chip conductor parts 7 , and the multiple on-chip conductor parts 7 are spaced apart between the first conductor part 3 and the second conductor part 4 . Adjacent on-chip conductor parts 7 are connected through some of the multiple on-chip conductor connection holes 6 .

[0112] In this embodiment, further, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are spaced apart between the first conductor part 3 and the second conductor part 4. The second conductor part 4 is connected to the first conductor part 3 through the multiple on-chip conductor parts 7 and the multiple on-chip conductor connection holes 6, which can further shorten the length and diameter of each on-chip conductor connection hole 6, further reduce the difficulty of the etching process, reduce the area occupied by the metal layer through-hole 2, reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the chip unit 100, and reduce the production cost.

[0113] In some examples, a conductor connection hole 6 is provided between two adjacent on-chip conductor members 7 .

[0114] like Figure 2 and Figure 3 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit; on the other hand, the two adjacent on-chip conductor parts 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0115] In some examples, a conductor connection hole 6 is provided between the first conductor 3 and the adjacent on-chip conductor 7 .

[0116] like Figure 2 and Figure 3 As shown, the first conductor part 3 is connected to the on-chip conductor part 7 adjacent to the first conductor part 3 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit; on the other hand, the first conductor part 3 and the on-chip conductor part 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0117] In some examples, a conductor connection hole 6 is provided between the second conductor 4 and the adjacent on-chip conductor 7 .

[0118] like Figure 2 and Figure 3 As shown, the second conductor part 4 is connected to the on-chip conductor part 7 adjacent to the second conductor part 4 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit; on the other hand, the second conductor part 4 and the on-chip conductor part 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0119] In some examples, the difference between the number of conductor connection holes 6 and the number of conductor connection members is 1.

[0120] like Figures 2 to 4 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7, a conductor connection hole 6 is provided between the first conductor part 3 and the on-chip conductor part 7, and a conductor connection hole 6 is provided between the second conductor part 4 and the on-chip conductor part 7. The difference between the number of conductor connection holes 6 and the number of conductor connectors is 1, so that the metal layer perforation component 17 can be arranged along the height direction of the metal layer 2, which can reduce the space occupied by the metal layer perforation component 17, further reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the chip unit, and reduce the production cost.

[0121] In some examples, the cross-section of the substrate through hole 5 along the substrate height direction is a polygon, and the length of the first side of the polygon close to the metal layer 2 is shorter than the length of the second long side of the polygon away from the metal layer 2 .

[0122] like Figure 13 As shown, the cross-section of the substrate through hole 5 is a polygon, and the length of the first side of the polygon close to the metal layer 2 is smaller than the length of the second long side of the polygon away from the metal layer 2, so that one end of the substrate through hole 5 is a flared end and the other end is a closed end. The closed end is arranged toward the side of the metal layer 2, which is convenient for opening the substrate through hole 5 and filling the conductor dielectric filling layer 12 into the substrate through hole 5. It can be understood that the conductor dielectric filling can dissipate heat for the chip unit.

[0123] In some examples, the cross-section of the through substrate via 5 along the substrate height direction is trapezoidal.

[0124] like Figures 2 to 4 As shown, the cross section of the substrate through hole 5 is trapezoidal, which further facilitates the opening of the substrate through hole 5 .

[0125] In some examples, the short side of the trapezoid is located on a side of the substrate layer 1 close to the metal layer 2 , and the long side of the trapezoid is located on a side of the substrate layer 1 far from the metal layer 2 .

[0126] like Figure 13As shown, the short side of the trapezoid is located on the side of the substrate layer 1 close to the metal layer 2, and the long side of the trapezoid is located on the side of the substrate layer 1 away from the metal layer 2. When the conductor dielectric filling layer 12 is filled into the substrate through hole 5, the flared end is set away from the side of the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield rate of the chip unit.

[0127] In some examples, the substrate through hole 5 is truncated cone-shaped, which facilitates the excavation of the substrate through hole 5 and makes the anisotropy of the substrate through hole 5 substantially uniform, thereby further improving the performance of the chip unit.

[0128] In some examples, the truncated cone includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer 1 close to the metal layer 2, and the second end face is located on the side of the substrate layer 1 away from the metal layer 2.

[0129] like Figure 2 and Figure 3 As shown, the truncated cone shape includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, so that the first end face is a closed end and the second end face is a flared end, and the closed end of the truncated cone is arranged toward the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield rate of the chip unit.

[0130] In some examples, the conductor connection hole 6 is columnar.

[0131] like Figure 2 、 Figure 3 and Figures 10 to 15 As shown, the conductor connection hole 6 is columnar. On the one hand, it is convenient for the production and processing of the conductor connection hole 6. On the other hand, the conductor connection hole 6 serves as a carrier for connecting two adjacent on-chip conductor parts 7, the on-chip conductor part 7 and the first conductor part 3, and the on-chip conductor part 7 and the second conductor part 4. The columnar design can make the signal transmission capabilities at both ends of the conductor connection hole 6 consistent, thereby ensuring the stability of the chip unit signal transmission.

[0132] like Figure 8 As shown, in some examples, the chip unit 100 further includes: a functional circuit 9 , which is connected to at least one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 .

[0133] like Figure 8As shown, in this embodiment, a functional circuit 9 is further included, and the functional circuit 9 can be connected to at least one of the first conductor 3, the second conductor 4, and the on-chip conductor 7, so as to facilitate access to the functional circuit 9. At the same time, a signal from outside the chip unit 100 can be transmitted to any one of the first conductor 3, the second conductor 4, and the on-chip conductor 7 through the first conductor 3, the second conductor 4, or the on-chip conductor 7, so that the functional module in the chip unit 100 can process the external signal (the external signal of the chip unit 100), making the signal processing of the chip unit 100 more flexible and improving the applicability of the chip unit 100.

[0134] In some examples, it is understandable that, when the chip unit 100 includes the substrate conductor 8 , some devices in the functional circuit 9 may also be connected to or located on the substrate conductor 8 .

[0135] In some examples, the signal transmitted to the functional circuit 9 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7 can be an internal signal within the metal layer 2, or an external signal from outside the chip unit. The external signal can be introduced into the functional circuit 9 through the metal layer through the first conductor 3 and / or the second conductor 4 and / or the on-chip conductor 7.

[0136] In some examples, when the signal input and output of the functional circuit 9 are connected to the same one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 , the access points of the signal input and output of the functional circuit 9 are different.

[0137] In this embodiment, the signal input end and the signal output end of the functional circuit 9 can be connected to the same one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, so that more functional circuits 9 can be connected through the first conductor 3, the second conductor 4 and the on-chip conductor 7, which can facilitate signal processing of the functional circuit 9.

[0138] In this embodiment, when the signal input end and the signal output end of the functional circuit 9 are connected to the same one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, the access points of the signal input end and the signal output end of the functional circuit 9 are different, which facilitates the input and output of signals, can prevent the input signal and the output signal from interfering with each other, and further improves the signal processing or transmission performance of the metal layer 2.

[0139] like Figure 13 As shown, in some examples, the chip unit 100 further includes: an internal signal input terminal connected to the functional circuit 9.

[0140] like Figure 13As shown, in this embodiment, an internal signal input terminal is further included. Through the setting of the internal signal input terminal, the signal inside the metal layer 2 can be transmitted to the functional circuit 9, so that the functional circuit 9 can simultaneously process the signal outside the metal layer 2 and the internal signal, further improving the processing capability of the functional circuit 9.

[0141] like Figure 2 、 Figure 9 and Figure 10 As shown, in some examples, the functional circuit 9 includes a switching circuit 901, and the switching circuit 901 includes: at least two parallel switching modules, the signal input end and / or the signal output end of each switching module is connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7; a first control switch, each switching module is provided with at least one first control switch, and the first control switch is used to control the working state of the signal input end or the signal output end of the switching module.

[0142] In some examples, each switching module may be connected to a signal input terminal, and each switching module may be connected to a signal output terminal. Such a configuration can ensure the independence of the signal input.

[0143] In some examples, multiple switching modules or some of the switching modules in multiple switching modules can share a signal input end; multiple switching modules or some of the switching modules in multiple switching modules can also share a signal output end. Such a setting can reduce access points and facilitate the layout of the switching circuit.

[0144] like Figure 2 、 Figure 9 and Figure 10 As shown, in this embodiment, the functional circuit 9 includes a switching circuit 901. The external signal is transmitted to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7 through the first conductor 3, the second conductor 4 and the on-chip conductor 7, and then the signal enters the switching circuit 901. The target switching module can be selected through the first control switch to output the signal, making the signal processing or transmission of the chip unit 100 more flexible, thereby improving the applicability of the chip unit 100.

[0145] In some examples, multiple switching modules are connected to the same signal input terminal; and / or multiple switching modules are connected to the same signal output terminal.

[0146] like Figure 2 、 Figure 9 and Figure 10 As shown, in this embodiment, multiple switching modules are connected to the same signal input terminal. During use, the signal input terminal can be connected to only one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, which facilitates the access of the switching circuit 901.

[0147] like Figure 2 、 Figure 9 and Figure 10 As shown, in this embodiment, multiple switching modules are connected to the same signal output end. During use, the signal output end can be connected to only one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, so as to facilitate the output of the signal of the switching circuit 901.

[0148] like Figure 2 、 Figure 9 and Figure 10 As shown, in this embodiment, multiple switching modules are connected to the same signal input terminal and / or multiple switching modules are connected to the same signal output terminal, which can reduce the access points of the switching circuit 901 and facilitate the setting of the switching circuit 901. At the same time, more circuits can be arranged through the first conductor 3, the second conductor 4 and the on-chip conductor 7, making the layout of the chip unit 100 more flexible and improving the applicability of the chip unit 100.

[0149] like Figure 2 and Figure 11 As shown, in some examples, the functional circuit 9 includes a driving circuit 902, and the driving circuit 902 includes: a driving module 9021, and the signal input end and / or the signal output end of the driving module 9021 are connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7.

[0150] like Figure 2 and Figure 11 As shown, in this embodiment, the functional circuit 9 includes a driving circuit 902. Considering that the signal may be attenuated during the transmission process, the signal is connected to the driving module 9021 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After the driving module 9021 performs driving enhancement, the signal is output through the output end of the driving signal, which can ensure the smoothness of signal transmission and further improve the performance of the chip unit 100.

[0151] It should be noted that the driving module 9021 in the figure is two inverters connected in series. In practice, the number of inverters can be an odd number, such as one inverter (the signal will be inverted); or an even number, such as two inverters here.

[0152] like Figure 2 and Figure 12 As shown, in some examples, the functional circuit 9 includes a conversion circuit 903, and the conversion circuit 903 includes: a conversion module, and the signal input end and / or signal output end of the conversion module are connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7.

[0153] like Figure 2 and Figure 12 As shown, in this embodiment, the signal can be transmitted to the conversion circuit 903 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. The signal is converted by the conversion circuit 903 and then output through the conversion module, thereby realizing signal processing.

[0154] In some examples, the conversion module is a serial-to-parallel conversion module or a parallel-to-serial conversion module 9031 (wherein, Figure 12 The parallel-to-serial conversion module is used as an example).

[0155] In this embodiment, the conversion module can be a serial-parallel conversion module. The signal is transmitted to the series signal end through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After passing through the serial-parallel conversion module, the signal is output through the parallel signal port model, which can improve the efficiency of signal transmission.

[0156] like Figure 2 and Figure 12 As shown, in this embodiment, the conversion module can also be a parallel-to-serial conversion module 9031. The signal is transmitted to the parallel signal end through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After passing through the parallel-to-serial conversion module 9031, the signal is output through the serial signal end. After multiple signals are converted into parallel-to-serial, the signal transmission line can be reduced, thereby improving the signal transmission efficiency.

[0157] In some examples, the functional circuit 9 includes an operation circuit 904 , which includes: an operation module 9041 , wherein the signal input terminal and / or the signal output terminal of the operation module 9041 are connected to at least one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 .

[0158] like Figure 13 As shown, in this embodiment, the functional circuit 9 further includes an arithmetic circuit 904. Signals are transmitted to an arithmetic module 9041 via at least one of the first conductor 3, the second conductor 4, and the on-chip conductor 7. After the signals are arithmetic, they are output via the signal output terminal. This allows the arithmetic circuit 904 to process both external and internal signals of the chip unit 100, improving signal flexibility.

[0159] In some examples, the system further includes: a second control switch connected to the operation module 9041 , configured to control the working states of the signal input and signal output terminals of the operation module 9041 .

[0160] like Figure 2 and Figure 13As shown, in this embodiment, a second control switch is further included. Through the setting of the second control switch, the working status of the signal input end and the signal output end of the operation module 9041 can be controlled, which is used to control the input and output of the signal, making the control method of the operation module 9041 more flexible.

[0161] like Figure 14 As shown, according to the second aspect of the embodiment of the present application, a chip component 200 is provided, including: a chip unit 100 of any of the above embodiments; the lead 10 of the chip unit 100 is connected to the second conductor 4, and the chip unit 100 is connected to the substrate 14 through the lead 10.

[0162] The chip assembly 200 of the embodiment of the present application includes the chip unit 100 of any of the above embodiments, and therefore has all the beneficial effects of the chip unit 100 of any of the embodiments of the present invention, which will not be described in detail here.

[0163] The chip assembly 200 provided herein can directly lead out leads 10 through the bottom of the chip unit 100. The leads 10 are further used to connect to the substrate 14, which facilitates the layout of the leads 10 of the chip assembly 200 and reduces the area occupied by the leads 10 on the front of the chip assembly 200. The front of the chip assembly 200 refers to the first surface of the chip unit 100.

[0164] In some examples, the substrate through-hole 5 of the chip unit 100 is filled with a heat dissipation medium layer, and the chip unit 100 is connected to the base plate 14 through the heat dissipation medium layer.

[0165] In this embodiment, the chip unit 100 may be connected to the substrate 14 via a heat dissipation medium layer, which may further improve the heat dissipation effect of the chip assembly 200 .

[0166] In some examples, it can be understood that, in the case where the heat dissipation medium layer is covered with a heat dissipation layer 13 , the chip unit 100 can be connected to the substrate 14 through the heat dissipation layer 13 .

[0167] like Figure 15 As shown, according to a third aspect of the embodiments of the present application, a 3D chip 300 is provided, comprising: at least two stacked chip units 100 according to any of the above embodiments; at least two chip units 100 including a first chip unit 15, wherein, when the substrate layer 1 of the first chip unit 15 is disposed on a base plate 14, one end of the lead 10 of the first chip unit 15 is connected to the second conductor 4 of the first chip unit 15, and the other end is connected to the base plate 14. Signals between the two chip units 100 are connected via a connecting conductor 16 between the chip units.

[0168] The 3D chip 300 of the embodiment of the present application includes the chip unit 100 of any of the above embodiments, and therefore has all the beneficial effects of the chip unit 100 of any of the embodiments of the present application, which will not be described in detail here.

[0169] The 3D chip 300 provided in the embodiment of the present application has a first chip unit 15 close to the substrate 14 , and leads 10 are extended through the bottom of the chip unit 100 , so that the arrangement of the leads 10 is more reasonable, reducing the area occupied by the front surface of the 3D chip 300 .

[0170] In some examples, the substrate through hole 5 of the first chip unit 15 is filled with a heat dissipation medium layer. When the substrate layer 1 of the first chip unit 15 is set on the substrate 14, the first chip unit 15 is connected to the substrate 14 through the heat dissipation medium layer.

[0171] In this embodiment, the 3D chip 300 may be connected to the substrate 14 via a heat dissipation dielectric layer, which may further improve the heat dissipation effect of the chip assembly 200 .

[0172] In some examples, it is understandable that, in the case where the heat dissipation medium layer is covered with a heat dissipation layer 13 , the chip unit 100 can be connected to the substrate 14 through the heat dissipation layer 13 . Specific embodiment 1

[0174] like Figure 2 and Figure 3 As shown, an embodiment of the present application provides a chip unit 100 , comprising: a substrate layer 1 , a metal layer 2 , a metal layer through-hole component 17 , a substrate through-hole 5 , an intra-chip conductor 7 and a lead 10 .

[0175] The metal layer through-hole assembly 17 includes a first conductor 3 , a second conductor 4 and a conductor connection hole 6 .

[0176] Among them, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; the first conductor 3 is formed on the first surface of the metal layer 2; the second conductor 4 is formed on the second surface of the metal layer 2; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 of the metal layer 2; the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6; the on-chip conductor 7 is arranged in the metal layer 2, located between the first conductor 3 and the second conductor 4, and the lead 10 is connected to the first conductor 3 and / or the second conductor 4.

[0177] like Figure 2 As shown, the lead 10 is connected to the first conductor 3; Figure 3 As shown, the lead 10 is connected to the second conductor 4 .

[0178] There are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0179] Among them, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are arranged at intervals between the first conductor part 3 and the second conductor part 4. Adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6 so that the signal can be transmitted to the first surface through the substrate layer 1.

[0180] In some examples, the through-substrate via 5 is dug in the substrate layer 1 , and the through-substrate via 5 penetrates the entire substrate to achieve connectivity of the metal layer 2 from the second surface.

[0181] Furthermore, pads may be provided in the first conductor 3 and / or the substrate through-hole 5 for bonding the lead 10 .

[0182] Furthermore, after the substrate layer 1 is dug, a conductor of metal or other material can be filled in to facilitate connection with the second conductor part 4, thereby realizing connection from the first conductor part 3 to the substrate layer 1, that is, the signal can be connected from the front to the back of the chip unit 100, through the entire chip unit 100, where the front of the chip unit 100 refers to the first surface of the metal layer 2, and the back of the chip unit 100 refers to the bottom surface of the substrate layer 1.

[0183] With the chip unit 100 of this embodiment, during the production process, only a perforation of the substrate needs to be added to a conventional planar chip to obtain the chip unit 100 of this embodiment, which is fully compatible with the existing planar chip process.

[0184] In this embodiment, signal conduction is achieved through the first conductor part 3, the second conductor part 4, the intra-chip conductor part 7 and the conductor connection hole 6 of the metal layer 2. The area of ​​the metal layer 2 occupied is very small, the resistance parasitic parameters and the capacitance parasitic parameters are very small, and the upper and lower connections of the chip unit 100 can be achieved, and the upper and lower bonding leads 10 of the chip unit 100 can also be achieved. Specific embodiment 2

[0186] like Figure 4 and Figure 5 As shown, an embodiment of the present application provides a chip unit 100, including: a substrate layer 1, a metal layer 2, a metal layer through-hole component 17, a substrate through-hole 5, an intra-chip conductor 7, a substrate conductor 8 and a lead 10.

[0187] The metal layer through-hole assembly 17 includes a first conductor 3 , a second conductor 4 and a conductor connection hole 6 .

[0188] Among them, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; the first conductor 3 is formed on the first surface of the metal layer 2; the second conductor 4 is formed on the second surface of the metal layer 2; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 of the metal layer 2; the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6; the on-chip conductor 7 is arranged in the metal layer 2, located between the first conductor 3 and the second conductor 4; the substrate conductor 8 is arranged in the substrate layer 1, and the lead 10 is connected to the first conductor 3 and / or the second conductor 4.

[0189] like Figure 4 As shown, the lead 10 is connected to the substrate conductor 8; Figure 5 As shown, the lead 10 is connected to the first conductor 3 .

[0190] There are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0191] Among them, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are arranged at intervals between the first conductor part 3 and the second conductor part 4. Adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6 so that the signal can be transmitted to the first surface through the substrate layer 1.

[0192] Among them, the substrate through hole 5 includes a bottom through hole 501 and an intermediate connecting hole 502. The bottom through hole 501 is opened at the bottom of the substrate and is connected to the substrate conductor part 8. The intermediate connecting hole 502 is located between the substrate conductor part 8 and the second conductor part 4. The substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connecting hole 502; the intermediate connecting hole 502 is processed along the first surface toward the substrate layer 1.

[0193] In some examples, during the preparation process, metal may be embedded in the substrate layer 1 through a buried word line process to form the substrate conductor 8 , which is then connected to the second conductor 4 through the intermediate connection hole 502 .

[0194] In some examples, grooves may be dug on the substrate layer 1 and substrate conductors 8 may be buried in the grooves.

[0195] In some examples, the substrate conductor 8 may be embedded in the front-end process of chip manufacturing.

[0196] It is understandable that in the entire chip unit 100, the thickness of the substrate is usually very large, so the height of the substrate through-hole is much greater than the height of the conductor connection hole 6. By adding a buried metal layer, the height of the bottom through-hole 501 can be greatly reduced.

[0197] In this embodiment, the substrate layer 1 typically requires thinning before perforation. However, by providing the substrate conductor 8 in this embodiment, the substrate layer 1 does not need to be thinned very much, and even bottom via 501 can be processed without thinning. Furthermore, because bottom via 501 does not need to pass through the entire substrate layer 1, perforation time is reduced, resulting in lower costs and a higher perforation yield and reliability. Specific embodiment 3

[0199] like Figure 8 As shown, an embodiment of the present application provides a chip unit 100, including: a substrate layer 1, a metal layer 2, a metal layer through-hole component 17, a substrate through-hole 5, an on-chip conductor 7, a substrate conductor 8, a functional circuit 9 and a lead 10.

[0200] The metal layer through-hole assembly 17 includes a first conductor 3 , a second conductor 4 and a conductor connection hole 6 .

[0201] Among them, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; the first conductor 3 is formed on the first surface of the metal layer 2; the second conductor 4 is formed on the second surface of the metal layer 2; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 of the metal layer 2; the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6; the on-chip conductor 7 is arranged in the metal layer 2, located between the first conductor 3 and the second conductor 4; the substrate conductor 8 is arranged in the substrate layer 1; the functional circuit 9 is connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, and the lead 10 is connected to the first conductor 3 and / or the second conductor 4.

[0202] like Figure 8 As shown, the lead 10 is connected to the second conductor 4 and the first conductor 3 through the substrate conductor 8 .

[0203] There are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0204] Among them, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are arranged at intervals between the first conductor part 3 and the second conductor part 4. Adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6 so that the signal can be transmitted to the first surface through the substrate layer 1.

[0205] Among them, the substrate through hole 5 includes a bottom through hole 501 and an intermediate connecting hole 502. The bottom through hole 501 is opened at the bottom of the substrate and is connected to the substrate conductor part 8. The intermediate connecting hole 502 is located between the substrate conductor part 8 and the second conductor part 4. The substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connecting hole 502; the intermediate connecting hole 502 is processed along the first surface toward the substrate layer 1.

[0206] In some examples, the functional circuit 9 may include one or more of a switching circuit 901 , a driving circuit 902 , a conversion circuit 903 , and an operation circuit 904 .

[0207] In this embodiment, considering that the first conductor 3 , the second conductor 4 and the on-chip conductor 7 are connected through the conductor connection hole 6 , the first conductor 3 , the second conductor 4 and the on-chip conductor 7 can be used to connect the functional circuit 9 inside the chip unit 100 .

[0208] like Figure 8 As shown, the functional circuit 9 is connected via the on-chip conductor 7 within the chip, the signal is input to the functional circuit 9 through the on-chip conductor 7, and the output of the functional circuit 9 transmits the signal to other on-chip conductors 7. It is understandable that the input and output of the functional circuit 9 can be connected to the same on-chip conductor 7.

[0209] Furthermore, the switching circuit 901 is used to output the signal that passes through the chip unit 100 after function switching.

[0210] like Figure 9 As shown, the switching circuit 901 includes a first switching module 9011 and a second switching module 9012 arranged in parallel. The first control switch includes a first switch K11, a second switch K12, a third switch K13, and a fourth switch K14. The first switch K11 is provided on the signal input side of the first switching module 9011, and the second switch K12 is provided on the signal output side of the first switching module 9011. The third switch K13 is provided on the signal input side of the second switching module 9012, and the fourth switch K14 is provided on the signal output side of the first switching module 9011. The first switching module 9011 and the second switching module 9012 share a signal input and a signal output. During operation, signal A is selected by the first control switch, processed by the first switching module 9011 or the second switching module 9012, and then output as signal B after selection by the first control switch.

[0211] like Figure 10 As shown, the switching circuit 901 includes a third switching module 9013 and a fourth switching module 9014 arranged in parallel. The first control switch includes a fifth switch K15, a sixth switch K16, a seventh switch K17, and an eighth switch K18. The fifth switch K15 is provided on the signal input side of the third switching module 9013, and the sixth switch K16 is provided on the signal output side of the third switching module 9013. The seventh switch K17 is provided on the signal input side of the fourth switching module 9014, and the eighth switch K18 is provided on the signal output side of the fourth switching module 9014. The first switching module 9011 and the second switching module 9012 each have a signal input terminal, and the first switching module 9011 and the second switching module 9012 share a signal output terminal. During operation, signal C is processed by the third switching module 9013 after being selected by the first control switch, and / or signal D is processed by the fourth switching module 9014 after being selected by the first control switch. The processed signal E is output via the signal output terminal after passing through the first control switch.

[0212] By configuring the switching circuit 901 , the input perforation can be functionally processed, thereby improving the flexibility of the signal and providing more options for signal transmission and processing.

[0213] like Figure 11 As shown, the signal F is driven by the driving module 9021 and then outputted as the signal G, which can increase the driving capability of the signal.

[0214] like Figure 12 As shown, Figure 8 The dots between H2 and Hn indicate that some input signals have been omitted. The input signals are parallel signals H1, H2, ..., and Hn. After passing through the parallel-to-serial conversion module, they are converted into a serial signal I for output. Similarly, a serial-to-parallel conversion method can also be employed. In this method, the input signal is serial signal I. After passing through the serial-to-parallel conversion module, it is converted into parallel signals H1, H2, ..., and Hn for output. The configuration of conversion circuit 903 allows for parallel-to-serial conversion of multiple signals, reducing signal transmission lines and improving signal transmission efficiency. Furthermore, it increases signal transmission bandwidth.

[0215] like Figure 13As shown, the second control switch includes a ninth switch K21, a tenth switch K22, and an eleventh switch K23. The external input signal L is input to the computation module 9041 via the ninth switch K21; the internal signal is input to the computation module 9041 via the tenth switch K22; and after processing by the computation module 9041, it is output as the output signal M via the eleventh switch K23. It is understood that the second control switch can be added as needed. The configuration of the computation circuit 904 allows both the external input signal and the internal signal to be processed and output, improving signal flexibility and adding computational capabilities with internal signals.

[0216] In some examples, the operation module 9041 can be a module with data operation or other processing functions.

[0217] In the description of the present invention, the term "plurality" refers to two or more than two. Unless otherwise expressly defined, the orientations or positional relationships indicated by the terms "upper" and "lower" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention. The terms "connect," "install," and "fix" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0218] In the description of the present invention, the terms "one embodiment," "some embodiments," "specific embodiments," etc., mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0219] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip unit, characterized in that: include: substrate layer; a metal layer, the metal layer comprising a first surface and a second surface opposite to each other, the second surface of the metal layer being disposed on the substrate layer; a metal layer through-hole component, disposed in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor, and a conductor connection hole, wherein the first conductor is formed on the first surface of the metal layer, the second conductor is formed on the second surface of the metal layer, the conductor connection hole is formed in the metal layer, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted through the substrate layer to the first surface; a substrate through hole, provided on the substrate layer and connected to the second conductor, wherein the substrate through hole is truncated cone-shaped; The truncated cone includes a first end surface and a second end surface, wherein the diameter of the first end surface is smaller than the diameter of the second end surface, the first end surface is located on a side of the substrate layer close to the metal layer, and the second end surface is located on a side of the substrate layer far from the metal layer; a lead connected to the first conductor and / or the second conductor; A substrate conductor member, disposed in the substrate layer; The substrate through hole includes a bottom through hole and an intermediate connection hole, wherein the bottom through hole is opened at the bottom of the substrate layer and is connected to the substrate conductor member, and the intermediate connection hole is located between the substrate conductor member and the second conductor member, and the substrate conductor member is connected to the second conductor member through the intermediate connection hole; an on-chip conductor, disposed in the metal layer and located between the first conductor and the second conductor; There are a plurality of conductor connection holes, the second conductor member is connected to the on-chip conductor member through some of the plurality of conductor connection holes, the on-chip conductor member is connected to the first conductor member through some of the plurality of conductor connection holes, and the difference between the number of the conductor connection holes and the number of the on-chip conductor members is 1; A conductor dielectric filling layer is filled in the substrate through hole; The heat dissipation layer covers the conductive dielectric filling layer.

2. The chip unit according to claim 1, characterized in that: Also includes: A metal filling layer is provided on the substrate through hole and / or the first conductor, and the lead is connected to the metal filling layer.

3. The chip unit according to claim 2, characterized in that: The lead is connected to the second conductor through the substrate conductor.

4. The chip unit according to claim 1, characterized in that: There are a plurality of on-chip conductor parts, and the plurality of on-chip conductor parts are spaced apart and arranged between the first conductor part and the second conductor part. Adjacent on-chip conductor parts are connected through some of the plurality of conductor connection holes.

5. A chip assembly, characterized in that: include: The chip unit according to any one of claims 1 to 4; The leads of the chip unit are connected to the second conductor, and the chip unit is connected to the substrate through the leads.

6. A 3D chip, characterized in that: include: At least two stacked chip units according to any one of claims 1 to 4; The at least two chip units include a first chip unit. When the substrate layer of the first chip unit is arranged on a base plate, one end of a lead of the first chip unit is connected to the second conductor of the first chip unit, and the other end is connected to the base plate.

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