Integrated circuit, packaging method of integrated circuit, and electronic device

Abstract

Embodiments of the present invention provide an integrated circuit, a packaging method for the integrated circuit, and an electronic device. The integrated circuit includes: a chip pin processing circuit, communication circuits of multiple communication types, an input / output controller, and a port enable controller, which are packaged inside the housing of the integrated circuit; pins packaged outside the housing, and the pins are connected to the chip pin processing circuit; wherein, the port enable controller selectively determines a type of communication port from the communication circuits of the multiple communication types, and the input / output controller selectively cooperates with the port enable controller to control the input / output state of a predetermined port and communicate by conducting communication between the pin and the input / output controller. In this way, according to the communication type actually required by the pins of different integrated circuits, a type of communication port is selectively determined to conduct communication between the corresponding pins and the input / output controller of the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of integrated circuit technology, and in particular, to an integrated circuit, a packaging method for an integrated circuit, and an electronic device. Background Art

[0002] With the development of current integrated circuit manufacturing processes and packaging technologies, new-generation intelligent products have higher requirements for the power consumption and packaging size of chips such as MCUs and MPUs. As the packaging size becomes smaller and smaller, the contradiction between the number of chip pins and the packaging size becomes more prominent.

[0003] For example, currently, when designing and developing the packaging of chips such as MCUs and MPUs, the number and sequence of packaging pins are generally planned according to specific application scenarios. When existing chips expand new applications or develop new markets, the following problems will be faced:

[0004] 1. The peripheral ports led to the packaging pins are not required in the new application;

[0005] 2. One or several other peripheral ports that need to be used are not led to the packaging pins;

[0006] 3. Both situations exist simultaneously.

[0007] In the case where the packaging size requirement is relatively high and the number of packaging pins is limited, expanding new applications or developing new markets generally leads to the re-design of the packaging and delays in the construction period. Summary of the Invention

[0008] Embodiments of the present invention provide an integrated circuit, a packaging method for an integrated circuit, and an electronic device. Communication circuits of multiple communication types are provided inside the integrated circuit. In this way, according to the communication types actually required by the pins of different integrated circuits, a type of communication port is selectively determined to conduct the communication between the corresponding pins and the input / output controller of the integrated circuit.

[0009] The first aspect of the present invention provides an integrated circuit, which is characterized by including:

[0010] A chip pin processing circuit, communication circuits of multiple communication types, an input / output controller, and a port enable controller encapsulated inside the housing of the integrated circuit;

[0011] Pins encapsulated outside the housing, and the pins are connected to the chip pin processing circuit;

[0012] Wherein, the port enable controller selectively determines a type of communication port from the communication circuits of multiple communication types, and the input / output controller selectively cooperates with the port enable controller to control the input / output state of a predetermined port and conduct the communication between the pins and the input / output controller.

[0013] In a preferred embodiment of the present invention, the communication circuits of the multiple communication types at least include a plurality of first-type communication ports and second-type communication ports respectively connected to the input / output controller.

[0014] In a further preferred embodiment of the present invention, each output port in the communication circuits of the multiple communication types is respectively provided with a chip pin processing module.

[0015] In a still further preferred embodiment of the present invention, the number of communication ports in the communication circuits of the multiple communication types connected to the chip pin processing circuit is greater than or equal to the number of the pins, and at least some communication ports are selectively selected from the communication circuits of the multiple communication types to determine the communication types of the pins.

[0016] In a preferred embodiment of the present invention, each communication circuit in the communication circuits of the multiple communication types respectively includes an input port, an output port, and a GPIO port, and the communication protocols supported by the input port and the output port may be the same or different.

[0017] In a further preferred embodiment of the present invention, during the integrated circuit design, the port enable controller sets all the communication circuits that may be used for multiplexing to work as GPIO after power-on reset, and sets the GPIO to the input state, while turning off the pull-up and pull-down resistors; after determining the ports required in the communication circuits of the multiple communication types, the corresponding ports are enabled, and for the other communication circuits that are not needed, the GPIO is kept in the input state, and the high or low level is determined through electrical connection.

[0018] The second aspect of the present invention also provides a packaging method for an integrated circuit, which is characterized by including:

[0019] Providing communication circuits of multiple communication types in the integrated circuit,

[0020] Determining a type of communication port from the communication circuits of the multiple communication types to conduct the communication between the pins and the input / output controller;

[0021] The input / output controller, the communication circuits of multiple communication types, the chip pin processing circuit that are sequentially electrically connected inside the integrated circuit housing, and the pins outside the integrated circuit housing.

[0022] In a preferred embodiment of the present invention, each communication circuit in the communication circuits of the multiple communication types respectively includes an input port, an output port, and a GPIO port; when designing the integrated circuit, the port enable controller sets all communication circuits that may be used for multiplexing to work as GPIO after power-on reset, and the GPIO is set to the input state, while the pull-up and pull-down resistors are turned off; after determining the ports required in the communication circuits of the multiple communication types, the corresponding ports are enabled, and for other communication circuits that are not needed, the GPIO is kept set to the input state, and the high or low level is determined through electrical connection.

[0023] In a preferred embodiment of the present invention, when redesigning the second integrated circuit based on the first integrated circuit, the communication ports used in the communication circuits of the multiple communication types are adjusted, the pins to be used are determined, and the re-determined communication ports and the re-determined pins are connected using the chip pin processing circuit.

[0024] The third aspect of the present invention further provides an electronic device, which is characterized by including: any one of the integrated circuits provided in the first aspect, and a circuit board on which the integrated circuit is installed.

[0025] By adopting the above technical solutions provided by the present invention, more types of protocol interfaces can be multiplexed as much as possible on fewer package pins. Thus, the probability of repeated design and packaging for the same integrated circuit is reduced, the product iteration cycle is shortened without changing the expected performance of the product, the number of various simulation tests for the new package is reduced, and the test modification cost is reduced, improving the competitiveness of the product. Description of the Drawings

[0026] Figure 1 It is a block diagram of the structure of an integrated circuit provided by an embodiment of the present invention.

[0027] Figure 2 It is a block diagram of the structure of another integrated circuit provided by an embodiment of the present invention.

[0028] Figure 3 It is a block diagram of the structure of yet another integrated circuit provided by an embodiment of the present invention.

[0029] Figure 4 It is a flowchart of a method for packaging an integrated circuit provided by an embodiment of the present invention.

[0030] Figure 5 It is a schematic diagram of the state of an integrated circuit in a method for packaging an integrated circuit provided by an embodiment of the present invention Figure 1 。

[0031] Figure 6 It is a schematic diagram of the state of an integrated circuit in a method for packaging an integrated circuit provided by an embodiment of the present invention Figure 2 。

[0032] Figure 7 Schematic diagram of the integrated circuit state in the integrated circuit packaging method provided by the embodiment of the present invention Figure 3 。

[0033] Figure 8 Schematic diagram of the structure of an electronic device provided by the embodiment of the present invention Detailed implementation manners

[0034] In the case where the packaging size requirements are relatively high and the number of packaging pins is limited; expanding new applications or developing new markets generally leads to a delay in the project due to the need for a redesigned package. Based on this, the embodiments of the present invention provide an integrated circuit, a packaging method for the integrated circuit, and an electronic device. A communication circuit with multiple communication types is provided inside the integrated circuit. In this way, according to the communication types actually required by the pins of different integrated circuits, a type of communication port is selectively determined to conduct the communication between the corresponding pins and the input / output controller of the integrated circuit

[0035] Such as Figure 1 shown is a block diagram of the structure of an integrated circuit provided by this embodiment. The integrated circuit includes

[0036] A chip pin processing circuit 130, communication circuits 140 with multiple communication types, an input / output controller 150, and a port enable controller 160 encapsulated inside the integrated circuit housing 110

[0037] Pins 120 encapsulated outside the integrated circuit housing 110, and the pins 120 are connected to the chip pin processing circuit 130

[0038] Among them, the port enable controller 160 selectively determines a type of communication port from the communication circuits 140 with multiple communication types. The input / output controller 150 selectively cooperates with the port enable controller 160 to control the input / output state of a predetermined port, and conducts the communication between the pins 120 and the input / output controller 150. And it can make the pins 120 support a specified type of communication protocol according to the determined type of communication port

[0039] Since the communication circuits 140 with multiple communication types can support multiple different types of communication, that is, they can support multiple types of communication protocols, when it is necessary for the integrated circuit pins to support a specified type of communication protocol in the future (for example, when redesigning an integrated circuit based on a previous integrated circuit product, or when testing the integrated circuit according to a new communication protocol in the future), a type of communication port can be directly and selectively determined. In this way, the corresponding pins and the input / output controller of the integrated circuit can support the specified communication protocol according to the specified communication port

[0040] Therefore, by adopting the above technical solution provided by the embodiment of the present invention, more types of protocol interfaces can be multiplexed as much as possible on fewer package pins. Thus, the occurrence probability of repeated design and packaging for the same integrated circuit is reduced, the product iteration cycle is shortened without changing the expected performance of the product, the number of various simulation tests for the new package is reduced, and the test modification cost is reduced, thereby improving the competitiveness of the product.

[0041] As Figure 1 shown, in a preferred implementation manner provided in this embodiment, the above integrated circuit further includes: a port pull-up / down controller 170. The port pull-up / down controller 170 cooperates with the input / output controller 150 and the port enable controller 160 to better control to determine a type of communication port from communication circuits 140 of multiple communication types. For example, as Figure 1 shown, the direct structural relationship of these circuit modules is: communication circuits 140 of multiple communication types, input / output controller 150, port enable controller 160, and port pull-up / down controller 170 together form a selection unit (MUX UNIT), and multiple selection units can be set according to the port quantity requirement. Each selection unit is internally provided with communication circuits 140 of multiple communication types and a GPIO controller 180 connected in parallel with the communication circuits 140 of multiple communication types. The GPIO controller 180 is internally provided with communication circuits 140 of multiple communication types, input / output controller 150, and port enable controller 160.

[0042] In a preferred implementation manner of this embodiment, the communication circuits 140 of multiple communication types at least include a first type of communication port and a second type of communication port respectively connected to the input / output controller. Further, a chip pin processing module 130 is respectively provided for each output port in the communication circuits 140 of multiple communication types.

[0043] It should be noted that each circuit module in the above chip pin processing circuit 130, communication circuits 140 of multiple communication types, input / output controller 150, and port enable controller 160 can be an integrated circuit respectively integrated together according to the integrated circuit design requirements, or can be multiple separately designed circuit modules. Among them, multiple communication circuits 140 of different multiple communication types can be designed, and each communication circuit 140 of multiple communication types can also support multiple different communication protocols. For example, a first port supporting a first protocol and a second port supporting a second protocol are respectively provided in the communication circuits 140 of multiple communication types; the first port and the second port can be set to support the same communication protocol or different communication protocols; for example, the first port in some communication circuits 140 of multiple communication types supports protocol A, and the first port in some communication circuits 140 of multiple communication types supports protocol B; the second port in some communication circuits 140 of multiple communication types supports protocol C, and the second port in some communication circuits 140 of multiple communication types supports protocol C; moreover, the communication circuits 140 of multiple communication types can also be provided with one or more first ports and one or more second ports. These different implementation manners all fall within the protection scope of the technical solutions provided in this embodiment.

[0044] In addition, in this embodiment, the main function of the chip pin processing circuit 130 is to connect the pin 120 and the inside of the integrated circuit. Since the pin 120 is usually provided with a part connected to the chip pin processing circuit 130, the pin 120 mentioned in this embodiment is usually the part of the integrated circuit chip that leaks outside the housing; the pin 120 can be plugged into the data control board, so that the controller inside the integrated circuit can complete the information, instruction transmission and conversion with other circuits on the data control board.

[0045] In the preferred implementation manner of this embodiment, each communication circuit in the communication circuits 140 of multiple communication types respectively includes an input port, an output port, and a GPIO port, and the communication protocols supported by the input port and the output port can be the same or different. In a further preferred implementation manner, during the integrated circuit design, the port enable controller sets all communication circuits that may be used for multiplexing to work as GPIO after power-on reset, and the GPIO is set to the input state, and at the same time, the pull-up and pull-down resistors are turned off; after determining the ports that need to be used in the communication circuits of multiple communication types, the corresponding ports are enabled, and for other communication circuits that do not need to be used, the GPIO is kept set to the input state, and the high or low level is determined through electrical connection.

[0046] More specifically, as Figure 2As shown in the figure, in an integrated circuit provided in this embodiment, in the design of the integrated circuit (e.g., a chip), a MUX_UNIT unit (the communication circuit 140 of the above-mentioned multiple communication types) is used to multiplex multiple protocol interfaces and GPIO. The multiplexed signals are connected to the IO_PAD (the chip pin processing circuit 130 of the above-mentioned chip), and are led to the package pins through connection lines. Among them, the connection lines are a general term for substrate lines, wire bonding, flip chip, etc.; wirebonding is usually called wire bonding in Chinese, which is one of the processes in the integrated circuit packaging industry. It is a technology that uses metal wires with a wire diameter of 15-50 microns to connect the chip and the lead frame, enabling the tiny chip to communicate with the external circuit without adding too much area; flip chip is usually called flip chip in Chinese, which is a leadless structure, generally containing circuit units, and is designed to be electrically and mechanically connected to the circuit through an appropriate number of solder balls located on its surface.

[0047] As Figure 2 shown in the figure, the IO controller (the input / output controller 150, the IO control signals of each protocol interface and GPIO are sent out by each protocol IP module in the integrated circuit, and can implement the port direction of multiple protocol interfaces and GPIO and control the pull-up and pull-down resistors. The MUX controller part selects which protocol interface of the MUX_UNIT unit to connect to the IO_PAD unit according to the specific situation of the application scenario. The IO_PAD is the internal PAD unit of the chip, and the internal signals of the chip can be led to the package pins through wire bonding or flip chip during packaging.

[0048] Among them, the GPIO mentioned in this embodiment, its full English name is: General-purpose input / output, which is the abbreviation of general-purpose input / output. Its function is similar to P0-P3 of 8051. Its pins can be freely used by the user through programming. Depending on the actual situation, the PIN pins can be used as general input (GPI), general output (GPO), or general input and output (GPIO).

[0049] This embodiment also provides an integrated circuit. The number of communication ports of the communication circuit 140 of multiple communication types connected to the chip pin processing circuit 130 is greater than or equal to the number of pins 120, and at least some communication ports are selectively selected from the communication circuit 140 of multiple communication types to determine the communication type of the pins.

[0050] As Figure 2As shown in the figure, it means that when the package size is sufficient, multiple IO_PADs can be connected to enough package pins. Considering the cost control and package size requirements, in actual package design, the package pins will only be connected to the required IO_PAD units according to the specific application scenario, and the unnecessary IO_PADs will generally not be connected. Specifically, Figure 3 The chip of this package can use the A protocol interface, B protocol interface and GPIO in the original application scenario. If the new application scenario requires the A protocol interface or the B protocol interface and also requires the C protocol interface or the D protocol interface when expanding the market, this package needs to be redesigned.

[0051] In existing integrated circuits, the MUX_UNIT unit implements the switching of various protocol interfaces, which is fixed after the chip design is completed. The package pins are also fixed after the package design is completed. When the package area is limited, the following methods are generally used to switch the protocol interface at the package level:

[0052] 1. Redesign the packaging and connection relationship,

[0053] 2. No new package is designed, and an external protocol conversion chip is used.

[0054] 3. Use a higher-precision packaging process when designing the package for the first time, and bring out as many package pins as possible while controlling the area.

[0055] However, these three methods have the following defects:

[0056] 1. Changing the package design involves a series of costs and time expenditures, including package design, package thermal simulation, trial production, FT solution modification, and reliability testing. The cost is very high and the timeliness is poor.

[0057] 2. The protocol conversion chip needs to be purchased from outside, which is limited in size, cost, and selectivity, and the supply chain problem is prominent. Since an external chip is used, the PCB area of the entire solution will inevitably increase.

[0058] 3. The use of unnecessary high-precision packaging processes in the first packaging design will lead to high mass production costs, limited supplier selection, and correspondingly increased costs for PCBs and passive components, reducing product competitiveness.

[0059] In addition, this embodiment also provides a group of integrated circuits, including a first integrated circuit and a second integrated circuit, the second integrated circuit and the first integrated circuit have the same or similar circuit structure inside, but the second integrated circuit and the first integrated circuit are different in the number of pins and / or the communication protocol supported by the pins; and the first integrated circuit is as described above Figures 1 - 3Integrated circuits are constructed in any way. The second integrated circuit can re-adjust the internal wiring method on the basis of the first integrated circuit according to the following method, so that the second integrated circuit can complete design and packaging quickly.

[0060] Among them, the specific forms of the integrated circuit chips mentioned in this embodiment include but are not limited to: 1. System on Chip, abbreviated as SoC in English; 2. Field Programmable Gate Array, abbreviated as FPGA in English; 3. Single-chip microcomputers including integrated circuit controllers, etc. And integrated circuits are often directly called chips. It can be installed in but not limited to the following devices: electronic products such as computers, tablets, mobile phones, computer peripherals, etc., and can also be wearable devices or intelligent travel tools, etc.

[0061] Such as Figure 4 As shown, this embodiment also provides a packaging method for an integrated circuit, and the method includes:

[0062] S110. Provide communication circuits of multiple communication types in the integrated circuit,

[0063] S120. Determine a type of communication port from the communication circuits of multiple communication types to conduct communication between the pins and the input / output controller;

[0064] S130. Package the input / output controller, communication circuits of multiple communication types, chip pin processing circuits inside the integrated circuit housing, and the pins outside the integrated circuit housing.

[0065] Therefore, by adopting the above technical solutions provided by the embodiments of the present invention, as many types of protocol interfaces as possible can be multiplexed on fewer packaging pins. Thereby reducing the probability of repeated design and packaging for the same integrated circuit, shortening the product iteration cycle without changing the expected performance of the product, reducing the number of various simulation tests for new packages, and reducing the test modification cost, and improving the competitiveness of the product.

[0066] In the packaging method for an integrated circuit provided in this embodiment, a flexible packaging method is used. One of the key technical means is that all MUX_UNITs that may be multiplexed during chip design are set to GPIO inputs and the pull-up and pull-down are turned off (the pull-up and pull-down can also be turned off for non-GPIO inputs). On this basis, short-circuiting the connection lines on different IO_PADs will not cause conflicts, creating the possibility for method multiplexing. When adopting different application scenarios, the software can turn off unused protocol interfaces or keep the GPIO input and turn off the pull-up and pull-down to prevent interference with the enabled protocol interfaces. At the same time, turn on the protocol interfaces to be used to meet the requirements of the new application scenario.

[0067] Among them, in the preferred implementation of this embodiment, each communication circuit in the communication circuits of multiple communication types respectively includes an input port, an output port, and a GPIO port; during integrated circuit design, the port enable controller sets all communication circuits that may be used for multiplexing to work as GPIO after power-on reset, and the GPIO is set to the input state, while the pull-up and pull-down resistors are turned off; after determining the ports required in the communication circuits of multiple communication types, the corresponding ports are enabled, and for other communication circuits that are not required, the GPIO is kept set to the input state, and the high or low level is determined through electrical connection.

[0068] When redesigning the second integrated circuit based on the first integrated circuit, the communication ports used in the communication circuits of multiple communication types are adjusted, and the pins required are determined, and the re-determined communication ports and the re-determined pins are connected using the chip pin processing circuit.

[0069] Specifically, as Figures 5 - 7 shown: As Figure 5 shown, during integrated circuit design, the MUX controller sets all MUX_UNITs that may be used for multiplexing to work as GPIO after power-on reset, and the GPIO is set to the input state, while the pull-up and pull-down resistors are turned off.

[0070] In addition, according to the actual situation, if the port corresponding to a certain protocol interface is in the input state and the pull-up and pull-down resistors are not turned on, the MUX_UNIT can also select this protocol interface to work after power-on reset.

[0071] As Figure 6 shown, for example, in a new application scenario where protocol interface C or protocol interface D is required and there is no need to redesign the package, the IOPAD of protocol interface C or D can be directly connected to the IOPAD of protocol interface A or B through bonding wires or substrate connection wires.

[0072] As Figure 7 shown, after power-on, which interface protocol is selected to be led out through the package pins according to the actual situation of the connection wires. For example, keep IO_PAD1 and IO_PAD2 in the GPIO mode, and protocol interfaces A and B do not work. The unconnected IOPAD3 and IOPAD4 in the original package are led to the existing package pins through connection wires and switched to protocol interface C.

[0073] In this way, it is possible to realize multiplexing more protocol interfaces using the existing package pins without increasing the package pins; enable small-size packages to adapt to more application scenarios and a larger market, and also reduce the probability of repeated design of packages.

[0074] As Figure 8As shown, this embodiment also provides an electronic device 600, which includes: any one of the integrated circuits mentioned above, and a circuit board on which the integrated circuit is installed.

[0075] Specifically, the electronic device 600 includes one or more processors, communication components, etc. The one or more processors include, for example: one or more central processing units (CPUs) 601, and / or one or more graphics processing units (GPUs) 613, etc. The processor can execute various appropriate actions and processes according to the executable instructions stored in the read-only memory (ROM) 602 or the executable instructions loaded from the storage section 608 into the random access memory (RAM) 603. The communication components include a communication component 612 and / or a communication interface 609. Among them, the communication component 612 can include, but is not limited to, a network card, and the network card can include, but is not limited to, an IB (Infiniband) network card. The communication interface 609 includes a communication interface of a network interface card such as a LAN card, a modem, etc. The communication interface 609 performs communication processing via a network such as the Internet.

[0076] The processor can communicate with the read-only memory 602 and / or the random access memory 603 to execute executable instructions, connect to the communication component 612 through the communication bus 604, and communicate with other target devices through the communication component 612.

[0077] In addition, in the RAM 603, various programs and data required for device operation can also be stored. The CPU 601 or GPU 613, ROM 602, and RAM 603 are connected to each other through the communication bus 604. In the case of having the RAM 603, the ROM 602 is an optional module. The RAM 603 stores executable instructions, or writes executable instructions into the ROM 602 during operation. The executable instructions cause the processor to perform the operations corresponding to the above communication method. The input / output (I / O) interface 605 is also connected to the communication bus 604. The communication component 612 can be integrally provided, or can be provided with multiple sub-modules (such as multiple IB network cards) and linked on the communication bus.

[0078] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication interface 609 including a network interface card such as a LAN card, a modem, etc. The drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed, so that the computer program read from it can be installed into the storage section 608 as needed.

[0079] It should be noted that, as Figure 6 shown, the architecture is only an optional implementation. In the actual practice process, the number and type of the above Figure 6 components can be selected, deleted, added or replaced according to actual needs; in terms of the setting of different functional components, implementation methods such as separate setting or integrated setting can also be adopted. For example, the GPU and CPU can be set separately or the GPU can be integrated on the CPU, the communication components can be set separately or can be integrated on the CPU or GPU, and so on. These alternative implementation methods all fall within the protection scope of the present invention.

[0080] The method and apparatus, electronic device and storage medium of the present invention can be implemented in many ways. For example, the method and apparatus, electronic device and storage medium of this embodiment can be implemented by software, hardware, firmware or any combination of software, hardware and firmware. The above order of steps for the method is only for illustration, and the steps of the method of this embodiment are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, the present invention can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the method according to this embodiment. Therefore, the present invention also covers a recording medium storing a program for executing the method according to this embodiment.

[0081] The description of this embodiment is given for the purpose of illustration and description, and is not exhaustive or limited to the disclosed form. Many modifications and variations are obvious to those of ordinary skill in the art. The embodiments are chosen and described in order to better explain the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and design various embodiments adapted to specific purposes with various modifications.

Claims

1. An integrated circuit, characterized in that, Comprising: A chip pin processing circuit, communication circuits of multiple communication types, an input / output controller, and a port enable controller encapsulated inside the housing of an integrated circuit. Each communication circuit of the multiple communication types of communication circuits includes an input port, an output port, and a GPIO port respectively. The communication protocols supported by the input port and the output port can be the same or different; Pins encapsulated outside the housing, and the pins are connected to the chip pin processing circuit; Wherein, the port enable controller selectively determines one type of communication port from the multiple communication types of communication circuits, and the input / output controller selectively cooperates with the port enable controller to control the input / output state of a predetermined port and conduct communication between the pins and the input / output controller. Wherein, during the design of the integrated circuit, the port enable controller sets all communication circuits that may be used for multiplexing to work as GPIO after power-on reset, and the GPIO is set to the input state, and at the same time, the pull-up and pull-down resistors are turned off; after determining the ports required in the multiple communication types of communication circuits, the corresponding ports are enabled. For other communication circuits that are not required, the GPIO is kept set to the input state, and the high or low level is determined through electrical connection.

2. The integrated circuit according to claim 1, wherein The multiple communication types of communication circuits at least include a plurality of first-type communication ports and second-type communication ports respectively connected to the input / output controller.

3. The integrated circuit according to claim 2, wherein Each output port in the multiple communication types of communication circuits is respectively provided with a chip pin processing module.

4. The integrated circuit according to claim 3, wherein The number of communication ports in the multiple communication types of communication circuits connected to the chip pin processing circuit is greater than or equal to the number of the pins, and at least some communication ports are selectively selected from the multiple communication types of communication circuits to determine the communication type of the pins.

5. A packaging method for an integrated circuit, characterized in that, Comprising: Providing communication circuits of multiple communication types in the integrated circuit according to any one of claims 1 to 4; Determining one type of communication port from the multiple communication types of communication circuits to conduct communication between the pins and the input / output controller; An input / output controller, communication circuits of multiple communication types, a chip pin processing circuit encapsulated inside the housing of the integrated circuit, and pins outside the housing of the integrated circuit.

6. The packaging method of the integrated circuit according to claim 5, characterized in that, When redesigning a second integrated circuit based on the first integrated circuit, adjusting the communication ports used in the multiple communication types of communication circuits, determining the pins required, and using the chip pin processing circuit to connect the re-determined communication ports and the re-determined pins.

7. An electronic device, characterized in that, Comprising: The integrated circuit according to any one of claims 1-4, and a circuit board on which the integrated circuit is installed.

Images