Semiconductor devices

Abstract

This invention provides a semiconductor device. When power lines, such as virtual power lines, are formed using a metal wiring layer close to the semiconductor substrate, conflicts between the first power line and wiring within a power switch circuit are avoided. The device includes: first and second power lines formed on the first wiring layer and extending in a first direction when viewed from above; a third power line connected to the first power line and a fourth power line connected to the second power line formed on the second wiring layer and extending in a second direction when viewed from above; and a first power switch circuit having a transistor disposed between the first power line and a fifth power line formed on the first wiring layer and overlapping at least one of the third or fourth power lines. The first power switch circuit has a first wiring formed on the second wiring layer that does not overlap with the third and fourth power lines and is electrically connected to the source region of the transistor and the fifth power line, and a second wiring electrically connected to the drain region of the transistor and the third power line.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] To reduce leakage current in semiconductor devices, a known method involves providing a power switch circuit between a power line and the power lines of each of multiple circuit modules, also known as a virtual power line, which is turned on when the circuit modules are in operation. For example, to improve the power supply capability of the power switch circuit, the size of the transistors used in the power switch circuit is designed to be larger than the size of the unit transistors used in the logic circuits within the circuit modules.

[0003] Patent Document 1: U.S. Patent No. 10141336

[0004] Patent Document 2: U.S. Patent Application Publication No. 2019 / 0244900

[0005] Patent Document 3: U.S. Patent Application Publication No. 2019 / 0214377

[0006] Patent Document 4: Japanese Patent Application Laid-Open No. 2018-190760

[0007] Patent Document 5: International Publication No. 2017 / 208887

[0008] If the layout size of the power switch circuit increases due to increased transistor size, the power switch circuit may not fit between power wiring lines arranged at a predetermined pitch. In this case, the power switch circuit is arranged astride the power wiring lines arranged at a predetermined pitch. Furthermore, to provide sufficient power supply voltage to circuit modules operating using a virtual power supply voltage, it is preferable to form a virtual power line between the power switch circuit and the circuit module using a metal wiring layer close to the semiconductor substrate.

[0009] However, when a virtual power line is formed between the power switch circuit and the circuit module using a metal wiring layer close to the semiconductor substrate, there is a concern that the wiring formed in the power switch circuit using the metal wiring layer close to the semiconductor substrate will conflict with the virtual power line. Summary of the Invention

[0010] The present invention has been made in view of the above-mentioned points, and aims to avoid conflict between the power line and the wiring in the power switch circuit arranged in the same layer when forming a power line such as a virtual power line using a metal wiring layer close to a semiconductor substrate.

[0011] In one embodiment of the present invention, a semiconductor device comprises: a first power supply line formed in a first wiring layer and extending in a first direction when viewed from above; a second power supply line formed in the first wiring layer and extending in the first direction; a third power supply line formed in a second wiring layer, extending in a second direction different from the first direction when viewed from above, and connected to the first power supply line, the second wiring layer being a wiring layer above the first wiring layer; a fourth power supply line formed in the second wiring layer, extending in the second direction, and connected to the second power supply line; a fifth power supply line formed in the first wiring layer; and a first power supply switch circuit having a first power supply line disposed between the first power supply line and the fifth power supply line. A transistor between the power lines, the transistor being located at a position overlapping with at least any one of the third power line and the fourth power line when viewed from above, the first power switch circuit comprising: a first wiring formed in the second wiring layer, electrically connected to the source region of the transistor and the fifth power line, extending in the second direction, on the transistor and not overlapping with the third power line and the fourth power line when viewed from above; and a second wiring formed in the second wiring layer, electrically connected to the drain region of the transistor and the third power line, extending in the second direction, on the transistor and not overlapping with the third power line and the fourth power line when viewed from above.

[0012] According to the disclosed technology, when the first power supply line is formed using a metal wiring layer close to the semiconductor substrate, it is possible to avoid conflict between the first power supply line and wiring within the power switch circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a diagram showing an example of the layout of the semiconductor device in the first embodiment.

[0014] Figure 2 Yes Figure 1 A block diagram of an example of a power switching circuit.

[0015] Figure 3 Yes Figure 2 A diagram showing an example of the layout of the power supply wiring of a power switching circuit.

[0016] Figure 4 It means from Figure 3 The layout is a diagram of the layout after removing the wiring of the M1 layer and the via holes between the M0 and M1 layers.

[0017] Figure 5 Yes Figure 3 as well as Figure 4 A perspective diagram of an example of the structure of a p-channel transistor.

[0018] Figure 6 It means along Figure 3 A cross-sectional view of the Y1-Y1' line.

[0019] Figure 7 This is a diagram showing an example of a layout of power supply wiring of a power supply switch circuit of a semiconductor device according to the second embodiment.

[0020] Figure 8 This is a diagram showing an example of a layout of power supply wiring of a power supply switch circuit of a semiconductor device according to a third embodiment.

[0021] Figure 9 This is a diagram showing an example of a layout of power supply wiring of a power switch circuit of a semiconductor device according to a fourth embodiment.

[0022] Figure 10 A diagram showing an example of the layout of a semiconductor device in the fifth embodiment.

[0023] Figure 11 A diagram showing an example of the layout of a semiconductor device in the sixth embodiment.

[0024] Figure 12 Yes Figure 11 FIG. 1 is a diagram showing an example of a layout of power supply wiring of the power switch circuit PSW2.

[0025] Description of Reference Numerals

[0026] 100, 102, 104…semiconductor device, D…drain region, ECAP…end cap, G…gate electrode, H1…spacer, PA…peripheral region, PCNT…power control signal, PCNT1…power switch control circuit, PD…power domain, PSW1, PSW2…power switch circuit, PT…p-channel transistor, S…source region, SCA…standard cell area, SIG…signal line, VDD…power line, VSS…power line (ground line), VVDD…virtual power line, W1…spacer. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments will be described using the drawings.

[0028] (First embodiment)

[0029] Figure 1 An example of the layout of the semiconductor device in the first embodiment is shown. Figure 1 The semiconductor device 100 shown has, for example, at least one power domain PD. A standard cell area SCA is provided in the power domain PD, in which a plurality of standard cells (not shown) are arranged. Although not particularly limited, the transistor mounted on the semiconductor device 100 is a finFET. Figure 5The standard cell area SCA is an example of a first area where a logic circuit can be arranged.

[0030] The end cap ECAP shown in the hatched pattern is arranged around the standard cell area SCA. The end cap ECAP has a dummy gate electrode or a dummy transistor not shown. Figure 1 The longitudinal direction, that is, the Y direction, is alternately arranged with an interval H1. Figure 1 The virtual power supply line VVDD01b and the ground line VSS01c extend in the transverse direction, that is, in the X direction. The X direction is an example of a first direction, and the Y direction is an example of a second direction, that is, a direction intersecting the X direction.

[0031] Furthermore, in the standard cell area SCA, virtual power supply lines VVDD11b and ground lines VSS11c extending in the Y direction are alternately arranged at intervals W1 in the X direction. Figure 1 In FIG. 1 , virtual power supply lines VVDD01b and 11b are shown by solid lines, and ground lines VSS01c and 11c are shown by dotted lines.

[0032] For example, virtual power line VVDD01b and ground line VSS01c extending in the X direction are formed using layer M0, the metal wiring layer closest to the semiconductor substrate. Virtual power line VVDD11b and ground line VSS11c extending in the Y direction are formed using layer M1, the metal wiring layer located directly above layer M0. Layer M0 is an example of a first wiring layer, and layer M1 is an example of a second wiring layer. Virtual power line VVDD01b is an example of a first power line, and ground line VSS01c is an example of a second power line. Virtual power line VVDD11b is an example of a third power line, and ground line VSS11c is an example of a fourth power line.

[0033] When describing the power supply line VDD without distinguishing wiring layers, etc., it is simply referred to as power supply line VDD or wiring VDD. When describing the virtual power supply line VVDD without distinguishing wiring layers, etc., it is simply referred to as virtual power supply line VVDD or wiring VVDD. When describing the ground line VSS without distinguishing wiring layers, etc., it is simply referred to as ground line VSS or power supply line VSS.

[0034] Virtual power lines VVDD01b and VVDD11b, extending in the X and Y directions, respectively, are interconnected at their intersections via vias. Similarly, ground lines VSS01c and VSS11c, extending in the X and Y directions, respectively, are interconnected at their intersections via vias. Furthermore, a mesh of virtual power lines VVDD and ground lines VSS are provided in the standard cell area SCA. Furthermore, a power line VDD (not shown) is provided to supply power to the virtual power line VVDD using multiple wiring layers above the M1 layer. The power line VDD is an example of a third power line.

[0035] A plurality of power switch circuits PSW1 are spaced apart in the standard cell area SCA. For example, each power switch circuit PSW1 is designed to have a layout size that allows it to be placed in an area surrounded by two virtual power lines VVDD01b extending in the X direction and two ground lines VSS11c extending in the Y direction.

[0036] In other words, each power switch circuit PSW1 is a two-height cell, arranged between two virtual power lines VVDD01b extending in the X direction, spanning one ground line VSS01c. Furthermore, each power switch circuit PSW1 is arranged between two ground lines VSS11c extending in the Y direction, spanning one virtual power line VVDD11b. Furthermore, no standard cells are arranged in the region where the power switch circuits PSW1 are arranged.

[0037] By designing the power switch circuit PSW1 to be larger than both the interval H1 and the interval W1, the ability of each power switch circuit PSW1 to supply the power supply voltage VVDD to the standard cell can be increased. However, when the X-direction dimension of the power switch circuit PSW1 is designed to be larger than the interval W1, the power switch circuit PSW1 overlaps with the virtual power line VVDD11b or ground line VSS11c of the M1 layer extending in the Y direction in a plan view. Similarly, when the Y-direction dimension of the power switch circuit PSW1 is designed to be larger than the interval H1, the power switch circuit PSW1 overlaps with the ground line VSS01c or virtual power line VVDD01b of the M0 layer extending in the X direction in a plan view.

[0038] As in Figure 3As explained above, not only the M0 layer but also the M1 layer is used to form the internal wiring of the power switch circuit PSW1. Therefore, it is necessary to design a layout so that the internal wiring of the M1 layer in the power switch circuit PSW1 does not conflict with the power wiring VVDD11b of the M1 layer. In particular, when the wiring of the M1 layer in the power switch circuit PSW1 is connected to the source electrode and the drain electrode alternately arranged across the gate electrode in the transistor, it is necessary to avoid conflict with the power wiring VVDD11b of the M1 layer to form the wiring of the M1 layer. The layout is designed in Figure 3 as well as Figure 4 is described in .

[0039] like Figure 1 As shown, each power switch circuit PSW1 is arranged in the X direction at a pitch that is twice the wiring pitch of the virtual power line VVDD01b (or ground line VSS01c) arranged in the X direction. Furthermore, each power switch circuit PSW1 is arranged in the Y direction at a pitch that is four times the wiring pitch of the virtual power line VVDD11b (or ground line VSS11c) arranged in the Y direction.

[0040] That is, for the plurality of power switch circuits PSW1 arranged in the standard cell area SCA, the transistors (for example, Figure 3 Alternatively, the power switch circuits PSW1 may be arranged in the X and Y directions at a pitch that is an integer multiple of the wiring pitch of the virtual power line VVDD (or ground line VSS), such as three times, six times, or the like.

[0041] By making the arrangement pitch an integral multiple, the positional relationship of the virtual power lines VVDD01b, 11b and the ground lines VSS01c, 11c relative to the power switch circuits PSW1 can be made uniform across all power switch circuits PSW1. Consequently, layout data for the power switch circuits PSW1 can be shared across at least one of the VVDD01b, 11b and ground lines VSS01c, 11c, facilitating layout design of the power switch circuits PSW1.

[0042] Furthermore, the size of the power switch circuit PSW1 in the X direction is not limited to twice the distance W1. Similarly, the size of the power switch circuit PSW1 in the Y direction is not limited to twice the distance H1. Figure 1 In the embodiment, the power switch circuit PSW1 is arranged in a zigzag pattern, but the arrangement pattern is not limited to Figure 1 .

[0043] Figure 2 Show Figure 1The power switch circuit PSW1 is an example of a power switch circuit PSW1. The power switch circuit PSW1 includes a p-channel transistor PT and a power switch control circuit PCNT1. Note that the p-channel transistor PT actually includes a plurality of transistors connected in parallel.

[0044] The source of the p-channel transistor PT is connected to, for example, a power supply line VDD that supplies an external power supply VDD, and the drain of the p-channel transistor is connected to a virtual power supply line VVDD of the standard cell. The gate electrode of the p-channel transistor PT is connected to the output of the power switch control circuit PCNT1. Alternatively, the power switch circuit PSW1 may include an n-channel transistor in place of the p-channel transistor PT. In this case, the source of the n-channel transistor is connected to the ground line VSS, and the drain is connected to each logic circuit of the standard cell and to a virtual ground line that supplies a ground voltage.

[0045] Power switch control circuit PCNT1 is connected to power line VDD and ground line VSS to maintain constant operation, and operates based on power control signal PCNT. When power control signal PCNT indicates an active mode, which activates circuits within power domain PD, power switch control circuit PCNT1 supplies ground voltage VSS to the gate electrode of p-channel transistor PT. This turns on p-channel transistor PT, connecting power line VDD to virtual power line VVDD.

[0046] When power control signal PCNT indicates power-down mode, power switch control circuit PCNT1 supplies power supply voltage VDD to the gate electrode of p-channel transistor PT. This turns off p-channel transistor PT, disconnecting power line VDD from virtual power line VVDD. Thus, p-channel transistor PT operates based on power control signal PCNT, functioning as a power switch connecting power line VDD to virtual power line VVDD.

[0047] In active mode, the p-channel transistor PT is turned on, connecting the power supply line VDD to the virtual power supply line VVDD. Thus, in active mode, the standard cells within the power domain PD receive the power supply voltage VDD via the virtual power supply line VVDD and operate. On the other hand, in power-down mode, the p-channel transistor PT is turned off, disconnecting the power supply line VDD from the virtual power supply line VVDD. Consequently, the standard cells within the power domain PD stop receiving the power supply voltage VDD and cease operation in power-down mode.

[0048] Figure 3 Show Figure 2 An example of the layout of the power supply wiring of the power switch circuit PSW1 is shown in FIG. Figure 3 in, omit Figure 2 The power switch control circuit PCNT1 is described.

[0049] Hereinafter, virtual power lines VVDD01b, VVDD11b and ground lines VSS01c, VSS11c extending from the outside of the power switch circuit PSW1 are also referred to as power lines VVDD, VSS. Virtual power lines VVDD02b, VVDD12b and power lines VDD02a, VDD12a enclosed within the power switch circuit PSW1 are also referred to as wirings VVDD02b, VVDD12b, VDD02a, VDD12a, respectively. Figure 1 As described in

[15] , two power supply lines VVDD01b and one power supply line VSS01c extending in the X direction are formed using the M0 layer, and two power supply lines VSS11c and one power supply line VVDD11b extending in the Y direction are formed using the M1 layer.

[0050] Power switch circuit PSW1 includes multiple p-channel transistors PT having multiple fins extending in the X direction and multiple gate electrodes G extending in the Y direction. The multiple fins are spaced apart in the Y direction. The multiple gate electrodes G are spaced apart in the X direction. Dummy gate electrodes DMYG are arranged on both sides of the region where the multiple gate electrodes G are arranged in the X direction.

[0051] Each gate electrode G is Figure 2 The gate electrode of the p-channel transistor PT shown is connected to the signal line SIG formed in the M0 layer via a via hole. The signal line SIG is connected to the M0 layer via a wiring or a via hole not shown. Figure 2 The output of the power switch control circuit PCNT1 is shown connected.

[0052] In the p-channel transistor PT, a source region S or a drain region D is formed between two adjacent gate electrodes G. The source regions S and drain regions D are alternately formed with the gate electrodes G interposed therebetween. Each source region S is electrically connected to a local wiring VDDLIa extending in the Y direction above each source region S on the L1 (local interconnect) layer. Each drain region D is electrically connected to a local wiring VVDDLIb extending in the Y direction above each drain region D on the L1 layer. The L1 layer is a wiring layer provided between the semiconductor substrate and the M0 layer.

[0053] In the finFET, the source region S and the drain region D are each formed in a fin. Therefore, the local wiring VDDLIa is connected to the fin functioning as the source region S, and the local wiring VVDDLIb is connected to the fin functioning as the drain region D.

[0054] Local wiring VDDLIa extending in the Y direction on the L1 layer is connected to wiring VDD02a on the M0 layer extending in the X direction on the p-channel transistor PT via a via, and is further connected to wiring VDD12a on the M1 layer extending in the Y direction on the source region S via a via. Wiring VDD12a on the M1 layer extending in the Y direction on the source region S is an example of a first wiring. The vias indicated by triangular marks in the figure represent both the via provided between the L1 layer and the M0 layer and the via provided between the M0 layer and the M1 layer, and are provided at positions that overlap when viewed from above.

[0055] By placing the M1 layer wiring VDD12a on the local wiring VDDLIa of each source region S and interconnecting them, the resistance of the source region S extending in the Y direction can be reduced, thereby enhancing the supply of power supply voltage VDD. Furthermore, by interconnecting the local wiring VDDLIa via the M0 layer wiring VDD02a, a sufficient power supply voltage VDD can be efficiently supplied to each source region S.

[0056] One or both of the wiring VDD02a of the M0 layer and the wiring VDD12a of the M1 layer are connected to the mesh power line VDD formed in the wiring layer above the M1 layer via a via hole not shown. For example, the via hole connecting the wiring VDD02a or the wiring VDD12a to the power line VDD can also be formed at the same position as the via hole indicated by the triangle mark when viewed from above on the source region S. Alternatively, the via hole connecting the wiring VDD02a to the power line VDD can be formed together with the wiring VDD12a of the M1 layer so that the wiring VDD02a of the M0 layer is relative to the source region S. Figure 3 Further extending in the X direction, the position may be formed so that the wiring VDD12a of the M1 layer is opposite to the Figure 3 A position further extending in the Y direction.

[0057] The local wiring VVDDLIb extending in the Y direction on the L1 layer is connected to the wiring VVDD02b on the M0 layer extending in the X direction on the p-channel transistor PT via a via, and is further connected to the wiring VVDD12b on the M1 layer extending in the Y direction on the drain region D via a via. The wiring VVDD12b on the M1 layer extending in the Y direction on the drain region D is an example of a second wiring.

[0058] By placing the M1 layer wiring VVDD12b on the local wiring VVDDLIb of each drain region D and interconnecting them, the resistance of the drain region D extending in the Y direction can be reduced, thereby enhancing the supply of the power supply voltage VVDD. Furthermore, by interconnecting the local wiring VVDDLIb via the M0 layer wiring VVDD02b, a sufficient power supply voltage VVDD can be efficiently output from each drain region D.

[0059] exist Figure 3 In the example, the M1 layer power supply line VVDD11b is formed on the source region S located at the center in the X direction of the p-channel transistor PT. The M1 layer power supply line VVDD11b supplies the power supply voltage VVDD supplied from each drain region D of the p-channel transistor PT via the local interconnect VVDDLIb and the M0 layer power supply line VVDD02b to the standard cell. Alternatively, the M1 layer power supply line VVDD11b may be arranged at a location other than the source region S.

[0060] By arranging the M1 layer power supply line VVDD11b at the center of the p-channel transistor PT in the X direction, the difference in distance between the six drain regions D and the M1 layer power supply line VVDD11b can be reduced. This reduces variations in parasitic resistance between each drain region D and the M1 layer power supply line VVDD11b, enabling efficient supply of the power supply voltage VVDD to the standard cell. Furthermore, the M1 layer power supply line VVDD11b is not limited to a single line; multiple lines may be arranged in a group. In this case, the group of multiple M1 layer power supply lines VVDD11b may also be located at the center of the p-channel transistor PT in the X direction.

[0061] On the other hand, to avoid conflict with the M1 layer power supply line VVDD11b, the M1 layer wiring VDD12a is not formed in the source region S facing the M1 layer power supply line VVDD11b. However, the local wiring VDDLIa in the source region S facing the M1 layer power supply line VVDD11b is sequentially connected to the M0 layer wiring VDD02a extending in the X direction and the M1 layer power supply line VDD12a via vias, and is also connected to the power supply line VDD above the M1 layer.

[0062] Therefore, even if the power switch circuit PSW1 is large and the power supply line VVDD11b of the M1 layer is routed across the power switch circuit PSW1, the desired power supply voltage VDD can be supplied to the source region S located below the power supply line VVDD112b of the M1 layer. In other words, a sufficient power supply voltage VVDD can be supplied from the power switch circuit PSW1 to the standard cell without reducing the supply capacity of the power supply voltage VDD to the power switch circuit PSW1.

[0063] Figure 4 Shown from Figure 3The layout is the layout after removing the wiring of the M1 layer and the conductive vias between the M0 and M1 layers. The local wiring VDDLIa of the L1 layer electrically connected to each source region S is connected to the two wirings VDD02a of the M0 layer extending in the X direction through the conductive vias. The local wiring VVDDLIb of the L1 layer electrically connected to each drain region D is connected to the two wirings VVDD02b of the M0 layer extending in the X direction through the conductive vias. As a result, even if the power supply line VVDD11b ( Figure 3 ) Even when wiring is performed in the Y direction on the power switch circuit PSW1, the repetitive structure and repetitive intervals of the source region S, the gate electrode G, and the drain region D can be maintained to form a p-channel transistor PT.

[0064] Figure 5 Show Figure 3 as well as Figure 4 An example of the structure of a p-channel transistor PT. The p-channel transistor PT has a fin extending in the X direction provided on a semiconductor substrate, and a gate electrode G extending in the Y direction across the fin. Figure 5 In the example shown, the p-channel transistor PT has eight fins and ten gate electrodes G. A gate insulating film is formed between the fins and the gate electrodes G, and the channel of the p-channel transistor PT is formed on the surface portion of the fin covered by the gate insulating film. Alternatively, the number of fins may be other than eight, and the number of gate electrodes G may be other than ten.

[0065] Furthermore, the source region S and the drain region D are respectively provided on both sides of the gate electrode G on the fin. Although not shown in the figure, local wiring VDD and local wiring VVDD are respectively provided in each source region and each drain region D along the extension direction of the gate electrode G. Figure 5 In the embodiment, the source region S and the drain region D may be swapped.

[0066] Figure 6 Shown along Figure 3 The cross section of the line Y1-Y1' is shown. Fins are formed in an element isolation insulating film such as STI (Shallow Trench Isolation) formed on a semiconductor substrate. Figure 6 In the cross section shown, the upper portion of the fin protruding above the element isolation insulating film is covered by the local wiring VVDDLIb. Figure 6 In the cross section shown, the local wiring VVDDLIb is connected to two power supply lines VVDD01b and a wiring VVDD02b formed in the M0 layer via vias.

[0067] exist Figure 6In the cross-section shown, wiring VVDD02b in the M0 layer is connected to wiring VVDD12b formed in the M1 layer via a via. Each local wiring VVDDLIb is formed in the interlayer insulating film. The interlayer insulating film above local wiring VVDDLIb is formed with vias, power supply line VVDD01b in the M0 layer, wirings VDD02a and VVDD02b, power supply line VSS01c, and signal line SIG. Power supply line VVDD12b in the M1 layer is formed in the interlayer insulating film above the M0 layer.

[0068] As described above, in this embodiment, even when the power switch circuit PSW1 is large and the power line VVDD11b of the M1 layer is routed across the power switch circuit PSW1, the desired power supply voltage VDD can be supplied to the source region S located below the power line VVDD11b of the M1 layer. In other words, a sufficient power supply voltage VVDD can be supplied from the power switch circuit PSW1 to the standard cells without reducing the supply capacity of the power supply voltage VDD to the power switch circuit PSW1.

[0069] Furthermore, even when the power supply line VVDD11b of the M1 layer is routed in the Y direction of the power switch circuit PSW1, the repetitive structure and repetitive spacing of the source region S, gate electrode G, and drain region D can be maintained, forming a p-channel transistor PT. In this case, for example, by arranging the power supply line VVDD11b of the M1 layer at the center of the p-channel transistor PT in the X direction, the difference in distance between the six drain regions D and the power supply line VVDD11b of the M1 layer can be reduced. This reduces the variation in parasitic resistance between each drain region D and the power supply line VVDD11b of the M1 layer, allowing the power supply voltage VVDD to be efficiently supplied to the standard cell.

[0070] The arrangement pitch of the power switch circuits PSW1 is designed to be an integer multiple of the wiring pitch of the power lines VSS01c or VSS11c, or the wiring pitch of the virtual power lines VVDD01b or VVDD11b. This allows all power switch circuits PSW1 to have the same positional relationship with respect to the virtual power lines VVDD01b and VVDD11b and the power lines VSS01c and VSS11c. Consequently, layout data for the power switch circuits PSW1 that span at least one of the virtual power lines VVDD01b and VVDD11b and the power lines VSS01c and VSS11c can be shared, facilitating layout design of the power switch circuits PSW1.

[0071] (Second embodiment)

[0072] Figure 7An example of the layout of the power switch circuit of the semiconductor device in the second embodiment is shown. Figure 3 The same elements are denoted by the same reference numerals and detailed descriptions thereof are omitted. Figure 7 The layout of the semiconductor devices of the power switch circuit PSW1 shown is similar to Figure 1 The layout of the semiconductor device 100 is the same. Figure 7 The semiconductor device including the power switch circuit PSW1 shown includes a standard cell area SCA in which a plurality of standard cells are arranged in a power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0073] In this embodiment, the power supply line VVDD11b of the M1 layer, which is arranged along the Y direction in the center of the power switch circuit PSW1 in the X direction, is connected to the wiring VVDD02b of the M0 layer extending in the X direction via a via hole indicated by a diamond. As a result, the power supply voltage VVDD output from the drain region D of the p-channel transistor PT is supplied not only to the power supply line VVDD02b of the M0 layer extending in the X direction, but also to the power supply line VVDD11b of the M1 layer via the wiring VVDD02b of the M0 layer extending in the X direction. As a result, Figure 3 The power switch circuit PSW1 can improve the supply capability of the power supply voltage VVDD to the standard cell compared to the power switch circuit PSW1. Figure 7 The layout after removing the wiring of the M1 layer and the via holes between the M0 and M1 layers is the same as Figure 4 same.

[0074] As described above, this embodiment also achieves the same effects as the above-described embodiment. For example, even when the power supply line VVDD11b of the M1 layer is routed across the power switch circuit PSW1, sufficient power supply voltage VVDD can be output from the power switch circuit PSW1 without reducing the supply capacity of the power supply voltage VDD to the power switch circuit PSW1. Furthermore, in this embodiment, the power supply line VVDD11b of the M1 layer is connected to the wiring VVDD02b of the M0 layer via a via, further improving the supply capacity of the power supply voltage VVDD to the standard cells.

[0075] (Third embodiment)

[0076] Figure 8 An example of the layout of the power switch circuit of the semiconductor device in the third embodiment is shown. Figure 3 as well as Figure 7 The same elements are denoted by the same reference numerals and detailed descriptions thereof are omitted. Figure 8 The layout of the semiconductor devices of the power switch circuit PSW1 shown is similar to Figure 1The layout of the semiconductor device 100 is the same. Figure 8 The semiconductor device including the power switch circuit PSW1 shown includes a standard cell area SCA in which a plurality of standard cells are arranged in a power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0077] In this embodiment, in addition to the power supply line VVDD11b on the M1 layer extending in the Y direction, power supply line VSS11c on the M1 layer extending in the Y direction is also routed on the p-channel transistor PT. In the M1 layer, wiring VVDD12b or wiring VDD12a is positioned to avoid power supply line VSS11c on the p-channel transistor PT. Local wiring VVDDLIb located below power supply line VSS11c is connected to wiring VVDD02b extending in the X direction via a via. Wiring VVDD02b is connected to wiring VVDD12b extending in the Y direction on the p-channel transistor PT.

[0078] Wiring VVDD12b is electrically connected to power supply line VVDD01b and power supply line VVDD11b. In other words, local wiring VVDDLIb, located below power supply line VSS11c, is electrically connected to power supply line VVDD01b and power supply line VVDD11b. Power supply line VSS01c is connected to power supply line VSS11c on p-channel transistor PT via a via connecting the M0 and M1 layers, and to power supply line VSS11c located at a position that does not overlap with p-channel transistor PT when viewed from above.

[0079] For example, if the power switch circuit PSW1 is large, multiple power lines or ground lines extending in the Y direction may be arranged to overlap with the power switch circuit PSW1. In such a case, by providing an area where the wiring VDD12a or the wiring VVDD12b within the power switch circuit PSW1 is not arranged, as in this embodiment, it is possible to additionally arrange the power line VSS11c at a position overlapping with the p-channel transistor PT of the power switch circuit PSW1.

[0080] In this embodiment, also with Figure 7 Similarly, the power supply line VVDD11b of the M1 layer arranged in the center of the power switch circuit PSW1 in the X direction is connected to the wiring VVDD02b of the M0 layer extending in the X direction via the via hole shown in the diamond shape. Figure 8 The layout after removing the wiring of the M1 layer and the via holes between the M0 and M1 layers is the same as Figure 4 same.

[0081] As described above, this embodiment also achieves the same effects as the above-described embodiment. Furthermore, in this embodiment, the power supply line VSS11c of the M1 layer is routed on the power switch circuit PSW1, thereby reducing the power supply resistance of the meshed power supply line VSS that supplies the power supply voltage VSS. This improves the ability to extract the power supply voltage VSS from the standard cell via the power supply line VSS.

[0082] Furthermore, even when the power supply line VSS of the M1 layer is routed to the power switch circuit PSW1, the power supply voltage VVDD can be reliably supplied to the drain region D located below the power supply line VSS. Consequently, the ability to extract the power supply voltage VSS can be improved without reducing the ability to supply the power supply voltage VVDD to the standard cell.

[0083] (Fourth embodiment)

[0084] Figure 9 An example of the layout of the power switch circuit of the semiconductor device in the fourth embodiment is shown. Figure 3 、 Figure 7 as well as Figure 8 The same elements are denoted by the same reference numerals and detailed descriptions thereof are omitted. Figure 9 The layout of the semiconductor devices of the power switch circuit PSW1 shown is similar to Figure 1 The layout of the semiconductor device 100 is the same. Figure 9 The semiconductor device including the power switch circuit PSW1 shown includes a standard cell area SCA in which a plurality of standard cells are arranged in a power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0085] In this embodiment, in addition to the power supply line VVDD11b of the M1 layer extending in the Y direction and located in the center of the power supply switch circuit PSW1 in the X direction, another power supply line VVDD11b of the M1 layer extending in the Y direction and a power supply line VSS11c of the M1 layer extending in the Y direction are also routed on the p-channel transistor PT. In the M1 layer, the wiring VVDD12b or the wiring VDD12a is arranged at a position that avoids the other power supply line VVDD11b and the power supply line VSS11c on the p-channel transistor PT.

[0086] Local wiring VVDDLIb located below power supply line VSS11c is connected to wiring VVDD02b extending in the X direction via a via. Wiring VVDD02b is connected to wiring VVDD12b extending in the Y direction on p-channel transistor PT. Wiring VVDD12b is electrically connected to power supply lines VVDD01b and VVDD11b. Local wiring VDDLIa located below another power supply line VVDD11b is connected to wiring VDD02a extending in the X direction via a via. Wiring VDD02a is connected to wiring VDD12a extending in the Y direction on p-channel transistor PT. Wiring VDD12a is supplied with power supply voltage VDD via, for example, wiring on a layer above layer M1.

[0087] and Figure 3 as well as Figure 8 Similarly, the local wiring VDDLIa that overlaps with the power line VVDD11b or the power line VSS11c of the M1 layer is connected to the wiring VDD02a of the M0 layer extending in the X direction via a via. In addition, the wiring VVDDLIb that overlaps with the power line VVDD11b or the power line VSS11c of the M1 layer is connected to the wiring VVDD02b of the M0 layer extending in the X direction and the wiring VVDD12b of the M1 layer extending in the Y direction via a via. The wiring VVDD12b is electrically connected to the power line VVDD01b and the power line VVDD11b. In addition, from Figure 9 The layout after removing the wiring of the M1 layer and the via holes between the M0 and M1 layers is the same as Figure 4 same.

[0088] By wiring the plurality of power supply lines VVDD11b of the M1 layer to the power switch circuit PSW1, the power supply resistance of the meshed power supply line supplying the power supply voltage VVDD can be reduced. Figure 3 Compared with the power switch circuit PSW1 of the M1 layer, the supply capability of the power supply voltage VVDD supplied to the standard cells via the power supply line VVDD11b of the M1 layer can be improved.

[0089] Furthermore, by routing the power supply line VVDD11b of the M1 layer to the p-channel transistor PT, the supply capacity of the power supply voltage VVDD supplied to the standard cell can be improved. Furthermore, as the size of the power switch circuit PSW1 in the X direction increases, the number of power supply lines VVDD11b and VSS11c crossing the M1 layer on the power switch circuit PSW1 tends to increase. In this case, by applying Figure 9 The layout method shown can also improve the supply capability of the power supply voltage VVDD to the standard cell and the extraction capability of the power supply voltage VSS from the standard cell.

[0090] In addition, Figure 9In the example shown, the power lines are arranged in the order of power line VSS11c, power line VVDD11b, power line VVDD11b, power line VSS11c, and power line VSS11c along the X direction, but this is not limiting. For example, power line VSS11c or a group of multiple power lines VSS11c and power line VVDD11b or a group of multiple power lines VVDD11b may be arranged alternately along the X direction. This also applies to the third embodiment.

[0091] As described above, this embodiment also achieves the same effects as the above-described embodiment. Furthermore, in this embodiment, by routing multiple power lines VVDD in the M1 layer to the power switch circuit PSW1, the power supply resistance of the meshed power line VVDD can be reduced. Consequently, compared to the above-described embodiment, the supply capacity of the power supply voltage VVDD supplied to the standard cells via the power lines VVDD in the M1 layer can be improved. Furthermore, by routing the power line VVDD11b in the M1 layer to the p-channel transistor PT, the supply capacity of the power supply voltage VVDD supplied to the standard cells can be further improved.

[0092] (Fifth embodiment)

[0093] Figure 10 An example of the layout of the semiconductor device in the fifth embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 10 The semiconductor device 102 shown has multiple peripheral areas PA, each housing a larger RAM (Random Access Memory) 1 and a smaller RAM 2, around an end cap ECAP surrounding a standard cell area SCA within a power domain PD. RAM 1 and RAM 2 are examples of functional circuits having predetermined functions. The peripheral area PA is an example of a second area.

[0094] A plurality of power switch circuits PSW1 are arranged at intervals in the standard cell area SCA. Figure 1 Similarly, each power switch circuit PSW1 is arranged in the X direction at a pitch that is twice the wiring pitch of the virtual power lines VVDD (or ground lines VSS) arranged in the X direction. Furthermore, each power switch circuit PSW1 is arranged in the Y direction at a pitch that is four times the wiring pitch of the virtual power lines VVDD (or ground lines VSS) arranged in the Y direction.

[0095] However, in this embodiment, a predetermined number of power switch circuits PSW1 are arranged in the standard cell area SCA near RAM1 at a pitch smaller than the predetermined pitch described above. That is, in the standard cell area SCA, the frequency of power switch circuits PSW1 arranged in the area adjacent to the peripheral area PA where RAM1 is arranged is higher than the frequency of power switch circuits PSW1 arranged in other areas. By arranging power switch circuits PSW1 near RAM1 in the standard cell area SCA, the ability to supply power supply voltage VVDD to RAM1 arranged in the power domain PD can be improved.

[0096] Furthermore, even when no functional circuits such as RAM1 are arranged around the standard cell area SCA, the arrangement frequency of the power switch circuit PSW1 can be increased as in this embodiment. Specifically, for example, the arrangement frequency of the power switch circuit PSW1 can be increased in corner areas within the standard cell area SCA compared to areas inside the standard cell area SCA.

[0097] As described above, this embodiment also achieves the same effects as the above-described embodiment. Furthermore, this embodiment changes the frequency at which the power switch circuit PSW1 is configured according to the required power supply voltage VVDD, thereby enabling the appropriate power supply voltage VVDD to be supplied to a specific circuit. Furthermore, the appropriate power supply voltage VVDD can also be supplied to functional circuits such as RAM1 located in the peripheral area PA outside the standard cell area SCA.

[0098] (Sixth embodiment)

[0099] Figure 11 An example of the layout of the semiconductor device in the sixth embodiment is shown. Figure 1 as well as Figure 10 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 11 The semiconductor device 104 shown in the figure has multiple power switch circuits PSW2 arranged at the end of the RAM2 side in the X direction within the power domain PD. The structure other than the power switch circuit PSW2 is the same as that of the power switch circuit PSW1. Figure 10 The power switch circuit PSW2 is an example of a second power switch circuit.

[0100] The X-direction dimension of power switch circuit PSW2 is less than one spacing W1. Therefore, power switch circuit PSW2 can be positioned so as not to overlap with power supply lines VVDD11b and VSS11c extending in the Y-direction when viewed from above. Consequently, there is no conflict between wiring VVD12a and wiring VVDD12b on the M1 layer above p-channel transistor PT and power supply lines VVDD11b and VSS11c extending in the Y-direction.

[0101] Furthermore, even if there is no space within the standard cell area SCA for arranging the power switch circuit PSW1, the power switch circuit PSW2 can be arranged near RAM 2. In particular, the power switch circuit PSW2 can be arranged in the peripheral portion of the standard cell area SCA. As a result, for example, the ability to supply the power supply voltage VVDD to RAM 2 arranged within the power domain PD can be improved.

[0102] Figure 12 Show Figure 11 An example of the layout of the power supply wiring of the power switch circuit PSW2. Figure 3 The same elements are given the same reference numerals and detailed descriptions are omitted. Figure 12 In the description of the power switch control circuit that generates the control voltage output to the signal line SIG connected to the gate electrode G of the power switch circuit PSW2, the description of the power switch control circuit that generates the control voltage output to the signal line SIG connected to the gate electrode G of the power switch circuit PSW2 is omitted. The function and operation of the power switch control circuit that controls the operation of the power switch circuit PSW2 are similar to those of the power switch control circuit PSW2. Figure 2 The functions and actions of the power switch control circuit PCNT1 shown in FIG. Figure 12 In the example shown in FIG. 1 , the power supply line VSS11 c extending in the Y direction is wired on the left side, and the power supply line VVDD11 b extending in the Y direction is wired on the right side, but the present invention is not limited thereto.

[0103] The power switch circuit PSW2 includes a plurality of p-channel transistors PT having eight fins extending in the X direction and four gate electrodes G extending in the Y direction. Dummy gate electrodes DMYG are arranged on both sides of the arrangement region of the four gate electrodes G in the X direction.

[0104] The power switch circuit PSW2 is similar to the power switch circuit PSW1 except that a p-channel transistor PT having four gate electrodes G is provided instead of the p-channel transistor PT having ten gate electrodes G. Figure 3 That is, in the p-channel transistor PT, the wiring and the via connected to the gate electrode G, the source region S, and the drain region D are the same as Figure 3The power switch circuit PSW2 is arranged in the same positional relationship with the power supply lines VVDD and VSS. This allows the layout data of the power switch circuit PSW2 to be shared, making the layout design of the power switch circuit PSW1 easier.

[0105] As described above, this embodiment also achieves the same effects as the above-described embodiment. Furthermore, this embodiment allows the placement of power switch circuit PSW2, which is smaller than power switch circuit PSW1, in the peripheral portion of the standard cell area SCA where power switch circuit PSW1 cannot be placed. As a result, for example, the ability to supply power supply voltage VVDD to RAM2 located within power domain PD can be improved.

[0106] In addition, although the above-mentioned embodiment is described as an example of being applied to power switch circuits PSW1 and PSW2 having finFETs, it can also be applied to power switch circuits having planar transistors, nanowire transistors, nanosheet transistors, fork-sheet transistors, CFETs (Complementary FETs: complementary field-effect transistors), vertical nanowire transistors, etc.

[0107] While the present invention has been described above based on the various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified within the scope of the present invention and can be appropriately determined according to the application.

Claims

1. A semiconductor device comprising: A first power line is formed in the first wiring layer and extends in a first direction when viewed from above; A second power line is formed in the first wiring layer and extends in the first direction; a third power line formed in a second wiring layer, extending in a second direction different from the first direction in a plan view, and connected to the first power line, the second wiring layer being a wiring layer above the first wiring layer; a fourth power line, formed in the second wiring layer, extending in the second direction and connected to the second power line; a fifth power line formed in the first wiring layer; and The first power switch circuit includes a transistor disposed between the first power line and the fifth power line. The transistor is located at a position overlapping at least one of the third power line and the fourth power line in a plan view, The first power switch circuit has: a first wiring formed in the second wiring layer, electrically connected to the source region of the transistor and the fifth power line, extending in the second direction, on the transistor and not overlapping with the third power line and the fourth power line in a plan view; and The second wiring is formed in the second wiring layer, is electrically connected to the drain region of the transistor and the third power line, extends in the second direction, is on the transistor and does not overlap with the third power line and the fourth power line when viewed from above.

2. The semiconductor device according to claim 1, wherein The first power switch circuit includes a third wiring extending in the first direction on the transistor and electrically connected to the drain region and the second wiring. On the transistor, the third power supply line and the third wiring are connected via a via hole.

3. The semiconductor device according to claim 1 or 2, wherein: The fourth power line is connected to the second power line via a via hole on the transistor.

4. The semiconductor device according to any one of claims 1 to 3, wherein: There are a plurality of the third power lines and a plurality of the fourth power lines, having a plurality of the above-mentioned first power switch circuits, The third power line and the fourth power line are repeatedly arranged at a first pitch in the first direction, The positions of the transistors of the plurality of first power switch circuits overlapping at least one of the third power line and the fourth power line in a plan view are identical to each other.

5. The semiconductor device according to any one of claims 1 to 4, wherein: A first area is provided, wherein the first area has the first power line, the second power line, the third power line, the fourth power line, and the first power switch circuit, and is provided with a logic circuit. The first region includes a portion where the arrangement frequency of the first power switch circuit is higher than that of the other portions.

6. The semiconductor device according to claim 5, wherein: having a second region adjacent to the first region and having a functional circuit different from the logic circuit, The portion with a higher arrangement frequency is adjacent to the second region.

7. The semiconductor device according to claim 5 or 6, wherein: A second power switch circuit is provided, the second power switch circuit being arranged in the first region and including a transistor that does not overlap with the third power line and the fourth power line in a plan view.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The above transistors are finFETs.

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