Semiconductor devices and methods

Abstract

The present disclosure relates generally to semiconductor devices and methods. Embodiments include a device having a nanostmcture on a substrate, the nanostmcture including a channel region. The device also includes a gate dielectric layer surrounding each nanostmcture. The device also includes a first work function adjustment layer on the gate dielectric layer, the first work function adjustment layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes an adhesion layer on the first work function adjustment layer. The device also includes a fill layer on the adhesion layer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a nanostructure located on a substrate, the nanostructure including a channel region; a gate dielectric layer surrounding each of the nanostructures; a first work function adjustment layer located on the gate dielectric layer, the first work function adjustment layer comprising a first n-type work function metal, aluminum, and carbon, wherein the work function value of the first n-type work function metal is less than that of titanium; an adhesive layer located on the first work function adjustment layer; and a filler layer located on the adhesive layer.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region; forming a first gate dielectric layer on the first channel region; forming a first work function adjustment layer on the first gate dielectric layer, the first work function adjustment layer including zirconium, hafnium, niobium, tantalum, or a combination thereof; forming a first barrier layer on the first work function adjustment layer, the first barrier layer being formed in situ with the first work function adjustment layer; forming an adhesive layer on the first barrier layer; and forming a filler layer on the adhesive layer.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region; forming a gate dielectric layer having a first portion and a second portion, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region; forming an n-type work function adjustment layer on the first portion and the second portion of the gate dielectric layer, the n-type work function adjustment layer surrounding each of the first set of nanostructures; forming a first barrier layer on and in situ with the n-type work function adjustment layer; removing the first barrier layer and the n-type work function adjustment layer from the second portion of the gate dielectric layer; forming a p-type work function adjustment layer on the first barrier layer on the first set of nanostructures and on the second portion of the gate dielectric layer; and forming a fill layer on the p-type work function adjustment layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figures 2 to 24B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 25 This is a flowchart of an example method for forming a replacement gate for a nanostructured FET, according to some embodiments.

[0011] Figure 26 This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0012] Figure 27 This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0013] Figure 28 This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0016] According to various embodiments, the gate electrode is formed with an active function adjustment layer. In some embodiments, the n-type device has an active function adjustment layer comprising Zr, Hf, Nb, Ta, or combinations thereof. These active function adjustment layers reduce the active function value and further shift the effective active function value to the n-type. These changes can improve the threshold voltage of the resulting n-type device.

[0017] Embodiments are described in the specific context of dies that include nanostructured FETs. However, various embodiments can be applied to dies that replace or incorporate other types of transistors (e.g., FinFETs, planar transistors, etc.) in conjunction with nanostructured FETs.

[0018] Figure 1 Examples of nanostructured FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1 This is a 3D view, in which some features of the nanostructure FET have been omitted for clarity. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), etc.

[0019] The nanostructured FET includes a nanostructure 66 (e.g., nanosheet, nanowire, etc.) on fins 62 on a substrate 50 (e.g., a semiconductor substrate), and the nanostructure 66 serves as the channel region of the nanostructured FET. The nanostructure 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62, which may protrude above and between adjacent isolation regions 70. Although the isolation regions 70 are shown / described as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 62 is shown as a single continuous material with respect to the substrate 50, the bottom portion of the fin 62 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 62 refers to the portion extending above and between adjacent isolation regions 70.

[0020] Gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 124 is located above gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62 on opposite sides of gate dielectric 122 and gate electrode 124. Epitaxial source / drain regions 98 can be shared between different fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by agglomerating epitaxial source / drain regions 98 by epitaxial growth, or by coupling epitaxial source / drain regions 98 to the same source / drain contact.

[0021] Figure 1 Reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section B-B' is along the longitudinal axis of the fin 62 and in, for example, the direction of current flow between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nanostructure FET. For clarity, the following figures refer to these reference cross sections.

[0022] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments relate to aspects used in planar devices (e.g., planar FETs) or in fin field-effect transistors (FinFETs). For example, a FinFET may include fins located on a substrate, and these fins serve as the channel region of the FinFET. Similarly, a planar FET may include a substrate, and portions of the substrate serve as the channel region of the planar FET.

[0023] Figures 2 to 24B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 23A , Figure 24A , Figure 26 and Figure 27 It shows Figure 1 The reference section A-A' shown is different in that it shows two fins. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 22B , Figure 23B and Figure 24B Show Figure 1 The reference section B-B' is shown. Figure 9C and Figure 9D It shows Figure 1The reference section C-C' shown differs in that it shows two fins.

[0024] exist Figure 2 In this embodiment, a substrate 50 is provided for forming a nanostructure FET. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or combinations thereof.

[0025] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0026] The substrate 50 may be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and p-type region 50P. The APT region may extend below the source / drain regions in the nanostructured FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be 10-1. 18 cm -3 Up to 10 19 cm -3 Within the range.

[0027] A multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers each of the first semiconductor layer 54 and the second semiconductor layer 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0028] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form channel regions for a nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity relative to the etching of the second semiconductor layer 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0029] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductor, II-VI compound semiconductor, etc. The etching of the first semiconductor material and the second semiconductor material relative to each other can have high etch selectivity, so that the first semiconductor layer 54 can be removed in the n-type region 50N without removing the second semiconductor layer 56, and the second semiconductor layer 56 can be removed in the p-type region 50P without removing the first semiconductor layer 54.

[0030] Each layer of the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form a channel region for a nanostructured FET in both the n-type region 50N and the p-type region 50P, the first semiconductor layer 54 can have a first thickness T1 and the second semiconductor layer 56 can have a second thickness T2, and the second thickness T2 is 30% to 60% smaller than the first thickness T1. Forming the second semiconductor layer 56 to a smaller thickness allows for the formation of the channel region at a higher density.

[0031] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fin 62 is a semiconductor strip patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 respectively comprise the remainders of the first semiconductor layer 54 and the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0032] The fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins 62 and nanostructures 64, 66, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on the nanostructures 64, 66.

[0033] Fins 62 and nanostructures 64, 66 may each have a width ranging from 8 nm to 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) may be wider or narrower than fins 62 and nanostructures 64, 66 in another region (e.g., p-type region 50P).

[0034] exist Figure 4 In this embodiment, STI regions 70 are formed on substrate 50 and between adjacent fins 62. The STI regions 70 are disposed around at least a portion of the fins 62 such that at least a portion of the nanostructures 64, 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI regions 70 separate features of adjacent devices.

[0035] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process, such as high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In embodiments, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although each of the STI regions 70 is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material such as described above can be formed on the liner.

[0036] A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 64, 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, or a combination thereof, may be employed. This planarization process exposes the nanostructures 64, 66 such that, after the planarization process is completed, the top surfaces of the nanostructures 64, 66 and the insulating material are coplanar (within a process variation). In embodiments where a mask is retained on the nanostructures 64, 66, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surfaces of the mask or the nanostructures 64, 66 are coplanar with the top surface of the insulating material, respectively (within a process variation). The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes from between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of STI region 70 can be formed as flat, convex, and / or concave by appropriate etching. The insulating material can be recessed using any acceptable etching process, such as a material-selective etching process for the insulating material (e.g., selectively etching the insulating material of STI region 70 at a faster rate than the materials of fins 62 and nanostructures 64, 66). For example, dilute hydrofluoric acid (dHF) can be used to perform oxide removal.

[0037] The previously described process is merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structures can include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structures are epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0038] Furthermore, suitable wells (not shown separately) may be formed in the substrate 50, fins 62, and / or nanostructures 64, 66. These wells may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0039] In embodiments with different well types, masks (not shown separately) such as photoresists can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0040] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0041] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures are grown for fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation, but in-situ doping and implantation doping can be used together.

[0042] exist Figure 5 In this process, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited on the dummy gate layer 74. The dummy gate layer 74 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed of one or more materials with high etch selectivity relative to the etching of the isolation material (e.g., STI region 70 and / or dummy dielectric layer 72). The mask layer 76 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and STI region 70, such that the dummy dielectric layer 72 extends over the STI region 70 and between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and nanostructures 64, 66.

[0043] exist Figure 6In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 by any acceptable etching technique to form dummy gate 84. The pattern of mask 86 may optionally be further transferred to dummy dielectric layer 72 by any acceptable etching technique to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66 that will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of nanostructure 66 that will be patterned to form channel regions 68. The pattern of mask 86 may be used to physically separate adjacent dummy gates 84. Dummy gate 84 may also have a length direction substantially perpendicular to the length direction of fin 62 (within process variations). Mask 86 may optionally be removed after patterning, for example, by any acceptable etching technique.

[0044] Figures 7A to 22B Various additional steps in manufacturing the embodiment device are shown. Figures 7A to 13B and Figures 21A to 22B Features of either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Structural differences between the n-type region 50N and the p-type region 50P (if any) are described in the text of each figure. Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The characteristics of the n-type region 50N are shown. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B Features in the p-type region 50P are shown.

[0045] exist Figure 7A and Figure 7BIn this embodiment, gate spacers 90 are formed on nanostructures 64, 66, on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric material(s). Acceptable dielectric materials include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or combinations thereof, such as silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, etc.; and multilayers thereof. The dielectric materials can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In the illustrated embodiment, each gate spacer 90 comprises multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-y (where x and y are in the range of 0 to 1). For example, the first spacer layer 90A may be formed of silicon carbonitride with a similar or different composition from the second spacer layer 90B. An acceptable etching process (e.g., dry etching, wet etching, or a combination thereof) may be performed to pattern the dielectric material(s). The etching may be anisotropic. During etching, some portions of the dielectric material(s) remain on the sidewalls of the dummy gate 84 (thus forming the gate spacer 90). After etching, the gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown). As will be described in more detail later, during etching, some portions of the dielectric material(s) may remain on the sidewalls of the fins 62 and / or nanostructures 64, 66 (thus forming fin spacers).

[0046] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for wells, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. During implantation, the channel region 68 remains covered by the dummy gate 84, ensuring that the channel region 68 remains substantially free of impurities implanted to form the LDD region. The LDD region can have 10 15 cm -3 Up to 10 19 cm -3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0047] Note that previous disclosures generally describe the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0048] exist Figure 8A and Figure 8BIn the illustrated embodiment, source / drain recesses 94 are formed in nanostructures 64, 66. In this embodiment, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of substrate 50 without etching substrate 50; fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is set below the top surface of STI region 70; and so on. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recesses 94, gate spacer 90 and dummy gate 84 jointly mask fin 62 and / or portions of nanostructures 64, 66. Each nanostructure 64, 66 can be etched using a single etching process, or multiple etching processes can be used to etch the nanostructures 64, 66. A timed etching process can be used to stop etching the source / drain recess 94 after it has reached the desired depth.

[0049] Optionally, internal spacers 96 are formed on the sidewalls of the remainder of the first nanostructure 64, such as those exposed by the source / drain recesses 94. As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recesses 94, and the first nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for the subsequent removal of the first nanostructure 64).

[0050] As an example of forming the internal spacer 96, the source / drain recess 94 can extend laterally. Specifically, the portion of the sidewalls of the first nanostructure 64 exposed by the source / drain recess 94 can be recessed. Although the sidewalls of the first nanostructure 64 are shown as straight, these sidewalls can be concave or convex. The sidewalls can be recessed by any acceptable etching process, such as an etching process selective to the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF). In some embodiments, the same etching process can be continuously performed to both form the source / drain recess 94 and recess the sidewalls of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching that insulating material. The insulating material can be silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low-k) material with a k-value less than 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer wall of the internal spacer 96 is shown as flush with the sidewall of the gate spacer 90, the outer wall of the internal spacer 96 can extend beyond or be recessed from the sidewall of the gate spacer 90. In other words, the internal spacer 96 can partially fill, fully fill, or overfill the sidewall recess. Furthermore, although the sidewall of the internal spacer 96 is shown as straight, the sidewall of the internal spacer 96 can be concave or convex.

[0051] exist Figure 9A and Figure 9B In this process, an epitaxial source / drain region 98 is formed in the source / drain recess 94. The epitaxial source / drain region 98 is formed in the source / drain recess 94 such that each dummy gate 84 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gate 84 and the first nanostructure 64 by appropriate lateral distances, such that the epitaxial source / drain regions 98 do not short-circuit with the subsequently formed gate of the resulting nanostructure FET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel region 68, thereby improving performance.

[0052] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 98 in the n-type region 50N is epitaxially grown in the source / drain recess 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material on which tensile strain is applied to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 98 in the n-type region 50N can have a surface that protrudes relative to the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0053] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 98 in the p-type region 50P is epitaxially grown in the source / drain recess 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P can have a surface that protrudes relative to the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0054] The epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form the source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration in the source / drain regions can be up to 10. 19 cm -3 Up to 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously described impurities. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0055] As a result of the epitaxial process used to form the epitaxial source / drain regions 98, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge, such as... Figure 9C As shown. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after the epitaxial process is completed, as... Figure 9DAs shown. In the illustrated embodiment, the spacer etching used to form the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover the extension of the sidewalls of fins 62 and / or nanostructures 64, 66 above a portion of the STI region 70, thereby preventing epitaxial growth. In another embodiment, the spacer etching used to form the gate spacer 90 is adjusted to not form fin spacers, thereby allowing the epitaxial source / drain region 98 to extend to the surface of the STI region 70.

[0056] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 98 may each include a liner layer 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the liner layer 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the liner layer 98A may have a lower impurity concentration than the main layer 98B, and the finishing layer 98C may have a higher impurity concentration than the liner layer 98A and a lower impurity concentration than the main layer 98B. In an embodiment where the epitaxial source / drain region 98 includes three semiconductor material layers, a liner layer 98A can be grown in the source / drain recess 94, a main layer 98B can be grown on the liner layer 98A, and a finishing layer 98C can be grown on the main layer 98B.

[0057] exist Figure 10A and Figure 10B In this configuration, a first interlayer dielectric (ILD) 104 is deposited over the epitaxial source / drain region 98, gate spacer 90, mask 86 (if present), or dummy gate 84. The first ILD 104 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0058] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., exhibiting high etch selectivity relative to the etching of the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0059] exist Figure 11A and Figure 11B In this process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be employed. This planarization process may also remove the mask 86 on the dummy gate 84, as well as portions of the gate spacer 90 along the sidewalls of the mask 86. After this planarization process, the gate spacer 90, the first ILD 104, CESL 102, and the top surfaces of the mask 86 (if present) or the dummy gate 84 are coplanar (within process variations). Therefore, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0060] exist Figure 12A and Figure 12B In the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 110. A portion of the dummy dielectric 82 in the recess 110 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 at a rate faster than the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may be used as an etch stop layer while etching the dummy gate 84. The dummy dielectric 82 is then removed. Each recess 110 exposes and / or covers a portion of the channel region 68. The portion of the second nanostructure 66 serving as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 98.

[0061] Then, the remaining portion of the first nanostructure 64 is removed to enlarge the recess 110. The remaining portion of the first nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructure 64 at a faster rate than the material of the second nanostructure 66. This etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the second nanostructure 66. Figures 14A to 21B As shown more clearly (and described in more detail later), the remainder of the second nanostructure 66 may have rounded corners.

[0062] exist Figure 13A and Figure 13B In the recess 110, a gate dielectric layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers used to replace the gate and each surrounds all (e.g., four) sides of the second nanostructure 66.

[0063] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the second nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the first ILD 104 and the gate spacer 90. The gate dielectric layer 112 may comprise oxides (e.g., silicon oxide or metal oxides), silicates (e.g., metal silicates), combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may comprise a dielectric material with a k-value greater than 7.0, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, metal oxides or silicates. Although in Figure 13A and Figure 13B A single-layer gate dielectric layer 112 is shown, but as will be described in more detail later, the gate dielectric layer 112 may include an interface layer and a main layer.

[0064] The gate electrode layer 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, ZrAl, HfAl, NbAl, TaAl, ZrSiC, HfSiC, NbSiC, combinations thereof, or multiple layers thereof. Although in Figure 13A and Figure 13B The diagram shows a single gate electrode layer 114, but as will be described in more detail later, the gate electrode layer 114 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler material.

[0065] Figures 14A to 21B The process of forming a layer for replacing the gate in the recess 110 is shown. A comparison with... Figure 13A Features in regions similar to 50R. Figure 25 This is a flowchart of an example method 200 for forming a replacement gate layer according to some embodiments. (In conjunction with...) Figure 25 Described Figures 14A to 21B When forming the replacement gate layer, a first work function adjustment layer 114 is formed in a first region (e.g., n-type region 50N) (see...). Figure 15A Then, one or more second work function adjustment layers 114C are formed in both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). (See also...) Figure 19A and Figure 19B Since the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P) include different numbers and types of work function adjustment layers, the devices formed in these regions have different threshold voltages.

[0066] exist Figure 14A and Figure 14B In step 202 of method 200, the gate dielectric layer 112 is deposited in the recess 110 of both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). The gate dielectric layer 112 may also be deposited on the top surface of the first ILD 104 and the gate spacer 90 (see...). Figure 13B In the illustrated embodiment, the gate dielectric layer 112 is multilayered, comprising an interface layer 112A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 112B (or more generally, a second gate dielectric layer). The interface layer 112A may be formed of silicon oxide, and the high-k dielectric layer 112B may be formed of hafnium oxide. Methods for forming the gate dielectric layer 112 may include molecular beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 112 surrounds all (e.g., four) sides of the second nanostructure 66.

[0067] exist Figure 15A and Figure 15BIn step 204 of method 200, a first work function adjustment layer 114A is deposited on the gate dielectric layer 112 in both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P). As will be described in more detail later, the first work function adjustment layer 114A is patterned to remove a portion of the first work function adjustment layer 114A in the second region (e.g., p-type region 50P), while retaining a portion of the first work function adjustment layer 114A in the first region (e.g., n-type region 50N). When the first work function adjustment layer 114A is removed from the second region (e.g., p-type region 50P), it may be referred to as an "n-type work function adjustment layer". The first work function adjustment layer 114A comprises any acceptable material to adjust the work function of the device to a desired amount for the application of the device to be formed, and can be deposited using any acceptable deposition process. For example, when the first work function adjustment layer 114A is an n-type work function adjustment layer, it can be formed from an n-type work function metal (NWFM) such as aluminum zirconium carbide (ZrAlC), aluminum hafnium carbide (HfAlC), aluminum niobium carbide (NbAlC), aluminum tantalum carbide (TaAlC), ZrAl, HfAl, NbAl, TaAl, ZrSiC, HfSiC, NbSiC, etc., or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. Although the first work function adjustment layer 114A is shown as a single layer, the first work function adjustment layer 114A can be multilayered. For example, the first work function adjustment layer 114A may include: a first layer of ZrAlC and a second layer of HfAlC; a first layer of ZrAlC, a second layer of HfAlC and a third layer of ZrAlC; a first layer of HfAlC, a second layer of ZrAlC and a third layer of HfAlC; a first layer of ZrAl, a second layer of HfAl and a third layer of NbAl; a first layer of ZrSiC, a second layer of HfSiC and a third layer of NbSiC; or a combination thereof.

[0068] In both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P), the first work function adjustment layer 114A is formed to a thickness sufficient to allow the portions of the first work function adjustment layer 114A between the second nanostructures 66 to merge. As a result, the portion 110M of the recess 110 between the second nanostructures 66... N 110M P The first work function adjustment layer 114A completely fills the area. In both the first region (e.g., n-type region 50N) and the second region (e.g., p-type region 50P), a corresponding portion of the gate dielectric layer 112 surrounds each second nanostructure 66, and a corresponding portion of the first work function adjustment layer 114A fills the region between the corresponding portions of the gate dielectric layer 112. In some embodiments, the first work function adjustment layer 114A is formed as... to Thickness within a certain range, for example, in to Within the range. The first work function adjustment layer 114A is formed to be less than The thickness may not cause partial merging of the first work function adjustment layer 114A. The first work function adjustment layer 114A is formed to be larger than... The thickness of the layer may negatively affect the threshold voltage of the resulting device. In some embodiments, the ratio of the thickness of the first work function adjustment layer 114A to the thickness of the interface layer 112A is in the range of 0.5 to 7.

[0069] The aluminum in the first work function adjustment layer 114A forms an aluminum dipole at the interface between the high-k dielectric layer 112B and the first work function adjustment layer 114A, which will form an aluminum dipole in the gate electrode layer 114 (see example). Figure 19A The effective work function of titanium shifts further towards the n-type work function value. Another metal in the first work function adjustment layer 114A (e.g., zirconium, hafnium, niobium, or tantalum) has a lower effective work function (eV) value than titanium, thus contributing to a further shift of the effective work function towards the n-type work function value.

[0070] In some embodiments, the first work function adjustment layer 114A is formed of aluminum zirconium carbide, which is deposited by an ALD process. Specifically, the first work function adjustment layer 114A may be formed as follows: a substrate 50 is placed in a deposition chamber, and various source precursors are cyclically dispensed into the deposition chamber. A first pulse of the ALD cycle is performed by dispensing a zirconium source precursor into the deposition chamber. Acceptable zirconium source precursors include zirconium chloride (ZrCl4), etc. The first pulse may be performed at a temperature in the range of 200°C to 500°C and a pressure in the range of 0.5 Torr to 45 Torr, for example, by maintaining the deposition chamber at such temperature and pressure. The first pulse may be performed for a duration in the range of 0.1 seconds to 60 seconds, for example, by holding the zirconium source precursor in the deposition chamber for such a duration. The zirconium source precursor is then removed from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas (e.g., argon or nitrogen) into the deposition chamber. A second pulse of the ALD cycle is performed by dispensing an aluminum source precursor into the deposition chamber. Acceptable aluminum source precursors include triethylaluminum (TEA) (Al2(C2H5)6), trimethylaluminum (TMA) (Al2(CH3)6), and combinations thereof. The second pulse can be performed at a temperature ranging from 200°C to 500°C and a pressure ranging from 0.5 Torr to 45 Torr, for example, by maintaining the deposition chamber at such temperature and pressure. The second pulse can be performed for a duration ranging from 0.1 seconds to 60 seconds, for example, by holding the aluminum source precursor in the deposition chamber for such a duration. The aluminum source precursor is then removed from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas (e.g., argon or nitrogen) into the deposition chamber. Each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of aluminum zirconium carbide. The ALD cycle is repeated until the first work function adjustment layer 114A has the desired thickness (as previously described). The ALD cycle can be repeated 5 to 180 times. Performing the ALD process with parameters within these ranges allows the first work function adjustment layer 114A to be formed to the desired thickness (previously described) and quality. Performing the ALD process with parameters outside these ranges may not allow the first work function adjustment layer 114A to be formed to the desired thickness or quality.

[0071] In some embodiments, the first work function adjustment layer 114A may include aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, or combinations thereof, wherein each material is deposited by an ALD process. The ALD process used to form these materials may be similar to the ALD process for aluminum zirconium carbide discussed above, wherein the zirconium source precursor is replaced by a suitable source precursor (e.g., hafnium, niobium, or tantalum source precursor), and the details of the ALD process will not be repeated here.

[0072] In embodiments involving hafnium aluminum carbide, the first pulse of the ALD cycle is performed by dispensing a hafnium source precursor into the deposition chamber. Acceptable hafnium source precursors include hafnium chloride (HfCl4), etc.

[0073] In embodiments including aluminum niobium carbide, the first pulse of the ALD cycle is performed by dispensing a niobium source precursor into the deposition chamber. Acceptable niobium source precursors include niobium chloride (NbCl5), etc.

[0074] In embodiments including aluminum tantalum carbide, the first pulse of the ALD cycle is performed by dispensing a tantalum source precursor into the deposition chamber. Acceptable tantalum source precursors include tantalum chloride (TaCl5), etc.

[0075] exist Figure 16A and Figure 16B In step 206 of method 200, an in-situ layer 114B is deposited on the first work function adjustment layer 114A. The in-situ layer 114B is formed in situ (e.g., in the same chamber as the first work function adjustment layer 114A and / or in a separate chamber on the same system, without vacuum disruption between the formation of layers 114A and 114B). In some embodiments, the in-situ layer 114B acts as a barrier or protective layer for the first work function adjustment layer 114A, such that the in-situ layer 114B suppresses (e.g., substantially prevents or at least reduces) changes in the work function of the first work function adjustment layer 114A during subsequent processing. In some embodiments, the in-situ layer 114B is formed of titanium nitride (TiN) or the like, and can be deposited by ALD, CVD, PVD, etc. In some embodiments, the in-situ layer 114B is omitted (see, for example...). Figure 26 ).

[0076] exist Figure 17A and Figure 17B In step 208 of method 200, a portion of the in-situ layer 114B and the first work function adjustment layer 114A is removed from the second region (e.g., p-type region 50P). Removing a portion of the in-situ layer 114B and the first work function adjustment layer 114A from the second region (e.g., p-type region 50P) expands the recess 110 in the second region to re-expose the gate dielectric layer 112 in the second region (e.g., p-type region 50P). This removal can be performed using acceptable photolithography and etching techniques, for example, by covering the second region with a mask and etching the first region. Etching can include any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic.

[0077] In some embodiments, a single etch is performed to remove portions of the in-situ layer 114B and the first work function adjustment layer 114A. This single etch may be selective for the materials of the in-situ layer 114B and the first work function adjustment layer 114A (e.g., selectively etching the materials of the in-situ layer 114B and the first work function adjustment layer 114A at a faster rate than one or more materials of the gate dielectric layer 112). For example, when the in-situ layer 114B is formed of titanium nitride and the first work function adjustment layer 114A is formed of aluminum zirconium carbide, both can be removed by wet etching using ammonium hydroxide (NH4OH).

[0078] In some embodiments, a first etching is performed to remove a portion of the in-situ layer 114B, and a second etching is performed to remove a portion of the first work function adjustment layer 114A. The first etching may be selective for the in-situ layer 114B (e.g., selectively etching the material of the in-situ layer 114B at a faster rate than the material of the first work function adjustment layer 114A). For example, when the in-situ layer 114B is formed of amorphous silicon, it can be removed by wet etching using dilute hydrofluoric acid (dHF). The second etching may be selective for the first work function adjustment layer 114A (e.g., selectively etching the material of the first work function adjustment layer 114A at a faster rate than the material of the gate dielectric layer 112). For example, when the first work function adjustment layer 114A is formed of aluminum zirconium carbide, it can be removed by wet etching using ammonium hydroxide (NH4OH).

[0079] exist Figure 18A and Figure 18BIn step 210 of method 200, a second work function adjustment layer 114C is deposited on in-situ layer 114B in a first region (e.g., n-type region 50N) and on gate dielectric layer 112 in a second region (e.g., p-type region 50P). As will be described in more detail later, a p-type device will be formed having the second work function adjustment layer 114C in the second region (e.g., p-type region 50P), and an n-type device will be formed having a first work function adjustment layer 114A and a second work function adjustment layer 114C in the first region (e.g., n-type region 50N). When the second work function adjustment layer 114C is the only work function adjustment layer in the second region (e.g., p-type region 50P), it may be referred to as a "p-type work function adjustment layer". The second work function adjustment layer 114C comprises any acceptable material to adjust the work function of the device to a desired amount for the application of the device to be formed, and can be deposited using any acceptable deposition process. For example, when the second work function adjustment layer 114C is a p-type work function adjustment layer, it can be formed from a p-type work function metal (PWFM) such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, and can be deposited by ALD, CVD, PVD, etc. Although the second work function adjustment layer 114C is shown as a single layer, it can be multilayered. For example, the second work function adjustment layer 114C may include a titanium nitride (TiN) layer and a tantalum nitride (TaN) layer.

[0080] The second work function adjustment layer 114C can serve as an adhesive layer in the first region (e.g., n-type region 50N). The second work function adjustment layer 114C can improve adhesion to the subsequently formed filler layer 114D and also prevent diffusion to surrounding layers. In some embodiments, a separate adhesive layer is formed in the first region (e.g., n-type region 50N) (see, for example...). Figure 20A and Figure 21A In 114E), and the second function adjustment layer 114C does not perform this function.

[0081] In the second region (e.g., p-type region 50P), the second work function adjustment layer 114C is formed to a thickness sufficient to allow the portions of the second work function adjustment layer 114C between the second nanostructures 66 to merge. As a result, the portion 110M of the recess 110 between the second nanostructures 66... P The second work function adjustment layer 114C completely fills the area. In the second region (e.g., p-type region 50P), corresponding portions of the gate dielectric layer 112 surround each second nanostructure 66, and corresponding portions of the second work function adjustment layer 114C fill the region between corresponding portions of the gate dielectric layer 112. In some embodiments, the second work function adjustment layer 114C is formed as follows: to Thickness within a certain range, for example, in to Within the range. The second work function adjustment layer 114C is formed to be less than The thickness may not cause partial merging of the second work function adjustment layer 114C. Forming the second work function adjustment layer 114C to be larger than... The thickness of the material may have a negative impact on the threshold voltage of the resulting device.

[0082] The material of the first work function adjustment layer 114A is different from the material of the second work function adjustment layer 114C. As described above, the first work function adjustment layer 114A can be formed of an n-type work function metal (NWFM), and the second work function adjustment layer 114C can be formed of a p-type work function metal (PWFM). NWFM is different from PWFM. Furthermore, in some embodiments, the material of the in-situ layer 114B is different from the material of the first work function adjustment layer 114A and the second work function adjustment layer 114C.

[0083] exist Figure 19A and Figure 19B In step 212 of method 200, the fill layer 114D is deposited on the second work function adjustment layer 114C. After formation is complete, the gate electrode layer 114 includes a first work function adjustment layer 114A, an in-situ layer 114B, a second work function adjustment layer 114C, and a fill layer 114D.

[0084] The filler layer 114D comprises any acceptable low-resistivity material. For example, the filler layer 114D can be formed of metals such as tungsten, aluminum, cobalt, ruthenium, or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The filler layer 114D fills the remaining portion of the recess 110.

[0085] Figure 20A and Figure 20B An embodiment is illustrated in which an adhesive layer 114E is included between a second work function adjustment layer 114C and an in-situ layer 114B in a first region (e.g., n-type region 50N). In some embodiments, the adhesive layer 114E may be formed before the formation of the second work function adjustment layer 114C and removed from the second region (e.g., p-type region 50P), or masking techniques may be used to prevent the formation of the adhesive layer 114E in the second region (e.g., p-type region 50P). The adhesive layer 114E comprises any acceptable material to promote adhesion and prevent diffusion. For example, the adhesive layer 114E may be formed of a metal or metal nitride, such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, etc., which may be deposited by ALD, CVD, PVD, etc.

[0086] Figure 21A and Figure 21B An embodiment is shown that includes an adhesive layer 114E in a first region (e.g., n-type region 50N), but does not include a second work function adjustment layer 114C in the first region (e.g., n-type region 50N). In some embodiments, the second work function adjustment layer 114C may be formed and removed from the first region (e.g., n-type region 50N), or masking techniques may be used to prevent the second work function adjustment layer 114C from being formed in the first region (e.g., n-type region 50N).

[0087] exist Figure 22A and Figure 22B In this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114 (these excess portions are above the top surfaces of the first ILD 104 and the gate spacer 90), thereby forming the gate dielectric 122 and the gate electrode 124. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be employed. During planarization, some portions of the gate dielectric layer 112 remain in the recess 110 (thus forming the gate dielectric 122). During planarization, some portions of the gate electrode layer 114 remain in the recess 110 (thus forming the gate electrode 124). Gate spacer 90, CESL 102, first ILD 104, gate dielectric 122 (e.g., interface layer 112A and high-k dielectric layer 112B, see...) Figure 19A-21B ), and gate electrode 124 (e.g., first work function adjustment layer 114A, in-situ layer 114B, second work function adjustment layer 114C, adhesive layer 114E and filler layer 114D, see Figure 19A-21B The top surfaces of the two nanostructures 66 are coplanar (within process variations). The gate dielectric 122 and the gate electrode 124 form the replacement gate of the resulting nanostructure FET. Each corresponding pair of gate dielectric 122 and gate electrode 124 may be collectively referred to as a “gate structure”. The gate structures each extend along the top surface, sidewalls and bottom surface of the channel region 68 of the second nanostructure 66.

[0088] exist Figure 23A and Figure 23B In this configuration, the second ILD 134 is deposited over the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0089] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material having high etch selectivity relative to the etching of the second ILD 134, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0090] exist Figure 24A and Figure 24B In this configuration, a gate contact 142 and a source / drain contact 144 are formed to contact the gate electrode 124 and the epitaxial source / drain region 98, respectively. The gate contact 142 is physically coupled and electrically coupled to the gate electrode 124. The source / drain contact 144 is physically coupled and electrically coupled to the epitaxial source / drain region 98.

[0091] As an example of forming the gate contact 142 and the source / drain contact 144, an opening for the gate contact 142 is formed through the second ILD 134 and ESL 132, and an opening for the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or adhesion layer, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 in the openings. The gate contact 142 and the source / drain contact 144 can be formed using different processes or the same process. Although shown to be formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in a different cross section, which can prevent short circuits in the contacts.

[0092] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanium region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanium region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings of the source / drain contact 144 (e.g., from the surface of the metal-semiconductor alloy region 146). Then, one or more materials of the source / drain contact 144 can be formed on the metal-semiconductor alloy region 146.

[0093] Figure 26 , Figure 27 and Figure 28 Various embodiments of the gate structure in the first region (e.g., n-type region 50N) are shown. Figure 26 It shows the relationship with Figure 21A The embodiments are similar to those in the previous one, but in which the in-situ layer 114B is omitted from the gate electrode layer 114 in the first region (e.g., n-type region 50N). Figure 27 and Figure 28 They respectively showed the same as Figure 21A and Figure 26 Similar embodiments to those described above, but wherein a barrier layer 114F is included in the gate electrode layer 114 in the first region (e.g., n-type region 50N). In these embodiments, the barrier layer 114F is formed between the high-k dielectric layer 112B and the first work function adjustment layer 114A in the first region (e.g., n-type region 50N). In some embodiments, the barrier layer 114F comprises any acceptable material to protect the high-k dielectric layer 112B and prevent other layers from diffusing into the high-k dielectric layer 112B. For example, the barrier layer 114F may be formed of a metal or a metal nitride (e.g., titanium nitride, silicon-doped titanium nitride, tantalum nitride, etc.), which may be deposited by ALD, CVD, PVD, etc.

[0094] The embodiments can achieve advantages. According to various embodiments, the gate electrode is formed with an active function adjustment layer. In some embodiments, the n-type device has an active function adjustment layer comprising Zr, Hf, Nb, Ta, or combinations thereof. These active function adjustment layers reduce the active function value and further shift the effective active function value towards the n-type. These changes can improve the threshold voltage of the resulting n-type device.

[0095] An embodiment includes a device having nanostructures on a substrate, the nanostructures including channel regions. The device also includes a gate dielectric layer surrounding each nanostructure. The device further includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, the work function value of the first n-type work function metal being less than that of titanium. The device also includes an adhesive layer on the first work function tuning layer. The device further includes a filler layer on the adhesive layer.

[0096] The embodiment may include one or more of the following features. In this device, the first n-type work function metal includes zirconium. The first n-type work function metal includes hafnium. The first n-type work function metal includes niobium. The first n-type work function metal includes tantalum. Various portions of the first work function adjustment layer fill the regions between various portions of the gate dielectric layer. The filling layer does not extend between adjacent nanostructures. The thickness of the first work function adjustment layer is... to Within the range.

[0097] The embodiment includes a method comprising forming a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region. The method further includes forming a first gate dielectric layer on the first channel region. The method further includes forming a first work function adjustment layer on the first gate dielectric layer, the first work function adjustment layer comprising zirconium, hafnium, niobium, tantalum, or combinations thereof. The method further includes forming a first barrier layer on the first work function adjustment layer, the first barrier layer being formed in situ with the first work function adjustment layer. The method further includes forming an adhesive layer on the first barrier layer. The method further includes forming a filler layer on the adhesive layer.

[0098] The embodiments may include one or more of the following features. In this method, the first work function adjustment layer includes aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, or a combination thereof. The method further includes forming a second set of nanostructures on a substrate, the second set of nanostructures including a second channel region, forming a second gate dielectric layer on the second channel region, forming the first work function adjustment layer on the second gate dielectric layer, forming a first barrier layer on the first work function adjustment layer on the second gate dielectric layer, and removing the first barrier layer and the first work function adjustment layer from the second gate dielectric layer. The method further includes forming a second work function adjustment layer on the second gate dielectric layer after removing the first barrier layer and the first work function adjustment layer from the second gate dielectric layer. The adhesive layer and the second work function adjustment layer are formed simultaneously using the same process. The second work function adjustment layer is formed on the adhesive layer. The method further includes forming a second barrier layer on the first gate dielectric layer, and the first work function adjustment layer is formed on the second barrier layer. The first gate dielectric layer and the second gate dielectric layer are formed simultaneously using the same process. Each part of the first work function adjustment layer fills the region between each part of the first gate dielectric layer.

[0099] The embodiment includes a method comprising forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method further includes forming a gate dielectric layer having a first portion and a second portion, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region. The method further includes forming an n-type work function adjustment layer on the first portion and the second portion of the gate dielectric layer, the n-type work function adjustment layer surrounding each of the first set of nanostructures. The method further includes forming a first barrier layer on and in situ with the n-type work function adjustment layer. The method further includes removing the first barrier layer and the n-type work function adjustment layer from the second portion of the gate dielectric layer. The method further includes forming a p-type work function adjustment layer on the first barrier layer on the first set of nanostructures and on the second portion of the gate dielectric layer. The method further includes forming a fill layer on the p-type work function adjustment layer.

[0100] Embodiments may include one or more of the following features. The method further includes forming a second barrier layer on a first portion of the gate dielectric layer, and an n-type work function adjustment layer is formed on the second barrier layer. Forming the n-type work function adjustment layer includes forming aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, or a combination thereof.

[0101] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0102] Example 1 is a semiconductor device comprising: a nanostructure located on a substrate, the nanostructure including a channel region; a gate dielectric layer surrounding each of the nanostructures; a first work function adjustment layer located on the gate dielectric layer, the first work function adjustment layer comprising a first n-type work function metal, aluminum, and carbon, the work function value of the first n-type work function metal being less than that of titanium; an adhesive layer located on the first work function adjustment layer; and a filler layer located on the adhesive layer.

[0103] Example 2 is the device described in Example 1, wherein the first n-type work function metal includes zirconium.

[0104] Example 3 is the device described in Example 1, wherein the first n-type work function metal includes hafnium.

[0105] Example 4 is the device described in Example 1, wherein the first n-type work function metal includes niobium.

[0106] Example 5 is the device described in Example 1, wherein the first n-type work function metal includes tantalum.

[0107] Example 6 is the device described in Example 5, wherein portions of the first work function adjustment layer fill the region between portions of the gate dielectric layer.

[0108] Example 7 is the device described in Example 1, wherein the filling layer does not extend between adjacent nanostructures.

[0109] Example 8 is the device described in Example 1, wherein the thickness of the first work function adjustment layer is... to Within the range.

[0110] Example 9 is a method for forming a semiconductor device, comprising: forming a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region; forming a first gate dielectric layer on the first channel region; forming a first work function adjustment layer on the first gate dielectric layer, the first work function adjustment layer including zirconium, hafnium, niobium, tantalum, or a combination thereof; forming a first barrier layer on the first work function adjustment layer, the first barrier layer being formed in situ with the first work function adjustment layer; forming an adhesive layer on the first barrier layer; and forming a filler layer on the adhesive layer.

[0111] Example 10 is the method described in Example 9, wherein the first work function adjustment layer comprises aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, or a combination thereof.

[0112] Example 11 is the method of Example 9, further comprising: forming a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region; forming a second gate dielectric layer on the second channel region; forming a first work function adjustment layer on the second gate dielectric layer; forming a first barrier layer on the first work function adjustment layer on the second gate dielectric layer; and removing the first barrier layer and the first work function adjustment layer from the second gate dielectric layer.

[0113] Example 12 is the method of Example 11, further comprising: after removing the first blocking layer and the first work function adjustment layer from the second gate dielectric layer, forming a second work function adjustment layer on the second gate dielectric layer.

[0114] Example 13 is the method described in Example 12, wherein the adhesive layer and the second work function adjustment layer are formed simultaneously using the same process.

[0115] Example 14 is the method described in Example 12, wherein the second work function adjustment layer is formed on the adhesive layer.

[0116] Example 15 is the method of Example 12, further comprising: forming a second barrier layer on the first gate dielectric layer, wherein the first work function adjustment layer is formed on the second barrier layer.

[0117] Example 16 is the method described in Example 12, wherein the first gate dielectric layer and the second gate dielectric layer are formed simultaneously using the same process.

[0118] Example 17 is the method described in Example 9, wherein portions of the first work function adjustment layer fill the region between portions of the first gate dielectric layer.

[0119] Example 18 is a method for forming a semiconductor device, comprising: forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region; forming a gate dielectric layer having a first portion and a second portion, the first portion being deposited on the first channel region and the second portion being deposited on the second channel region; forming an n-type work function adjustment layer on the first portion and the second portion of the gate dielectric layer, the n-type work function adjustment layer surrounding each of the first set of nanostructures; forming a first barrier layer on and in situ with the n-type work function adjustment layer; removing the first barrier layer and the n-type work function adjustment layer from the second portion of the gate dielectric layer; forming a p-type work function adjustment layer on the first barrier layer on the first set of nanostructures and on the second portion of the gate dielectric layer; and forming a fill layer on the p-type work function adjustment layer.

[0120] Example 19 is the method of Example 18, further comprising: forming a second barrier layer on a first portion of the gate dielectric layer, wherein the n-type work function adjustment layer is formed on the second barrier layer.

[0121] Example 20 is the method described in Example 18, wherein forming the n-type work function adjustment layer includes forming aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, aluminum tantalum carbide, or a combination thereof.

Claims

1. A semiconductor device, comprising: A nanostructure located on a substrate, the nanostructure including a channel region; A gate dielectric layer surrounds each of the nanostructures; A first work function adjustment layer is located on the gate dielectric layer. The first work function adjustment layer includes a first n-type work function metal, aluminum, and carbon. The work function value of the first n-type work function metal is less than that of titanium. The first n-type work function metal includes zirconium, hafnium, niobium, or a combination thereof. An adhesive layer is located on the first work function adjustment layer; and A filler layer is located on the adhesive layer.

2. The device according to claim 1, wherein, Each portion of the first work function adjustment layer fills the region between each portion of the gate dielectric layer.

3. The device according to claim 1, wherein, The filling layer does not extend between adjacent nanostructures.

4. The device according to claim 1, wherein, The thickness of the first work function adjustment layer is in the range of 5 Å to 50 Å.

5. A method for forming a semiconductor device, comprising: A first set of nanostructures is formed on a substrate, the first set of nanostructures including a first channel region; A first gate dielectric layer is formed on the first channel region; A first work function adjustment layer is formed on the first gate dielectric layer. The first work function adjustment layer includes a first n-type work function metal. The work function value of the first n-type work function metal is less than that of titanium. The first n-type work function metal includes zirconium, hafnium, niobium, or a combination thereof. A first barrier layer is formed on the first work function adjustment layer, and the first barrier layer is formed in situ with the first work function adjustment layer. An adhesive layer is formed on the first barrier layer; as well as A filler layer is formed on the adhesive layer.

6. The method according to claim 5, wherein, The first work function adjustment layer includes aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, or a combination thereof.

7. The method according to claim 5, further comprising: A second set of nanostructures is formed on the substrate, the second set of nanostructures including a second channel region; A second gate dielectric layer is formed on the second channel region; The first work function adjustment layer is formed on the second gate dielectric layer; The first barrier layer is formed on the first work function adjustment layer on the second gate dielectric layer; and Remove the first blocking layer and the first work function adjustment layer from the second gate dielectric layer.

8. The method according to claim 7, further comprising: After removing the first barrier layer and the first work function adjustment layer from the second gate dielectric layer, a second work function adjustment layer is formed on the second gate dielectric layer.

9. The method according to claim 8, wherein, The adhesive layer and the second work function adjustment layer are formed simultaneously using the same process.

10. The method according to claim 8, wherein, The second work function adjustment layer is formed on the adhesive layer.

11. The method of claim 8, further comprising: A second barrier layer is formed on the first gate dielectric layer, and the first work function adjustment layer is formed on the second barrier layer.

12. The method according to claim 8, wherein, The first gate dielectric layer and the second gate dielectric layer are formed simultaneously using the same process.

13. The method according to claim 5, wherein, Each portion of the first work function adjustment layer fills the region between each portion of the first gate dielectric layer.

14. A method for forming a semiconductor device, comprising: A first set of nanostructures and a second set of nanostructures are formed on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. A gate dielectric layer having a first portion and a second portion is formed, wherein the first portion is deposited on the first channel region and the second portion is deposited on the second channel region; An n-type work function adjustment layer is formed on a first portion of the gate dielectric layer and a second portion of the gate dielectric layer, and the n-type work function adjustment layer surrounds each of the first group of nanostructures. The n-type work function adjustment layer includes a first n-type work function metal, the work function value of which is less than that of titanium. The first n-type work function metal includes zirconium, hafnium, niobium, or a combination thereof. A first blocking layer is formed on and in situ with the n-type work function adjustment layer; Remove the first blocking layer and the n-type work function adjustment layer from the second portion of the gate dielectric layer; A p-type work function adjustment layer is formed on the first barrier layer and the second portion of the gate dielectric layer on the first group of nanostructures; as well as A filling layer is formed on the p-type work function adjustment layer.

15. The method of claim 14, further comprising: A second barrier layer is formed on a first portion of the gate dielectric layer, and the n-type work function adjustment layer is formed on the second barrier layer.

16. The method of claim 14, wherein, Forming the n-type work function adjustment layer includes forming aluminum zirconium carbide, aluminum hafnium carbide, aluminum niobium carbide, or a combination thereof.

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