Display substrate, manufacturing method thereof and display device
By introducing stacked low-temperature polycrystalline silicon and amorphous silicon layer structures into the thin-film transistors of LTPS display devices, the problem of high leakage current was solved, costs were reduced, yield was improved, and better display effects were achieved.
Patent Information
- Application Number
- CN202210373906.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-11
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2042-04-11
AI Technical Summary
The high leakage current of thin-film transistors in LTPS display devices prevents the stored charge in the capacitors from being effectively shut off, affecting the display effect, increasing manufacturing costs, and reducing yield.
In the active layer of a thin-film transistor, a low-temperature polycrystalline silicon layer and an amorphous silicon layer are introduced in a stacked manner. The amorphous silicon layer is located between the low-temperature polycrystalline silicon layer and the source/drain metal layer to reduce leakage current. A control signal with a fixed positive potential is obtained by setting the first gate of the target transistor to be connected to a fixed signal terminal.
While ensuring display quality, the number of process steps for the display substrate was reduced, manufacturing costs were lowered, yield was improved, and the performance of thin-film transistors was enhanced.
Smart Images
Figure CN114823724B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the same, and a display device. Background Technology
[0002] LTPS (Low-Temperature Polycrystalline Silicon) display devices are widely used due to their advantages such as low cost and high drive current. However, the high leakage current of thin-film transistors in LTPS display devices can lead to ineffective shut-off of the charge stored in the capacitors, negatively impacting the display effect. In related technologies, several oxide transistors can replace several transistors in the LTPS backplane; however, this increases the need for additional processes, typically involving several patterning steps, significantly increasing manufacturing costs. Furthermore, the increased number of process steps also increases the probability of product defects. Therefore, existing display substrates are characterized by high cost and low yield. Summary of the Invention
[0003] This invention provides a display substrate, a method for manufacturing the same, and a display device to address the problems of high cost and low yield of existing display substrates.
[0004] To solve the above problems, the present invention is implemented as follows:
[0005] In a first aspect, embodiments of the present invention provide a display substrate, including a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes a plurality of thin-film transistors, the plurality of thin-film transistors including a target transistor, the target transistor including a first gate layer, an active layer and a source / drain metal layer, wherein the active layer includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked thereon, the amorphous silicon layer being located between the low-temperature polycrystalline silicon layer and the source / drain metal layer, and the source / drain metal layer being in contact with the amorphous silicon layer.
[0006] In some embodiments, the target transistor further includes a second gate layer, a portion of the first gate layer forming a first gate of the target transistor, and a portion of the second gate layer forming a second gate of the target transistor;
[0007] The first gate layer and the source / drain metal layer are located on the same side of the active layer, and the second gate layer is located on the side of the active layer away from the first gate layer.
[0008] In some embodiments, the first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
[0009] In some embodiments, the plurality of thin-film transistors includes a driving transistor, and the target transistor includes thin-film transistors other than the driving transistor among the plurality of thin-film transistors.
[0010] In some embodiments, the target transistor is a compensation transistor and / or a reset transistor among the plurality of thin-film transistors.
[0011] In a second aspect, embodiments of the present invention provide a display device comprising the display substrate described in any one of the first aspects.
[0012] Thirdly, embodiments of the present invention provide a method for manufacturing a display substrate, comprising the following steps:
[0013] Provide a substrate;
[0014] An active layer is fabricated on the substrate, wherein the active layer includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked along a direction away from the substrate, and the orthogonal projection of the low-temperature polycrystalline silicon layer on the substrate covers the orthogonal projection of the amorphous silicon layer on the substrate;
[0015] A first gate layer and a source / drain metal layer are formed on the side of the active layer away from the substrate, wherein at least a portion of the source / drain metal layer is in contact with the amorphous silicon layer.
[0016] In some embodiments, prior to fabricating the active layer on the substrate, the method further includes:
[0017] A second gate layer is fabricated on the substrate, wherein a portion of the first gate layer forms the first gate of the target transistor, and a portion of the second gate layer forms the second gate of the target transistor. The first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
[0018] In some embodiments, the fabrication of the active layer on the substrate includes:
[0019] Deposit low-temperature polycrystalline silicon material on the substrate;
[0020] Photoresist is coated onto the low-temperature polycrystalline silicon material and then exposed and developed.
[0021] The photoresist in the photoresist removal area is removed and the low-temperature polysilicon material is etched to form a low-temperature polysilicon layer, wherein the photoresist in the photoresist retention area is retained after the low-temperature polysilicon layer is etched.
[0022] Photoresist is exposed in the photoresist retention area to expose a target region of the active layer, wherein the target region includes a region corresponding to the active layer of the target transistor;
[0023] An amorphous silicon layer is formed in the target region.
[0024] In some embodiments, after the photoresist is exposed, the angle between the side of the photoresist and the substrate is greater than 70 degrees.
[0025] In the technical solution of this invention embodiment, the active layer of the target transistor includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked together. By setting the amorphous silicon layer, the leakage current of the target transistor can be reduced, so that all thin-film transistors can be fabricated using the LTPS process to ensure that the target transistor has a low leakage current. This can reduce the process steps of the display substrate while ensuring the display effect, which helps to reduce the manufacturing cost of the display substrate and improve the yield of the display substrate. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the structure of the display substrate provided in an embodiment of the present invention;
[0028] Figure 2 These are simulation results of the transfer characteristics of the display substrate provided in the embodiments of the present invention;
[0029] Figure 3 This is another structural schematic diagram of the display substrate provided in an embodiment of the present invention;
[0030] Figure 4 This is another structural schematic diagram of the display substrate provided in an embodiment of the present invention;
[0031] Figure 5 This is a schematic diagram of the structure of the display substrate provided in an embodiment of the present invention;
[0032] Figure 6 This is a flowchart of the method for manufacturing a display substrate provided in this invention. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] In the embodiments of this invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Additionally, the use of "and / or" in this application indicates at least one of the connected objects, such as A and / or B and / or C, representing seven possibilities: including A alone, B alone, C alone, and the presence of both A and B, both B and C, both A and C, and the presence of A, B, and C.
[0035] This invention provides a display substrate.
[0036] like Figure 1 As shown, in one embodiment, the display substrate includes a substrate 10 and a driving circuit layer 20 disposed on the substrate 10. The driving circuit layer 20 includes a plurality of pixel driving circuits, each pixel driving circuit corresponding to a sub-pixel.
[0037] like Figure 1 As shown, in some embodiments, the driving circuit layer 20 specifically includes a buffer layer 201, an active layer, a first gate insulating layer 204, a first gate layer 205, a third gate insulating layer 206, a third gate layer 207, an interlayer insulating layer 208, and a source / drain metal layer 209, which are sequentially disposed along the direction away from the substrate 10.
[0038] Each pixel driving circuit includes multiple thin-film transistors. For example, a 7T1C pixel driving circuit includes seven thin-film transistors and a storage capacitor. Obviously, the structure of the pixel driving circuit is not limited to this. For example, it can also be a pixel driving circuit with different structures such as 3T1C and 5T1C. In this embodiment, the specific structure of the pixel driving circuit is not further limited.
[0039] Multiple thin-film transistors include target transistor 22.
[0040] In some embodiments, the plurality of thin-film transistors includes a driving transistor 21, and the target transistor 22 includes thin-film transistors other than the driving transistor 21 among the plurality of thin-film transistors.
[0041] Each thin-film transistor includes a first gate layer 205, an active layer, and a source / drain metal layer 209, wherein the source / drain metal layer 209 is in contact with the active layer.
[0042] For the thin-film transistors other than the driving transistor 21, their active layers consist of a stacked low-temperature polycrystalline silicon layer 202 and an amorphous silicon layer 203. The amorphous silicon layer 203 is located between the low-temperature polycrystalline silicon layer 202 and the source / drain metal layer 209, and the source / drain metal layer 209 is in contact with the amorphous silicon layer 203. In this way, by using the stacked low-temperature polycrystalline silicon layer 202 and the amorphous silicon layer 203 as the active layers, the leakage current of these thin-film transistors can be reduced.
[0043] like Figure 4 As shown, in some embodiments, the target transistor 22 is a compensation transistor 22B and / or a reset transistor 22A among a plurality of thin-film transistors. It should be understood that the compensation transistor 22B and / or the reset transistor 22A are more sensitive to leakage current and require lower leakage current. In this embodiment, the active layer of the compensation transistor 22B and / or the reset transistor 22A may be configured to include a stacked low-temperature polycrystalline silicon layer 202 and an amorphous silicon layer 203 to reduce the leakage current of the compensation transistor 22B and / or the reset transistor 22A.
[0044] It should be understood that the active layer of the driving transistor 21 is composed of a low-temperature polysilicon layer 202, which makes the driving transistor 21 have a relatively large leakage current.
[0045] like Figure 2 As shown, Figure 2 The simulation test results of the thin-film transistors of the display substrate in this embodiment are shown, where the horizontal axis represents the gate voltage Vgs in V and the vertical axis represents the leakage current Ids in A. Figure 2 The dashed line corresponds to the simulation results of existing low-temperature polycrystalline silicon transistors, while the solid line represents the simulation results of thin-film transistors with active layers including stacked low-temperature polycrystalline silicon layers 202 and amorphous silicon layers 203.
[0046] Simulation tests show that setting the active layer of the thin-film transistor as a stacked low-temperature polycrystalline silicon layer and amorphous silicon layer can reduce its leakage current. In this way, the driving transistor can still maintain a large current and stronger driving capability by using only the low-temperature polycrystalline silicon layer as the active layer, which helps to improve the reliability of the display substrate.
[0047] In the technical solution of this invention embodiment, the active layer of the target transistor 22 includes a low-temperature polycrystalline silicon layer 202 and an amorphous silicon layer 203 stacked together. By setting the amorphous silicon layer 203, the leakage current of the target transistor 22 can be reduced. Thus, all thin-film transistors can be fabricated using the LTPS process to ensure that the target transistor 22 has a low leakage current. This reduces the process steps of the display substrate while ensuring the display effect, which helps to reduce the manufacturing cost of the display substrate and improve the yield of the display substrate.
[0048] like Figure 3As shown, in some embodiments, the target transistor 22 further includes a second gate layer 210 and a second gate insulating layer 211, a portion of the first gate layer 205 forms the first gate of the target transistor 22, and a portion of the second gate layer 210 forms the second gate of the target transistor 22.
[0049] In the technical solution of this embodiment, the first gate layer 205 and the source / drain metal layer 209 are located on the same side of the active layer, and the second gate layer 210 is located on the side of the active layer away from the first gate layer 205. In other words, the first gate and the second gate of the target transistor 22 are located on opposite sides of the active layer of the target transistor 22.
[0050] In some embodiments, the first gate of the target transistor 22 is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
[0051] During operation, the first gate of the target transistor 22 is connected to a positive fixed potential. Thus, when the target transistor 22 is turned on, it is mainly controlled by the second gate. The conductive channel is mainly formed at the lower interface of the active layer, more specifically, the lower surface of the low-temperature polycrystalline silicon layer 202, which has fewer defects and less scattering of charge carriers, and can have a larger on-state current.
[0052] like Figure 5 As shown, the GOA region where the GOA (array substrate row drive) unit is set also includes a GOA transistor 22C. The active layer of the GOA transistor 22C retains only the low-temperature polysilicon layer as the active layer to ensure that the GOA transistor 22C in the GOA region has a high driving capability.
[0053] When the target transistor 22 is in the off state, both the first gate and the second gate are at positive potential, which strengthens its control capability and further reduces the leakage current of the target transistor 22, giving the target transistor 22 a larger switching ratio. This helps improve the performance of the target transistor 22 and ensures good display effect even in low-frequency display mode.
[0054] This invention provides a display device comprising the display substrate described in any of the above embodiments.
[0055] The display device of this embodiment includes all the technical solutions of the above-described display substrate embodiments, and therefore can at least achieve all the technical effects of the above embodiments, which will not be repeated here.
[0056] This invention provides a method for manufacturing a display substrate.
[0057] like Figure 6 As shown, in one embodiment, the method for manufacturing the display substrate includes the following steps:
[0058] Step 601: Provide a substrate;
[0059] Step 602: An active layer is fabricated on the substrate, wherein the active layer includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked along a direction away from the substrate, and the orthogonal projection of the low-temperature polycrystalline silicon layer on the substrate covers the orthogonal projection of the amorphous silicon layer on the substrate;
[0060] Step 603: A first gate layer and a source / drain metal layer are formed on the side of the active layer away from the substrate, wherein at least a portion of the source / drain metal layer is in contact with the amorphous silicon layer.
[0061] The technical solution of this embodiment is used to manufacture the display substrate in the above-described display substrate embodiment.
[0062] In this embodiment, where the target transistor only includes a first gate, each structure is first fabricated sequentially on the substrate using normal processes.
[0063] In one exemplary embodiment, a buffer layer can be first fabricated on a substrate, and then a low-temperature polycrystalline silicon layer and an amorphous silicon layer can be sequentially fabricated on the buffer layer to form a low-temperature polycrystalline silicon layer.
[0064] Furthermore, by referring to relevant technologies, the first gate insulating layer, the first gate layer, the third gate insulating layer, the third gate layer, the source and drain metal layers, etc. can be fabricated sequentially. Obviously, the structure of the display substrate is not limited to this. During implementation, the structure to be fabricated can be adjusted as needed, and no further limitations are made here.
[0065] In some embodiments, step 602 above includes:
[0066] Deposit low-temperature polycrystalline silicon material on the substrate;
[0067] Photoresist is coated onto the low-temperature polycrystalline silicon material and then exposed and developed.
[0068] The photoresist in the photoresist removal area is removed and the low-temperature polysilicon material is etched to form a low-temperature polysilicon layer, wherein the photoresist in the photoresist retention area is retained after the low-temperature polysilicon layer is etched.
[0069] Photoresist is exposed in the photoresist retention area to expose a target region of the active layer, wherein the target region includes a region corresponding to the active layer of the target transistor;
[0070] An amorphous silicon layer is formed in the target region.
[0071] In the technical solution of this embodiment, after the low-temperature polycrystalline silicon layer is fabricated, the photoresist is retained and exposed again to define the target area corresponding to the target transistor. Here, the target transistor refers to the thin-film transistor other than the driving transistor. More specifically, the target transistor may refer to the compensation transistor and / or the reset transistor.
[0072] It is important to understand that after photoresist is coated onto the low-temperature polysilicon material, the first exposure forms a photoresist removal area and a photoresist retention area. After development, the photoresist in the photoresist removal area is removed, while the photoresist in the photoresist retention area is retained. Then, the low-temperature polysilicon material is etched to form a low-temperature polysilicon layer.
[0073] Next, the photoresist retention area is exposed a second time, and then through development and other operations, the portion of the photoresist in the photoresist retention area corresponding to the target area is removed, exposing the portion of the low-temperature polysilicon layer corresponding to the target area.
[0074] In one embodiment, after the second exposure process exposes the retained photoresist, the angle between the side of the photoresist and the substrate is greater than 70 degrees.
[0075] During the second exposure, OPC (Optical Proximity Correction) technology can be used. Specifically, light-blocking strips of a certain width and spacing can be set at the edge of the opaque area of the mask to affect the diffraction of light and adjust the distribution of light.
[0076] In this embodiment, OPC technology enables a steeper distribution of light intensity at specific locations, ensuring a larger slope at the edge of the photoresist. In this embodiment, the slope of the photoresist edge is controlled to be greater than 70° to improve the subsequent fabrication effect of the amorphous silicon layer.
[0077] In some embodiments, negative photoresist can be used in the above process, so that after exposure and development, an inverted trapezoidal structure can be formed, which is more conducive to breaking the amorphous silicon film at a specific location to complete the stripping operation.
[0078] After the target area of the low-temperature polycrystalline silicon layer is exposed, amorphous silicon material is first deposited. In practice, a 1 to 5 nanometer thick amorphous silicon film can be deposited by chemical vapor deposition (CVD). Specifically, amorphous silicon films with a large band gap and a high hydrogen content can be prepared by adjusting the deposition power, deposition pressure and gas flow ratio.
[0079] In an exemplary embodiment, the deposition power is 100W to 1000W, the deposition pressure is controlled at 500 to 2000 mtorr, and the flow ratio of silane to hydrogen during deposition is 1:3 to 1:10.
[0080] For example, in another embodiment, the deposition power is selected as 100W, the deposition pressure is 500mtorr, and the gas flow ratio is 1:3.
[0081] In another embodiment, the deposition power is selected as 1000W, the deposition pressure is 2000mtorr, and the gas flow ratio is 1:10.
[0082] In another embodiment, the deposition power is selected as 700W, the deposition pressure is 1500mtorr, and the gas flow ratio is 1:7.
[0083] In another embodiment, the deposition power is selected as 550W, the deposition pressure is 1300mtorr, and the gas flow ratio is 1:8.
[0084] In another embodiment, the deposition power is selected as 400W, the deposition pressure is 1700mtorr, and the gas flow ratio is 1:5.5.
[0085] In this embodiment, the above process can fabricate an amorphous silicon thin film with a band gap greater than 1.8 eV. The wider band gap can suppress the generation of electron holes caused by heat to a greater extent, thereby improving leakage current. The presence of hydrogen can fill dangling bonds and reduce defect-assisted tunneling, thereby further reducing leakage current.
[0086] Next, the excess amorphous silicon film is lifted off. In practice, at least the amorphous silicon film in the region corresponding to the driving transistor needs to be lifted off. Alternatively, only the amorphous silicon film in the target region corresponding to the target transistor can be retained. This completes the fabrication of the active layer pattern.
[0087] The thin-film transistors in the GOA (Gallery Array) region are also stripped of their amorphous silicon films through a peeling process, leaving only the low-temperature polycrystalline silicon layer as the active layer, to ensure that the thin-film transistors in the GOA region have high driving capability.
[0088] After the active layer pattern is fabricated, the active layer can be made conductive at the corresponding positions of the source and drain regions of each thin-film transistor by self-aligned ion implantation doping. Here, the process itself can refer to relevant technologies and no additional process steps are required.
[0089] Furthermore, the subsequent structures of the display substrate are fabricated by referring to relevant processes, which will not be elaborated here.
[0090] like Figure 2As shown in the simulation test, in this embodiment, the active layer of thin film transistors such as compensation transistors and reset transistors is set as a stacked low-temperature polycrystalline silicon layer and amorphous silicon layer, which can reduce their leakage current. The driving transistor uses only the low-temperature polycrystalline silicon layer as the active layer, which can still maintain a large current and has a stronger driving capability, thus helping to improve the reliability of the display substrate.
[0091] Compared with the LTPS display substrate in related technologies, the technical solution of this embodiment adds a patterning process, which enables low leakage current of thin film transistors such as compensation transistors and reset transistors and strong driving capability of driving transistors.
[0092] Compared with existing LTPO (Low Temperature Polycrystalline Oxide) display substrates, it reduces at least two to three patterning processes. During the fabrication process, it is not necessary to consider factors such as temperature and hydrogenation in the fabrication processes of oxide transistors and low temperature polycrystalline silicon layers. This can effectively reduce the complexity of the process, improve the yield of display substrates, and help save costs.
[0093] Furthermore, the thickness of the subsequently prepared inorganic film layer can also be effectively reduced. Tests have shown that the thickness of the subsequent inorganic film layer can be reduced by more than 5000 Å, which can reduce the possibility of damage to the display substrate caused by stress mismatch.
[0094] In some embodiments, the target transistor includes a first gate and a second gate.
[0095] In this embodiment, before step 602, the method further includes:
[0096] A second gate layer is fabricated on the substrate, wherein a portion of the first gate layer forms the first gate of the target transistor, and a portion of the second gate layer forms the second gate of the target transistor. The first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
[0097] In this embodiment, a metal layer is first deposited on the substrate by physical vapor deposition (PVD). For example, materials such as Mo (molybdenum) can be selected to form the metal layer. Then, the metal layer is patterned using a patterning process to serve as the second gate of the target transistor. After the second gate is fabricated, a second gate insulating layer and a buffer layer can be fabricated on the side of the second gate away from the substrate. Further fabrication of other structures can be completed with reference to the above embodiment, which will not be elaborated here.
[0098] In this embodiment, the first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
[0099] During operation, the first gate of the target transistor is connected to a positive fixed potential. Thus, when the target transistor is turned on, it is mainly controlled by the second gate. The conductive channel is mainly formed at the lower interface of the active layer, more specifically, the lower surface of the low-temperature polycrystalline silicon layer, which has fewer defects and less scattering of charge carriers, and can have a larger on-state current.
[0100] When the target transistor is in the off state, both the first gate and the second gate are at positive potential, which strengthens its control capability and can further reduce the leakage current of the target transistor, giving the target transistor a larger switching ratio. This helps to improve the performance of the target transistor and ensures good display effect even in low-frequency display conditions.
[0101] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A display substrate, characterized in that, The device includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes a plurality of thin-film transistors, each of which includes a target transistor. The target transistor includes a first gate layer, an active layer, and a source / drain metal layer. The active layer includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked together. The amorphous silicon layer is located between the low-temperature polycrystalline silicon layer and the source / drain metal layer, and the source / drain metal layer is in contact with the amorphous silicon layer. The plurality of thin-film transistors include driving transistors, and the target transistor includes thin-film transistors other than the driving transistors among the plurality of thin-film transistors; The target transistor further includes a second gate layer, a portion of the first gate layer forming a first gate of the target transistor, and a portion of the second gate layer forming a second gate of the target transistor; Wherein, the first gate layer and the source / drain metal layer are located on the same side of the active layer, and the second gate layer is located on the side of the active layer away from the first gate layer; The first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential; When the target transistor is in the off state, both the first gate and the second gate are at positive potential.
2. The display substrate as described in claim 1, characterized in that, The target transistor is a compensation transistor and / or a reset transistor among the plurality of thin-film transistors.
3. A display device, characterized in that, The display substrate includes any one of claims 1 to 2.
4. A method for manufacturing a display substrate, characterized in that, Includes the following steps: Provide a substrate; An active layer is fabricated on the substrate, wherein the active layer includes a low-temperature polycrystalline silicon layer and an amorphous silicon layer stacked along a direction away from the substrate, and the orthogonal projection of the low-temperature polycrystalline silicon layer on the substrate covers the orthogonal projection of the amorphous silicon layer on the substrate; A first gate layer and a source / drain metal layer are formed on the side of the active layer away from the substrate, wherein at least a portion of the source / drain metal layer is in contact with the amorphous silicon layer; Before fabricating the active layer on the substrate, the method further includes: A second gate layer is fabricated on the substrate, wherein a portion of the first gate layer forms the first gate of the target transistor, a portion of the second gate layer forms the second gate of the target transistor, and the first gate of the target transistor is connected to a fixed signal terminal to obtain a first control signal with a fixed positive potential.
5. The method as described in claim 4, characterized in that, The fabrication of the active layer on the substrate includes: Deposit low-temperature polycrystalline silicon material on the substrate; Photoresist is coated onto the low-temperature polycrystalline silicon material and then exposed and developed. The photoresist in the photoresist removal area is removed and the low-temperature polysilicon material is etched to form a low-temperature polysilicon layer, wherein the photoresist in the photoresist retention area is retained after the low-temperature polysilicon layer is etched. Photoresist is exposed in the photoresist retention area to expose a target region of the active layer, wherein the target region includes a region corresponding to the active layer of the target transistor; An amorphous silicon layer is formed in the target region.
6. The method as described in claim 5, characterized in that, After exposure of the retained photoresist, the angle between the side of the photoresist and the substrate is greater than 70 degrees.
Citation Information
Patent Citations
Array substrate and preparation method thereof, and display panel
CN113594178A