Display panel and manufacturing method thereof

Abstract

The application provides a display panel and a manufacturing method of the display panel. The manufacturing method of the display panel comprises successively conducting conductorization treatment on a first electrode and an oxide semiconductor layer made of the same metal oxide semiconductor material, without a gate insulating layer and a gate metal layer above the metal oxide semiconductor material, so that the first electrode made of the metal oxide semiconductor material is conductorized. Thus, a storage capacitor can be formed by the conductorized oxide semiconductor layer and the gate metal layer above the oxide semiconductor layer, so that the capacitance of the storage capacitor can be improved, and the problem of display failure caused by insufficient capacitance of the storage capacitor can be solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Technology

[0002] When an active-matrix organic light-emitting diode (AMOLED) display is turned on, each sub-pixel needs to maintain the voltage of the data signal after it is written to it before the next frame scan. This requires each sub-pixel's driving circuit to have a sufficiently large capacitor. Otherwise, problems such as screen flickering and bright / dark spots will occur.

[0003] The capacitance value of a capacitor is directly proportional to its area; to achieve sufficient capacitance, the capacitor area must meet the corresponding capacitance requirement. In fact, in the array driving circuit of AMOLED products, capacitors occupy a large area, making them a significant challenge in improving resolution (pixels per inch, PPI). Therefore, finding ways to increase capacitance without increasing capacitor area is crucial for AMOLED display products.

[0004] In summary, existing display panels suffer from display defects due to insufficient capacitance of the storage capacitors. Therefore, it is necessary to provide a display panel and a method for manufacturing the display panel to improve this defect. Summary of the Invention

[0005] This application provides a display panel and a method for manufacturing the display panel, which can increase the capacitance value of the storage capacitor and improve the display problem caused by insufficient capacitance value of the storage capacitor.

[0006] This application provides a display panel, including:

[0007] Base;

[0008] A thin-film transistor, disposed on the substrate, the thin-film transistor including an oxide semiconductor layer; and

[0009] A storage capacitor is disposed on the substrate, the storage capacitor including a first electrode and a second electrode disposed on the side of the first electrode opposite to the substrate;

[0010] The first electrode and the oxide semiconductor layer are disposed on the same layer, and both the first electrode and the oxide semiconductor layer comprise the same metal oxide semiconductor material. The first electrode is conductive.

[0011] According to one embodiment of this application, the thin-film transistor includes a gate, which is disposed on the side of the oxide semiconductor layer opposite to the substrate;

[0012] The second electrode is disposed on the same layer as the gate electrode and is made of the same material as the gate electrode.

[0013] According to one embodiment of this application, the display panel further includes a channel shielding layer, which is disposed between the oxide semiconductor layer and the substrate, and is disposed opposite to the oxide semiconductor layer.

[0014] According to one embodiment of this application, the storage capacitor includes a third electrode, the third electrode being disposed between the first electrode and the substrate, and the second electrode being electrically connected to the third electrode;

[0015] The third electrode is disposed on the same layer as the channel shielding layer and is made of the same material as the channel shielding layer.

[0016] According to one embodiment of this application, the storage capacitor further includes a fourth electrode, which is disposed on the side of the second electrode opposite to the first electrode, and the first electrode is electrically connected to the fourth electrode.

[0017] According to one embodiment of this application, the display panel includes a dielectric layer disposed between the third electrode and the first electrode, and a gate insulating layer disposed between the first electrode and the second electrode;

[0018] The thickness of the gate insulating layer is less than the thickness of the dielectric layer.

[0019] According to one embodiment of this application, the display panel further includes a plurality of wires, which are disposed on the same layer as the first electrode and are made of the same material as the first electrode, and the wires are conductive.

[0020] This application embodiment also provides a method for manufacturing a display panel, including:

[0021] Deposit a layer of metal oxide semiconductor material on a substrate;

[0022] A first photoresist layer, a second photoresist layer with a thickness less than the first photoresist layer, and an opening exposing a portion of the metal oxide semiconductor material are formed on the metal oxide semiconductor material.

[0023] The metal oxide semiconductor material is etched to form an oxide semiconductor layer covered by the first photoresist layer and a first electrode covered by the second photoresist layer;

[0024] The first photoresist layer is thinned and the second photoresist layer is removed to expose the first electrode, and the first electrode is then made conductive.

[0025] Remove the first photoresist layer to expose the oxide semiconductor layer, and sequentially deposit a gate insulating layer and a gate metal layer covering the oxide semiconductor layer and the first electrode on the substrate;

[0026] The gate metal layer is etched to form a gate that is directly opposite the oxide semiconductor layer and a second electrode that is directly opposite the first electrode;

[0027] Using the gate as a self-aligned mask, the gate insulating layer is etched to expose the opposite ends of the oxide semiconductor layer that are not covered by the gate.

[0028] The opposite ends of the oxide semiconductor layer not covered by the gate are conductiveized to form the source and drain.

[0029] According to an embodiment of this application, the steps of forming a first photoresist layer, a second photoresist layer with a thickness less than the first photoresist layer, and exposing an opening in the metal oxide semiconductor layer on the metal oxide semiconductor material include:

[0030] A photoresist material is deposited on the metal oxide semiconductor material; and

[0031] The photoresist material is exposed using a halftone mask to form the first photoresist layer, the second photoresist layer, and the opening.

[0032] According to one embodiment of this application, the step of thinning the first photoresist layer and removing the second photoresist includes:

[0033] The first photoresist layer is thinned by etching using a plasma dry etching process, and the second photoresist layer is removed by etching.

[0034] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a method for manufacturing the display panel. By using a halftone mask process, a first electrode and an oxide semiconductor layer made of the same metal oxide semiconductor material are successively conductiveized. Then, a gate insulating layer and a gate metal layer are deposited on top of the first electrode and the oxide semiconductor layer. Therefore, it is not necessary to make the first electrode made of metal oxide semiconductor material conductive by removing the gate insulating layer and the gate metal layer above the metal oxide semiconductor material. In this way, a storage capacitor can be formed by using the conductive first electrode and the gate metal layer above it. Since the thickness of the gate insulating layer is much smaller than the thickness of the dielectric layer, the distance between the upper and lower plates of the storage capacitor can be reduced, thereby increasing the capacitance value of the storage capacitor and improving the display defects caused by insufficient capacitance value of the storage capacitor. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figures 1a to 1f This is a schematic diagram illustrating the manufacturing process of a display panel based on related technologies.

[0037] Figure 2 This is a schematic diagram of the film layer stacking structure of the first type of display panel provided in the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the film layer stacking structure of a second type of display panel provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the film layer stacking structure of a third type of display panel provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the film layer stacking structure of the fourth type of display panel provided in the embodiments of this application;

[0041] Figures 6a to 6n This is a schematic diagram of the process structure of the method for manufacturing a display panel provided in an embodiment of this application. Detailed Implementation

[0042] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0043] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] Currently, the transistors in large-size AMOLED display panels based on oxide transistors are mainly coplanar structures with top gates, requiring conductor-forming treatment for their sources and drains. The source and drain of large-size AMOLED display panels are currently conductive primarily through plasma processing, with the main process as follows: Figures 1a to 1f As shown, the sequence is as follows: patterning of semiconductor layer 11, deposition of gate insulating layer 12, deposition of gate metal layer 13, patterning of gate 130, further etching of gate insulating layer 12 using gate 130 as a mask to expose semiconductor layer 11, and plasma treatment to make source 111 and drain 112 conductive.

[0045] As can be seen from the above process, in order for the plasma to contact the semiconductor layer 11, the gate metal layer 13 and the gate insulating layer 12 above the semiconductor layer 11 need to be etched away. This will cause the conductive semiconductor layer 11 to be unable to form a capacitor with the gate metal layer 13, but only with the metal layer 14 below. Since the thickness of the dielectric layer 15 is much greater than the thickness of the gate insulating layer 12, the capacitance value formed by it is much smaller.

[0046] In view of this, this application provides a display panel, the display panel including a substrate, thin-film transistors, and a storage capacitor. Both the thin-film transistors and the storage capacitor are disposed on the substrate. The thin-film transistors include an oxide semiconductor layer, and the storage capacitor includes a first electrode and a second electrode disposed on the side of the first electrode facing away from the substrate. The first electrode and the oxide semiconductor layer are disposed in the same layer, and both include the same metal oxide semiconductor material. The first electrode is conductive.

[0047] like Figure 2 As shown, Figure 2This is a schematic diagram of the film layer stacking structure of a first type of display panel provided in an embodiment of this application. The display panel includes a substrate 21 and a driving circuit layer disposed on the substrate 21 for controlling and driving an OLED to emit light. The driving circuit layer may include thin-film transistors and storage capacitors. It should be noted that "disposed on the substrate 21" can mean that it is in direct contact with one side surface of the substrate 21 or indirect contact.

[0048] In one embodiment, the display panel may be a rigid AMOLED display panel, and the substrate 21 may be a glass substrate.

[0049] In one embodiment, the display panel may be a flexible AMOLED display panel, and the substrate 21 may also be a flexible substrate. The substrate 21 may be a single-layer flexible substrate structure formed of organic materials, and the organic materials may include, but are not limited to, polyimide.

[0050] In one embodiment, the substrate 21 may also be a double-layer or multi-layer flexible substrate structure formed by sequentially stacking organic materials such as polyimide with inorganic materials such as silicon oxide or silicon nitride.

[0051] In one embodiment, the substrate 21 may also be provided with an insulating layer and an impurity barrier layer formed of inorganic materials such as silicon nitride or silicon oxide.

[0052] Furthermore, the thin-film transistor includes an oxide semiconductor layer 23, a source 24, a drain 25, and a gate 26, with a dielectric layer 22 disposed on the substrate 21, and the oxide semiconductor layer 23 disposed on the side of the dielectric layer 22 facing away from the substrate 21.

[0053] It should be noted that the oxide semiconductor layer 23 is disposed on the side of the dielectric layer 22 away from the substrate 21. This can mean that the oxide semiconductor layer 23 and the surface of the dielectric layer 22 away from the substrate 21 are in direct contact or indirect contact.

[0054] The source electrode 24 and the drain electrode 25 are disposed on the same layer as the oxide semiconductor layer 23 and are made of the same material as the oxide semiconductor layer 23. The source electrode 24 and the drain electrode 25 are formed by a conductor-forming process using metal oxide semiconductor material.

[0055] Furthermore, the storage capacitor includes a first electrode 27 and a second electrode 28. The first electrode 27 and the oxide semiconductor layer 23 are disposed on the same layer, and both the first electrode 27 and the oxide semiconductor layer 23 comprise the same metal oxide semiconductor material. The first electrode 27 is conductive. The second electrode 28 is disposed on the side of the first electrode 27 facing away from the substrate 21.

[0056] In one embodiment, the metal oxide semiconductor material can be any one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or other metal oxides.

[0057] In one embodiment, such as Figure 2 As shown, the second electrode 28 is disposed on the same layer as the gate 26 and is made of the same material as the gate 26.

[0058] The material of the gate 26 may include, but is not limited to, any one of the metal materials such as copper, aluminum, titanium, and molybdenum. The gate 26 may also be a multilayer metal conductive film formed by stacking two or more of the above metal materials.

[0059] In the actual fabrication process, the second electrode 28 and the gate 26 can be formed by the same metal film deposition process.

[0060] In this embodiment, the first electrode 27 and the second electrode 28 are disposed opposite each other, and the first electrode 27 and the second electrode 28 are isolated from each other by a gate insulating layer 29. The overlapping portion of the first electrode 27 and the second electrode 28 forms the storage capacitor.

[0061] Compared to Figure 1f The existing display panels shown employ a storage capacitor formed by a conductive semiconductor layer 11 and an underlying metal layer 14. In this embodiment, a first electrode 27 and a second electrode 28 constitute the storage capacitor. Since the thickness of the gate insulating layer 29 is less than the thickness of the dielectric layer 22, the distance between the first electrode 27 and the second electrode 28 of the storage capacitor can be reduced. This allows for an increase in the capacitance value of the storage capacitor without changing its size, thereby improving the display quality issue caused by insufficient capacitance. In other embodiments, the size of the storage capacitor can be reduced while maintaining its capacitance value, thereby improving the resolution of the display panel.

[0062] Furthermore, the display panel also includes an interlayer dielectric layer 30, a metal trace layer 31, a planarization layer 32, an anode 33, a pixel definition layer 34, a light-emitting layer, and a cathode (not shown in the figure) stacked on the gate 26 and the second electrode 28.

[0063] The interlayer dielectric layer 30 covers the gate 26, the second electrode 28, the source 24, the drain 25, and the dielectric layer 22. The materials of the interlayer dielectric layer 30, the dielectric layer 22, and the gate insulating layer 29 can all be inorganic insulating materials, including but not limited to at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0064] The metal trace layer 31 is disposed on the side of the interlayer dielectric layer 30 facing away from the substrate 21. The metal trace layer 31 includes multiple signal traces, which may include multiple scan lines and multiple data lines. The scan lines are connected to the gate 26 through vias penetrating the interlayer dielectric layer 30. The data lines are connected to the drain 25 through vias penetrating the interlayer dielectric layer 30. The anode 33 is connected to the data lines through vias penetrating the planarization layer 32 to receive the data signals transmitted by the data lines.

[0065] Furthermore, such as Figure 2 As shown, the storage capacitor further includes a fourth electrode 35, which is disposed on the side of the second electrode 28 opposite to the first electrode 27, and the first electrode 27 is electrically connected to the fourth electrode 35.

[0066] In one embodiment, the fourth electrode 35 may be disposed on the same layer as the metal wiring layer 31. In actual fabrication, the fourth electrode 35 and the metal wiring layer 31 may be fabricated using the same metal film deposition process.

[0067] The fourth electrode 35 can be connected to the first electrode 27 through a via penetrating the interlayer dielectric layer 30 and the gate insulating layer 29. The second electrode 28 can independently form one pole of the storage capacitor, and the fourth electrode 35 and the first electrode 27 are connected in parallel to form the other pole of the storage capacitor, thereby further increasing the capacitance value of the storage capacitor.

[0068] like Figure 3 As shown, Figure 3 This is a schematic diagram of the film layer stacking structure of the second type of display panel provided in the embodiments of this application. Figure 3 The second type of display panel shown is... Figure 2The structure of the first type of display panel is roughly the same, except that the display panel further includes a channel shielding layer 36, which is disposed between the oxide semiconductor layer 23 and the substrate 21, and is disposed opposite to the oxide semiconductor layer 23.

[0069] The channel shielding layer 36 is made of an opaque metal material and is disposed directly below the oxide semiconductor layer 23. It can be used to block light from shining from the bottom surface of the substrate 21 onto the oxide semiconductor layer 23, thereby ensuring the stability of the thin film transistor.

[0070] The channel shielding layer 36 can be connected to the data line in the metal trace layer 31 through the via through the interlayer dielectric layer 30 to receive the same data signal as the source 24 or drain 25, thereby avoiding the generation of parasitic capacitance between it and the source 24 or drain 25.

[0071] like Figure 4 As shown, Figure 4 This is a schematic diagram of the film layer stacking structure of the third type of display panel provided in the embodiments of this application. Figure 4 The structure of the third type of display panel shown is similar to Figure 3 The structure of the second type of display panel shown is roughly the same, except that the storage capacitor further includes a third electrode 37, which is disposed between the first electrode 27 and the substrate 21, and the second electrode 28 is electrically connected to the third electrode 37.

[0072] In one embodiment, the third electrode 37 is disposed on the same layer as the channel shielding layer 36, and may be made of the same material as the channel shielding layer 36. In actual fabrication, the third electrode 37 and the channel shielding layer 36 may be fabricated using the same metal deposition process.

[0073] The second electrode 28 can be connected to the third electrode 37 through a via penetrating the gate insulating layer 29 and the dielectric layer 22.

[0074] It should be noted that the second electrode 28 and the third electrode 37 are connected in parallel to form one pole of the storage capacitor, and the fourth electrode 35 and the first electrode 27 are connected in parallel to form the other pole of the storage capacitor. This allows for... Figure 2 Based on the display panel shown, the capacitance value of the storage capacitor is further increased.

[0075] like Figure 5 As shown, Figure 5 This is a schematic diagram of the film layer stacking structure of the fourth type of display panel provided in the embodiments of this application. Figure 5The structure of the fourth type of display panel shown is similar to... Figure 4 The structure of the third type of display panel shown is roughly the same, the difference being: Figure 5 There is no metal trace layer 31 and fourth electrode 35 in it.

[0076] The anode 33 can be connected to the drain 25 through a via penetrating the planarization layer 32 and the interlayer dielectric layer 30. The channel shielding layer 36 can be electrically connected to the data line through a via. The data line can be disposed on the same layer as the gate 26.

[0077] In the storage capacitor, the second electrode 28 and the third electrode 37 are connected in parallel to form one pole of the storage capacitor, and the first electrode 27 alone forms the other pole of the storage capacitor. In this way, the capacitance value of the storage capacitor can also be increased.

[0078] Furthermore, the display panel also includes multiple wires (not shown in the figure), which are disposed on the same layer as the first electrode 27 and are made of the same material as the first electrode 27, and are conductive.

[0079] The conductive wire can be fabricated simultaneously with the first electrode 27 and the oxide semiconductor layer 23. The difference between the conductive wire and the oxide semiconductor layer 23 is that both the conductive wire and the first electrode 27 are made conductive after plasma treatment. The conductive wire can be connected to the source electrode 24, the drain electrode 25, the first electrode 27, or other components.

[0080] Based on the display panel provided in the above embodiments of this application, this application also provides a method for manufacturing a display panel, combined with... Figures 6a to 6n As shown, Figures 6a to 6n This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. The method for manufacturing the display panel includes:

[0081] Step S1: Deposit a layer of metal oxide semiconductor material on the substrate.

[0082] Combination Figure 6a As shown, before depositing the metal oxide semiconductor material 201, a channel shielding layer 36 and a third electrode 37 are formed on the substrate 21. The channel shielding layer 36 and the third electrode 37 can be prepared by the same metal film deposition process.

[0083] In the embodiments of this application, the metal oxide semiconductor material can be any one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or other metal oxides.

[0084] Step S2: Form a first photoresist layer, a second photoresist layer with a thickness less than the first photoresist layer, and an opening that exposes a portion of the metal oxide semiconductor material on the metal oxide semiconductor material.

[0085] Combination Figures 6b to 6c The step of forming a first photoresist layer 202, a second photoresist layer 203 with a thickness less than the first photoresist layer 202, and an opening 204 exposing the metal oxide semiconductor layer on the metal oxide semiconductor material 201 includes: depositing a photoresist material on the metal oxide semiconductor material 201; and exposing the photoresist material through a halftone mask to form the first photoresist layer 202, the second photoresist layer 203, and the opening 204.

[0086] In this embodiment, the halftone mask may include a transparent area, a semi-transparent area, and a non-transparent area. During the exposure of the photoresist material, the portion of the photoresist material corresponding to the transparent area receives the most light, and all the photoresist in this portion is removed, thereby forming the opening 204. The portion of the photoresist material corresponding to the semi-transparent area receives partial light, and some of the photoresist in this portion is removed, thereby forming the second photoresist layer 203. The portion of the photoresist material corresponding to the non-transparent area does not receive partial light, and the photoresist in this portion is not removed, thereby forming the first photoresist layer 202. The thickness of the first photoresist layer 202 is greater than the thickness of the second photoresist layer 203.

[0087] Step S3: Etch the metal oxide semiconductor material to form an oxide semiconductor layer covered by the first photoresist layer and a first electrode covered by the second photoresist layer.

[0088] Step S4: Thin the first photoresist layer and remove the second photoresist layer to expose the first electrode, and perform a conductor treatment on the first electrode.

[0089] Combination Figures 6c to 6e In step S3, the metal oxide semiconductor material exposed by the opening 204 can be removed by wet etching, while the metal oxide semiconductor material covered by the first photoresist layer 202 and the second photoresist layer 203 is retained, forming the oxide semiconductor layer 23 and the first electrode 27.

[0090] In step S4, the step of thinning the first photoresist layer and removing the second photoresist layer includes: using a plasma dry etching process to etch and thin the first photoresist layer 202 and to etch and remove the second photoresist layer 203. The plasma dry etching process can use gases or mixtures thereof that have oxidizing properties, such as O2, CF4, and N2O.

[0091] In step S4, after removing the second photoresist layer 203 and exposing the first electrode 27, the substrate is bombarded with plasma to make the exposed first electrode 27 conductive.

[0092] Step S5: Remove the first photoresist layer to expose the oxide semiconductor layer, and sequentially deposit a gate insulating layer and a gate metal layer covering the oxide semiconductor layer and the first electrode on the substrate.

[0093] Step S6: Etch the gate metal layer to form a gate that is directly opposite the oxide semiconductor layer and a second electrode that is directly opposite the first electrode;

[0094] Combination Figures 6f to 6g In step S5, the first photoresist layer 202 can be removed using a stripping liquid to expose the unconductive oxide semiconductor layer 23. Then, a gate insulating layer 29 and a gate metal layer covering the oxide semiconductor layer 23 and the first electrode 27 are deposited sequentially.

[0095] In step S6, the gate metal layer is etched to form a gate 26 opposite to the oxide semiconductor layer 23 and a second electrode 28 opposite to the first electrode 27. Multiple signal traces can also be formed. The first electrode 27 and the second electrode 28 can form a storage capacitor.

[0096] During steps S5 to S6, after depositing and forming the gate insulating layer 29, the gate insulating layer 29 and the dielectric layer 22 can be etched to form a via penetrating the gate insulating layer 29 and the dielectric layer 22 to expose the third electrode 37. After forming the second electrode 28, the second electrode 28 can be connected to the third electrode 37 through the via, so that together with the third electrode 37, they constitute one electrode of the storage capacitor.

[0097] Step S7: Using the gate as a self-aligned mask, etch the gate insulating layer to expose the opposite ends of the oxide semiconductor layer that are not covered by the gate.

[0098] Combination Figure 6h In step S7, using the gate 26 as a self-aligned mask, a gas containing F or Cl is used to etch away the gate insulating layer 29 that is not covered by the gate metal layer, so as to expose the opposite ends of the oxide semiconductor layer that are not covered by the gate.

[0099] Step S8: Conduct the opposite ends of the oxide semiconductor layer that are not covered by the gate to form the source and drain.

[0100] Combination Figure 6i In step S8, the substrate is subjected to plasma bombardment or similar methods to conduct the exposed opposite ends of the oxide semiconductor layer, thereby forming the source 24 and drain 25 of the thin-film transistor, respectively. In step S8, the substrate can be bombarded with plasma using an inert gas or a gas containing hydrogen.

[0101] Step S9: An interlayer dielectric layer 30 covering the gate, the second electrode, the source and the drain is deposited on the gate metal layer, and a plurality of vias are formed on the interlayer dielectric layer 30.

[0102] Combination Figure 6j In step S9, multiple vias are formed by etching the interlayer dielectric layer 30, and the multiple vias can expose the gate 26, the drain 25 and the first electrode 27 respectively.

[0103] Step S10: A metal trace layer 31 and a fourth electrode 35 are formed on the interlayer dielectric layer 30.

[0104] Combination Figure 6k In step S10, a metal material can be deposited on the interlayer dielectric layer 30, and then the metal material can be etched to form the metal trace layer 31 and the fourth electrode 35.

[0105] The metal trace layer 31 includes multiple signal traces, which may include multiple scan lines and multiple data lines. The scan lines are connected to the gate 26 through vias penetrating the interlayer dielectric layer 30. The data lines are connected to the drain 25 through vias penetrating the interlayer dielectric layer 30. The anode 33 is connected to the data lines through vias penetrating the planarization layer 32 to receive the data signals transmitted by the data lines.

[0106] The second electrode 28 and the third electrode 37 are connected in parallel to form one pole of the storage capacitor, and the fourth electrode 35 can be connected in parallel with the first electrode 27 through a via penetrating the interlayer dielectric layer 30 and the gate insulating layer 29 to form the other pole of the storage capacitor.

[0107] Step S11: A planarization layer is formed on the metal trace layer, and a via is formed on the planarization layer.

[0108] Combination Figure 6l The planarization layer 32 covers the metal trace layer 31 and the fourth electrode 35, and the vias on the planarization layer 32 can expose the signal traces in the metal trace layer 31.

[0109] Step S12: An anode is formed on the planarization layer, and the anode is connected to the metal trace layer through a via penetrating the planarization layer.

[0110] Combination Figure 6m The anode 33 is formed on the planarization layer 32 and is connected to the signal traces in the metal trace layer 31 through vias in the planarization layer 32. The anode 33 can be made of a conductive transparent metal oxide material.

[0111] Step S13: A pixel definition layer, a light-emitting layer, and a cathode are sequentially formed on the anode.

[0112] Combination Figure 6n The pixel definition layer 34 is disposed on the planarization layer 32 and covers the anode 33. Multiple pixel openings are formed on the pixel definition layer 34, and the organic light-emitting material in the light-emitting layer can be formed within these pixel openings. Both the organic functional layer in the light-emitting layer and the cathode can be fully deposited on the pixel definition layer.

[0113] After completing step S13, an encapsulation layer can be formed on the cathode layer. The encapsulation layer can be formed by sequentially stacking an inorganic encapsulation layer, an organic encapsulation layer, and another inorganic encapsulation layer.

[0114] Based on the display panel provided in the above embodiments of this application, this application also provides an electronic device, which includes the display panel provided in the above embodiments. The electronic device can be a mobile terminal, such as color electronic paper, color e-book, smartphone, etc. The electronic device can also be a wearable terminal, such as smartwatch, smart bracelet, etc. The electronic device can also be a fixed terminal, such as color electronic billboard, color electronic poster, etc.

[0115] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a method for manufacturing the display panel. By using a halftone mask process, a first electrode and an oxide semiconductor layer made of the same metal oxide semiconductor material are successively conductiveized. Then, a gate insulating layer and a gate metal layer are deposited on top of the first electrode and the oxide semiconductor layer. Therefore, it is not necessary to make the first electrode made of metal oxide semiconductor material conductive by removing the gate insulating layer and the gate metal layer above the metal oxide semiconductor material. In this way, a storage capacitor can be formed by using the conductive first electrode and the gate metal layer above it. Since the thickness of the gate insulating layer is much smaller than the thickness of the dielectric layer, the distance between the upper and lower plates of the storage capacitor can be reduced, thereby increasing the capacitance value of the storage capacitor and improving the display defects caused by insufficient capacitance value of the storage capacitor.

[0116] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A method for manufacturing a display panel, characterized in that, include: Deposit a layer of metal oxide semiconductor material on a substrate; A first photoresist layer, a second photoresist layer with a thickness less than the first photoresist layer, and an opening exposing a portion of the metal oxide semiconductor material are formed on the metal oxide semiconductor material. The metal oxide semiconductor material is etched to form an oxide semiconductor layer covered by the first photoresist layer and a first electrode covered by the second photoresist layer; The first photoresist layer is thinned and the second photoresist layer is removed to expose the first electrode, and the first electrode is then made conductive. Remove the first photoresist layer to expose the oxide semiconductor layer, and sequentially deposit a gate insulating layer and a gate metal layer covering the oxide semiconductor layer and the first electrode on the substrate; The gate metal layer is etched to form a gate that is directly opposite the oxide semiconductor layer and a second electrode that is directly opposite the first electrode; Using the gate as a self-aligned mask, the gate insulating layer is etched to expose the opposite ends of the oxide semiconductor layer that are not covered by the gate. The opposite ends of the oxide semiconductor layer not covered by the gate are conductiveized to form the source and drain.

2. The method for manufacturing a display panel as described in claim 1, characterized in that, The steps of forming a first photoresist layer, a second photoresist layer with a thickness less than the first photoresist layer on the metal oxide semiconductor material, and exposing an opening in the metal oxide semiconductor material include: A photoresist material is deposited on the metal oxide semiconductor material; and The photoresist material is exposed using a halftone mask to form the first photoresist layer, the second photoresist layer, and the opening.

3. The method for manufacturing a display panel as described in claim 2, characterized in that, The steps of thinning the first photoresist layer and removing the second photoresist include: The first photoresist layer is thinned by etching using a plasma dry etching process, and the second photoresist layer is removed by etching.

4. A display panel, characterized in that, The display panel is manufactured by the method of any one of claims 1 to 3, wherein the display panel comprises: Base; A thin-film transistor, disposed on the substrate, the thin-film transistor including an oxide semiconductor layer; and A storage capacitor is disposed on the substrate, the storage capacitor including a first electrode and a second electrode disposed on the side of the first electrode opposite to the substrate; The first electrode and the oxide semiconductor layer are disposed on the same layer, and both the first electrode and the oxide semiconductor layer comprise the same metal oxide semiconductor material. The first electrode is conductive.

5. The display panel as described in claim 4, characterized in that, The thin-film transistor includes a gate disposed on the side of the oxide semiconductor layer opposite to the substrate; The second electrode is disposed on the same layer as the gate electrode and is made of the same material as the gate electrode.

6. The display panel as described in claim 5, characterized in that, The display panel further includes a channel shielding layer disposed between the oxide semiconductor layer and the substrate, and disposed opposite to the oxide semiconductor layer.

7. The display panel as described in claim 6, characterized in that, The storage capacitor includes a third electrode, which is disposed between the first electrode and the substrate, and the second electrode is electrically connected to the third electrode; The third electrode is disposed on the same layer as the channel shielding layer and is made of the same material as the channel shielding layer.

8. The display panel as described in claim 7, characterized in that, The storage capacitor further includes a fourth electrode, which is disposed on the side of the second electrode opposite to the first electrode, and the first electrode is electrically connected to the fourth electrode.

9. The display panel as described in claim 7, characterized in that, The display panel includes a dielectric layer disposed between the third electrode and the first electrode, and a gate insulating layer disposed between the first electrode and the second electrode; The thickness of the gate insulating layer is less than the thickness of the dielectric layer.

10. The display panel as claimed in claim 4, characterized in that, The display panel also includes multiple wires, which are disposed on the same layer as the first electrode and are made of the same material as the first electrode. The wires are conductive.

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