Electronic device

Abstract

The application discloses an electronic device. It comprises a first substrate, a semiconductor layer, a first metal layer and a second metal layer; the semiconductor layer comprises a plurality of active parts, each active part comprising a source contact sub-part and a drain contact sub-part; the first metal layer is arranged on the side of the semiconductor layer away from the first substrate and comprises a plurality of sources and a plurality of data lines, one end of a source is electrically connected with a data line, and the other end is electrically connected with the source contact sub-part of an active part; the second metal layer is arranged on the side of the semiconductor layer away from the first substrate and is arranged in a layer different from the first metal layer, the second metal layer comprises a plurality of drains, and one drain is electrically connected with the drain contact sub-part of an active part; wherein the first metal layer comprises a plurality of data line groups, each data line group comprises a plurality of data lines, and the distance between any two adjacent data line groups is smaller than the distance between any two adjacent data lines in any data line group. The application can improve the resolution of the electronic device and reduce the process difficulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an electronic device. BACKGROUND

[0002] In the current electronic device, especially in the virtual reality (VR) device, due to the limitation of resolution, the viewing effect will be seriously affected, and the user will feel dizzy.

[0003] At present, on the array substrate of the electronic device, the source electrode, the drain electrode and the data line of the thin film transistor need to be arranged in the same metal layer, and the line width and the line distance made by the existing panel factory exposure equipment are limited, and a certain distance needs to be reserved between the source electrode, the drain electrode and the data line to reserve space and reduce the parasitic capacitance, therefore, it is difficult to compress the space on one side of the array substrate to improve the resolution. SUMMARY

[0004] The electronic device provided by the embodiment of the present application can save the wiring space and improve the resolution of the electronic device.

[0005] The electronic device provided by the embodiment of the present application comprises:

[0006] a first substrate;

[0007] a semiconductor layer arranged on one side of the first substrate, wherein the semiconductor layer comprises a plurality of active parts, and each active part comprises a source contact sub-part, a drain contact sub-part and a channel sub-part located between the source contact sub-part and the drain contact sub-part;

[0008] a first metal layer arranged on the side of the semiconductor layer away from the first substrate and comprising a plurality of source electrodes and a plurality of data lines, one end of one source electrode is electrically connected with a corresponding data line, and the other end is electrically connected with the source contact sub-part of one active part;

[0009] a second metal layer arranged on the side of the semiconductor layer away from the first substrate and arranged in a layer different from the first metal layer, wherein the second metal layer comprises a plurality of drain electrodes, and one drain electrode is electrically connected with the drain contact sub-part of one active part;

[0010] wherein the first metal layer comprises a plurality of data line groups, and each data line group comprises a plurality of data lines, and the distance between any two adjacent data line groups is smaller than the distance between any two adjacent data lines in any data line group.

[0011] In an embodiment of the present application, the second metal layer is disposed on a side of the first metal layer distal to the semiconductor layer, and the electronic device further comprises a spacer layer disposed between the first metal layer and the second metal layer.

[0012] In an embodiment of the present application, the plurality of data lines are arranged along a first direction and extend along a second direction, the first direction being different from the second direction, and a footprint of a drain on the first substrate corresponds to a space between footprints of two adjacent data lines in a corresponding data line group on the first substrate.

[0013] In an embodiment of the present application, a width of each drain along the first direction is greater than or equal to 2 micrometers.

[0014] In an embodiment of the present application, a width of a drain along the first direction is equal to a space between two adjacent data lines in a corresponding data line group.

[0015] In an embodiment of the present application, a width of a drain along the first direction is less than a space between two adjacent data lines in a corresponding data line group.

[0016] In an embodiment of the present application, the electronic device comprises a plurality of pixel regions, and a pixel region corresponds to a data line group, each pixel region comprises a first sub-pixel region, a second sub-pixel region adjacent to the first sub-pixel region along the first direction, and a third sub-pixel region adjacent to the first sub-pixel region along the second direction.

[0017] Each data line group comprises a first data line, a second data line, and a third data line, the first sub-pixel region and the third sub-pixel region in a pixel region are both located between the first data line and the second data line in a corresponding data line group, and the second sub-pixel region in a pixel region is located between the second data line and the third data line in a corresponding data line group.

[0018] In an embodiment of the present application, the first data line in a data line group is adjacent to a third data line in an adjacent data line group, a distance between the first data line and the third data line in the adjacent data line groups is less than a distance between the first data line and the second data line in the data line group, or less than a distance between the second data line and the third data line in the data line group.

[0019] In an embodiment of the present application, the electronic device further comprises a second substrate disposed on the side of the first metal layer and the second metal layer away from the first substrate, and a color resist layer disposed on the side of the second substrate close to the first substrate, the color resist layer comprising a plurality of first color resist blocks, a plurality of second color resist blocks and a plurality of third color resist blocks disposed corresponding to the pixel regions;

[0020] wherein a first color resist block is disposed corresponding to a first sub-pixel region and partially overlaps with the adjacent first data line and the second data line, a second color resist block is disposed corresponding to a second sub-pixel region and partially overlaps with the adjacent second data line and the third data line, and a third color resist block is disposed corresponding to a third sub-pixel region and partially overlaps with the adjacent first data line and the second data line.

[0021] In an embodiment of the present application, the length of the overlapping part of the first color resist block and the first data line along the first direction is equal to the width of the first data line along the first direction, and the length of the overlapping part of the first color resist block and the second data line along the first direction is less than the width of the second data line along the first direction.

[0022] The length of the overlapping part of the second color resist block and the second data line along the first direction is less than the width of the second data line along the first direction, and the length of the overlapping part of the second color resist block and the third data line along the first direction is equal to the width of the third data line along the first direction.

[0023] The length of the overlapping part of the third color resist block and the first data line along the first direction is equal to the width of the first data line along the first direction, and the length of the overlapping part of the third color resist block and the second data line along the first direction is less than or equal to the width of the second data line along the first direction.

[0024] In an embodiment of the present application, each pixel region further comprises a fourth sub-pixel region adjacent to the third sub-pixel region along the first direction and adjacent to the second sub-pixel region along the second direction, and the third color resist block is disposed in the third sub-pixel region and partially extends to the fourth sub-pixel region.

[0025] In an embodiment of the present application, each source electrode is connected to a data line, and each source electrode is connected to a corresponding drain electrode through a corresponding active region, and the plurality of drain electrodes comprises a first drain electrode corresponding to the first data line, and in each pixel region, the first drain electrode is disposed in the fourth sub-pixel region.

[0026] In an embodiment of the present application, the plurality of drain electrodes further comprises a second drain electrode corresponding to the second data line, the plurality of source electrodes comprises a third source electrode corresponding to the third data line, and the first drain electrode, the second drain electrode and the third source electrode are arranged along the first direction and located between two adjacent pixel regions along the second direction.

[0027] In an embodiment of the present application, the electronic device further comprises a third metal layer disposed on the side of the first metal layer and the second metal layer close to the semiconductor layer, and the third metal layer comprises a plurality of scan lines extending along the first direction and arranged along the second direction, each of the scan lines is located between two adjacent pixel regions arranged along the second direction, and the first drain electrode, the second drain electrode and the third source electrode are located on the side of the scan lines away from the first substrate.

[0028] In an embodiment of the present application, the electronic device further comprises a black matrix layer disposed on the side of the second substrate close to the first substrate, and the black matrix layer surrounds each of the first sub-pixel region, each of the second sub-pixel region and each of the third sub-pixel region.

[0029] In an embodiment of the present application, the electronic device further comprises a black matrix layer disposed on the side of the second substrate close to the first substrate, and the black matrix layer surrounds each of the first sub-pixel region, each of the second sub-pixel region and each of the third sub-pixel region.

[0030] In an embodiment of the present application, the black matrix layer comprises a first sub-portion disposed between the first sub-pixel region and the third sub-pixel region and located between two adjacent scan lines, and a second sub-portion disposed between two adjacent pixel regions along the second direction, and the length of the first sub-portion along the second direction is less than the length of the second sub-portion along the second direction.

[0031] In an embodiment of the present application, the electronic device further comprises a black matrix layer disposed on the side of the second substrate close to the first substrate, and the black matrix layer surrounds each of the first sub-pixel region, each of the second sub-pixel region and each of the third sub-pixel region.

[0032] The beneficial effects of the present application are as follows: the present application sets the source electrode and the data line in the first metal layer, sets the drain electrode in the second metal layer, and further sets the drain electrode in a different layer from the source electrode and the data line, so that the first metal layer and the second metal layer can have more wiring space, reduce the difficulty of the process, improve the resolution of the electronic device, and each data line group includes a plurality of data lines, the distance between any two adjacent data line groups is less than the distance between any two adjacent data lines in any data line group, that is, the distance between the two adjacent data line groups can be reduced at least, more wiring space is saved, and the resolution of the electronic device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0034] Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in the figure.

[0035] Figure 2 A distribution structure schematic diagram of a data line in a display panel provided by an embodiment of the present application is shown in the figure.

[0036] Figure 3 A distribution structure schematic diagram of a data line in a display panel provided by an embodiment of the present application is shown in the figure.

[0037] Figure 4 A distribution structure schematic diagram of a data line and a drain electrode provided by an embodiment of the present application is shown in the figure.

[0038] Figure 5 A distribution structure schematic diagram of a data line and a drain electrode provided by an embodiment of the present application is shown in the figure.

[0039] Figure 6 A distribution structure schematic diagram of a data line and a drain electrode provided by an embodiment of the present application is shown in the figure.

[0040] Figure 7 A planar wiring schematic diagram of a display panel provided by an embodiment of the present application is shown in the figure.

[0041] Figure 8 A planar distribution schematic diagram of a pixel area of a display panel provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] The disclosure that follows provides many different embodiments, or examples, for implementing different structures of the application. For the purpose of simplicity, the elements and settings of the various examples are described in their most specific combinations. It is clear, however, that the application is not limited to the specific combinations described, but rather, the specific combinations can be selected from the various elements and settings to achieve the application. In addition, the disclosure provides examples of various specific processes and materials, but it is understood that other processes and / or materials can be used.

[0044] The electronic device according to the embodiment of the present application includes a first substrate 10, a semiconductor layer 20, a first metal layer 30, and a second metal layer 40. Figure 1 and Figure 2 The electronic device according to the embodiment of the present application includes a first substrate 10, a semiconductor layer 20, a first metal layer 30, and a second metal layer 40.

[0045] The semiconductor layer 20 is disposed on one side of the first substrate 10, and includes a plurality of active portions 21. Each active portion 21 includes a source contact sub-portion 211, a drain contact sub-portion 212, and a channel sub-portion 213 between the source contact sub-portion 211 and the drain contact sub-portion 212. The first metal layer 30 is disposed on the side of the semiconductor layer 20 distal to the first substrate 10, and includes a plurality of sources 31 and a plurality of data lines 32. One end of each source 31 is electrically connected to one data line 32, and the other end is electrically connected to the source contact sub-portion 211 of one active portion 21. The second metal layer 40 is disposed on the side of the semiconductor layer 20 distal to the first substrate 10, and is disposed in a layer different from the first metal layer 30. The second metal layer 40 includes a plurality of drains 41, and each drain 41 is electrically connected to the drain contact sub-portion 212 of one active portion 21.

[0046] Further, the first metal layer 30 includes a plurality of data line groups 33, and each data line group 33 includes a plurality of data lines 32. The distance between any two adjacent data line groups 33 is less than the distance between any two adjacent data lines 32 within any data line group 33.

[0047] In the implementation process, please refer to Figure 3In the existing display panel, a plurality of data signal lines 1 arranged in a vertical direction and a plurality of scan signal lines 2 arranged in a horizontal direction are included, and a plurality of sub-pixel regions 5 are defined by the intersection of the data signal lines 1 and the scan signal lines 2, each of the sub-pixel regions 5 corresponds to a source electrode 3 and a drain electrode 4, wherein the source electrode 3 is electrically connected with the data signal line 1, so as to transmit the data signal through the drain electrode 4 to the corresponding sub-pixel region 5. Wherein, the data signal line 1, the source electrode 3 and the drain electrode 4 are located in the same metal layer, and the line width and line distance of the existing exposure equipment is about 1.5 microns, and the spacing between the drain electrode 4 and the source electrode 3, the data signal line 1 needs to be reserved to provide process space and reduce parasitic capacitance, thereby it is difficult to effectively improve the resolution under the premise of a certain display panel area. However, please refer to Figure 2 In the embodiment of the present application, the source electrode 31 and the data line 32 are arranged in the first metal layer 30, and the drain electrode 41 is arranged in the second metal layer 40, and the drain electrode 41 is arranged in a different layer from the source electrode 31 and the data line 32, so that the first metal layer 30 and the second metal layer 40 have more wiring space, reduce the process difficulty, and improve the resolution of the electronic device. And each data line group 33 includes a plurality of data lines 32, the distance between any two adjacent data line groups 33 is less than the distance between any two adjacent data lines 32 in any data line group 33, that is, the distance between the two adjacent data line groups 33 can be reduced at least, and more wiring space is saved. The first metal layer 30 and the second metal layer 40 have more space for wiring, and the resolution of the electronic device is improved.

[0048] Specifically, please continue to refer to Figure 1 And Figure 2 The electronic device provided by the embodiment of the present application includes a display area 101 and a non-display area 102, and the electronic device further includes a first substrate 10, a light shielding layer 61 arranged on the first substrate 10, a first insulating layer 71 arranged on the first substrate 10 and covering the light shielding layer 61, a semiconductor layer 20 arranged on the first insulating layer 71, a second insulating layer 72 arranged on the first insulating layer 71 and covering the semiconductor layer 20, a third metal layer 50 arranged on the second insulating layer 72, a third insulating layer 73 arranged on the second insulating layer 72 and covering the third metal layer 50, a first metal layer 30 arranged on the third insulating layer 73, a spacing layer 74 arranged on the third insulating layer 73 and covering the first metal layer 30, a second metal layer 40 arranged on the spacing layer 74, an interlayer dielectric layer 75 arranged on the spacing layer 74 and covering the second metal layer 40, a pixel electrode layer arranged on the interlayer dielectric layer 75, a passivation layer 76 arranged on the interlayer dielectric layer 75 and covering the pixel electrode layer, and a common electrode layer arranged on the passivation layer 76.

[0049] Optionally, the materials of the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the spacing layer 74, the interlayer dielectric layer 75 and the passivation layer 76 can be organic insulating materials or inorganic insulating materials, for example, the organic insulating material can be polyimide, the inorganic insulating material can be silicon nitride or silicon oxide, etc., which are not limited herein.

[0050] It should be noted that, in the above film layer structure, the semiconductor layer 20 includes a plurality of active parts 21 arranged in the display area 101, the third metal layer 50 includes a plurality of gate electrodes 51, a plurality of scan lines 52 arranged in the display area 101 and a first connecting part 53 arranged in the non-display area 102, the first metal layer 30 includes a plurality of source electrodes 31 and a plurality of data lines 32 arranged in the display area 101, the second metal layer 40 includes a plurality of drain electrodes 41 arranged in the display area 101 and a second connecting part 42 arranged in the non-display area 102, the pixel electrode layer includes a pixel electrode 62 arranged in the display area 101 and a third connecting part 64 arranged in the non-display area 102, and the common electrode layer includes a common electrode arranged in the display area 101 and a fourth connecting part 65 arranged in the non-display area 102.

[0051] Further, each active part 21 corresponds to a light shielding layer 61, a source electrode 31, a drain electrode 41, a gate electrode 51 and an active part 21 correspond to each other and constitute a thin film transistor device, wherein each active part 21 includes a source electrode contact sub-part 211, a drain electrode contact sub-part 212 and a channel sub-part 213 between the source electrode contact sub-part 211 and the drain electrode contact sub-part 212, and each source electrode 31 is electrically connected to the source electrode contact sub-part 211 of the corresponding active part 21, and each drain electrode 41 is electrically connected to the drain electrode contact sub-part 212 of the corresponding active part 21. Specifically, each source electrode 31 is electrically connected to the corresponding source electrode contact sub-part 211 through a first via hole arranged between the first metal layer 30 and the semiconductor layer 20, each drain electrode is electrically connected to the corresponding drain electrode contact sub-part 212 through a second via hole arranged between the second metal layer 40 and the semiconductor layer 20, and each gate electrode 51 is located above the corresponding active part 21.

[0052] In addition, the plurality of data lines 32 are arranged along the first direction X and extend along the second direction Y, each source electrode 31 is electrically connected to a corresponding data line 32, and each data line 32 transmits a data signal through a corresponding source electrode 31, a corresponding active part 21 of the source electrode 31 and a drain electrode 41.

[0053] In the embodiment of the present application, the pixel electrode 62 is overlapped with the drain electrode 41 through a third via hole passing through the interlayer dielectric layer 75, and the drain electrode 41 can transmit a data signal in a corresponding data line 32 to the pixel electrode 62.

[0054] The passivation layer 76 conformally covers the third via, and the common electrode 63 also conformally covers the third via and can form an electric field between the pixel electrode 62. In addition, the electronic device provided by the embodiment of the present application further comprises a filling portion 66 arranged in the third via to fill the third via and improve the flatness of the film layer.

[0055] Please refer to Figure 4 In the prior art, the drain electrode 4 is located between two adjacent data signal lines 1, and the line width of the data signal line 1 is L, and the line spacing is L+3S. Since the process technology is limited and the space is limited, L and S have limit values, and after reaching the limit values, L and S cannot be further reduced, thereby limiting the increase of the number of data signal lines 1 and the increase of the resolution of the electronic device. In addition, in the prior art, since the drain electrode 4 and the data signal line 1 are arranged in the same layer, if the line width and the line spacing of the data signal line 1 are reduced to reach the limit value in order to improve the resolution, the circuit or the open circuit between the electrodes and the signal lines in the same layer is easily caused, which seriously affects the yield of the electronic device.

[0056] However, in the embodiment of the present application, please refer to Figure 5 and Figure 6 Since the drain electrode 41 and the data line 32 are located in different film layers, the influence of the spacing and the width between the drain electrode 41 and the data line 32 does not need to be considered, that is, the width of the drain electrode 41 along the first direction X can be less than the spacing between the two adjacent data lines 32, as shown in Figure 5 , or equal to the spacing between the two adjacent data lines 32, as shown in Figure 6 . In the embodiment of the present application, the drain electrode 41 and the data line 32 are arranged in different layers, so that a large amount of space can be reserved for wiring, which can improve the resolution while ensuring the yield of the electronic device.

[0057] In the embodiment of the present application, the first metal layer 30 comprises a plurality of data line groups 33 arranged along the first direction X, and each data line group 33 comprises a plurality of data lines 32. In the embodiment of the present application, the distance between the two adjacent data line groups 33 is less than the distance between the two adjacent data lines 32 in any data line group 33. In the embodiment of the present application, the orthographic projection of each drain electrode 41 on the first substrate 10 is located between the orthographic projections of the two adjacent data lines 32 in each data line group 33 on the first substrate 10, that is, no drain electrode 41 is arranged between the two adjacent data line groups 33.

[0058] It should be noted that in the prior art, due to the limitation of wiring space and process, the limit value of the width of the drain electrode along the horizontal direction is generally 1.5 microns, and in the embodiment of the present application, the width of the drain electrode 41 along the first direction X can be greater than or equal to 2 microns.

[0059] Please continue to refer toFigure 1 and Figure 2 The electronic device provided by the embodiment of the present application further comprises a plurality of pixel regions arranged in the display region 101, and each pixel region comprises a first sub-pixel region 1011, a second sub-pixel region 1012 and a third sub-pixel region 1013, wherein the second sub-pixel region 1012 is adjacent to the first sub-pixel region 1011 along the first direction X, and the third sub-pixel region 1013 is adjacent to the first sub-pixel region 1011 along the second direction Y. Each sub-pixel region is provided with a pixel electrode and a corresponding thin film transistor device, and each sub-pixel region corresponds to a data line 32, that is, the corresponding data line 32 is electrically connected to the source 31 corresponding to each sub-pixel region, and transmits the data signal to the pixel electrode in the sub-pixel region through the corresponding active part 21 and drain 41.

[0060] In the embodiment of the present application, each data line group 33 corresponds to a sub-pixel region, that is, each data line group 33 comprises a first data line 321, a second data line 322 and a third data line 323.

[0061] Further, each first sub-pixel region 1011 and each third sub-pixel region 1013 are located between the first data line 321 and the second data line 322, and each second sub-pixel region 1012 is located between the second data line 322 and the third data line 323.

[0062] Further, in each data line group 33, the first data line 321, the second data line 322 and the third data line 323 are arranged in sequence along the first direction X, and the first data line 321 in one data line group 33 is adjacent to the third data line 323 in the adjacent data line group 33, and is spaced apart from the third data line 323 in the other adjacent data line group 33, and is spaced apart by one first data line 321, two second data lines 322 and one third data line 323. The distance between the adjacent first data line 321 and the third data line 323 in the adjacent two data line groups 33 is less than the distance between the first data line 321 and the second data line 322 in any data line group 33, or less than the distance between the second data line 322 and the third data line 323 in any data line group 33, and the distance between the first data line 321 and the second data line 322 in any data line group 33 is equal to the distance between the second data line 322 and the third data line 323 in any data line group 33.

[0063] Optionally, in the same data line group 33, the distance between the first data line 321 and the second data line 322 and the distance between the second data line 322 and the third data line 323 can be 5 microns, and the distance between the adjacent first data line 321 and the third data line 323 between the adjacent two data line groups 33 can be 1.5 microns.

[0064] In the embodiment of the present application, the first data line 321 transmits a data line signal to the pixel electrode in the first sub-pixel area 1011 through the corresponding source electrode 31, the active part 21 corresponding to the source electrode 31 and the drain electrode 41, the second data line 322 transmits a data line signal to the pixel electrode in the second sub-pixel area 1012 through the corresponding source electrode 31, the active part 21 corresponding to the source electrode 31 and the drain electrode 41, and the third data line 323 transmits a data line signal to the pixel electrode in the third sub-pixel area 1013 through the corresponding source electrode 31, the active part 21 corresponding to the source electrode 31 and the drain electrode 41. The plurality of source electrodes 31 includes the first source electrode 311 corresponding to the first data line 321, the second source electrode 312 corresponding to the second data line 322 and the third source electrode 313 corresponding to the third data line 323, and the plurality of drain electrodes 41 includes the first drain electrode 411 corresponding to the first data line 321, the second drain electrode 412 corresponding to the second data line 322 and the third drain electrode 413 corresponding to the third data line 323.

[0065] Please refer to Figure 1 , Figure 2 and Figure 7 , the orthographic projections of the first source electrode 311, the second source electrode 312 and the third source electrode 313 on the first substrate 10 are all within the coverage range of the orthographic projection of the data line 32 on the first substrate 10, and the first drain electrode 411, the second drain electrode 412 and the first source electrode 311 corresponding to the same pixel area are arranged along the first direction and located between the adjacent two pixel areas arranged along the second direction Y.

[0066] In the embodiment of the present application, the plurality of scan lines 52 extends along the first direction X and is arranged along the second direction Y, and any scan line 52 is located between the adjacent two pixel areas arranged along the second direction Y, i.e. the first drain electrode 411, the second drain electrode 412 and the first source electrode 311 are located on the side of the scan line 52 away from the first substrate 10.

[0067] Optionally, the distance between the adjacent two scan lines 52 along the second direction Y can be equal to 16 microns.

[0068] In addition, each pixel area further includes a fourth sub-pixel area 1014 adjacent to the third sub-pixel area 1013 along the first direction X and adjacent to the second sub-pixel area 1012 along the second direction Y, and the third drain electrode 413 is arranged in the fourth sub-pixel area 1014.

[0069] As mentioned above, the electronic device provided by the embodiment of the present application further includes a second substrate (not shown in the figure) arranged on the side of the first metal layer 30 and the second metal layer 40 away from the first substrate 10, and in the embodiment of the present application, the second substrate is located on the side of the second metal layer 40 away from the first metal layer 30.

[0070] It should be noted that in other embodiments of the present application, the second metal layer can also be arranged between the first metal layer and the semiconductor layer, which aims to arrange the drain and the data line, the source in different layers to provide more wiring space, and other arrangements such as the distribution of the sub-pixel area, the data line, the source and the drain can be arranged according to the embodiments of the present application, which will not be described here.

[0071] In the embodiments of the present application, the electronic device further comprises a black matrix layer 80 arranged on the side of the second substrate close to the first substrate 10 and a color resistance layer 90; wherein the black matrix layer 80 is arranged around each sub-pixel area and comprises a plurality of openings, the color resistance layer 90 comprises a plurality of color resistance blocks, and one sub-pixel area corresponds to one opening, one opening corresponds to one color resistance block, that is, one sub-pixel area can correspond to one color resistance block.

[0072] The orthographic projection of the scan line 52 on the first substrate 10, the orthographic projection of the first drain 411 on the first substrate 10, the orthographic projection of the second drain 412 on the first substrate 10 and the orthographic projection of the third source 313 on the first substrate 10 are all within the coverage range of the orthographic projection of the black matrix layer 80 on the first substrate 10.

[0073] Specifically, the black matrix layer 80 comprises a first sub-part 81 arranged between the first sub-pixel area 1011 and the third sub-pixel area 1013 and located between two adjacent scan lines 52, and a second sub-part 82 arranged between two adjacent pixel areas along the second direction Y, and the length of the first sub-part 81 along the second direction Y is less than the length of the second sub-part 82 along the second direction Y; wherein the orthographic projection of the scan line 52 on the first substrate 10, the orthographic projection of the first drain 411 on the first substrate 10, the orthographic projection of the second drain 412 on the first substrate 10 and the orthographic projection of the third source 313 on the first substrate 10 are all within the coverage range of the orthographic projection of the second sub-part 82 on the first substrate 10.

[0074] It can be understood that only part of the black matrix layer 80, such as the first sub-part 81 and the second sub-part 82, is shown in the embodiments of the present application, and the black matrix layer 80 also comprises other parts to be arranged around each sub-pixel area to avoid color mixing and other phenomena between adjacent sub-pixel areas.

[0075] In addition, the plurality of color resist blocks include a plurality of first color resist blocks 91, a plurality of second color resist blocks 92, and a plurality of third color resist blocks 93, wherein a first color resist block 91 is correspondingly arranged in a first sub-pixel region 1011 and partially overlaps with the adjacent first data line 321 and the second data line 322, a second color resist block 92 is correspondingly arranged in a second sub-pixel region 1012 and partially overlaps with the adjacent second data line 322 and the third data line 323, and a third color resist block 93 is correspondingly arranged in a third sub-pixel region 1013 and partially overlaps with the adjacent first data line 321 and the second data line 322.

[0076] Optionally, the first color resist block 91 can be a red color resist block, the second color resist block 92 can be a green color resist block, and the third color resist block 93 can be a blue color resist block.

[0077] Further, the length of the overlapping part of the first color resist block 91 and the first data line 321 along the first direction X is equal to the width of the first data line 321 along the first direction X, the length of the overlapping part of the first color resist block 91 and the second data line 322 along the first direction X is less than the width of the second data line 322 along the first direction X; the length of the overlapping part of the second color resist block 92 and the second data line 322 along the first direction X is less than the width of the second data line 322 along the first direction X, and the length of the overlapping part of the second color resist block 92 and the third data line 323 along the first direction X is equal to the width of the third data line 323 along the first direction X; the length of the overlapping part of the third color resist block 93 and the first data line 321 along the first direction X is equal to the width of the first data line 321 along the first direction X, and the length of the overlapping part of the third color resist block 93 and the second data line 322 along the first direction X is less than or equal to the width of the second data line 322 along the first direction X.

[0078] Optionally, the width of the first color resist block 91 along the first direction X, the width of the second color resist block 92 along the first direction X, and the width of the third color resist block 93 along the first direction X can all be equal to 8 microns.

[0079] Optionally, the third color resist block 93 can also be arranged in the third sub-pixel region 1013 and partially extend into the fourth sub-pixel region 1014.

[0080] Please refer to Figure 3 In the prior art, the display panel includes color resist 6 arranged in the sub-pixel region 5, and according to the existing process, the CD value of the color resist 6 can be maximally 5.6 microns, and the color crosstalk between adjacent color resists 6 and other phenomena need to be considered, so that the actual CD value needs to be smaller than 5.6 microns, or the distance between adjacent color resists 6 needs to be increased, so that it is difficult to increase the number of color resists 6 by compressing the CD value of the color resist 6 to improve the resolution of the display panel, and the CD of the color resist 6 cannot be compressed beyond the limit of the existing process. However, please refer toFigure 7 and Figure 8 In the embodiment of the present application, by changing the arrangement mode of the color resistance blocks, the three color resistance blocks 6 arranged in one row in the prior art is changed to two color resistance blocks, i.e., the first color resistance block 91 and the second color resistance block 92, arranged in one row, the third color resistance block 93 is moved to the other side of the first color resistance block 91, and the length of each color resistance block in the second direction Y is reduced, thereby the width and arrangement space of each color resistance block in the first direction X can be increased, thereby the process difficulty of each color resistance block can be reduced, and the resolution of the electronic device can be effectively improved.

[0081] In the embodiment of the present application, the distance from one end of the first sub-part 81 away from the adjacent second sub-part 82 to one end of the second sub-part 82 away from the adjacent first sub-part 81 is set as a first distance, and the length of each color resistance block in the second direction Y can be less than or equal to the first distance, i.e., the length of the first color resistance block 91 in the second direction Y, the length of the second color resistance block 92 in the second direction Y, and the length of the third color resistance block 93 in the second direction Y can all be less than or equal to the first distance.

[0082] The electronic device provided by the embodiment of the present application is also used in the field of VR display, and can effectively improve the resolution and display effect of the VR device. It should be noted that when the electronic device provided by the embodiment of the present application is used in the field of VR display, the space is small, and therefore the thin film transistor device in the embodiment of the present application includes a source electrode 31, a drain electrode 41, an active part 21, and a gate electrode 51, i.e., a single-gate structure, the thickness of the gate electrode 51 can be thickened to adjust the electrical properties of the thin film transistor device, and the specific selection can be made according to actual needs.

[0083] In summary, in the embodiment of the present application, the source electrode 31 and the data line 32 are arranged on the first metal layer 30, and the drain electrode 41 is arranged on the second metal layer 40, thereby the drain electrode 41 is arranged on a different layer from the source electrode 31 and the data line 32, a large amount of wiring space can be saved, each data line group 33 includes a plurality of data lines 32, the distance between any two adjacent data line groups 33 is less than the distance between any two adjacent data lines 32 in any data line group 33, i.e., the distance between the adjacent two data line groups 33 can be at least reduced to compress the space, and the first metal layer 30 and the second metal layer 40 are both wired by more space; in addition, the arrangement of the sub-pixel area is improved, sufficient space can be reserved for each color resistance block, the process difficulty of the color resistance block is reduced, and the resolution of the electronic device is effectively improved.

[0084] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0085] The above has carried out the detailed introduction to the electronic device provided by the embodiment of the application, the principle and implementation mode of the application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the technical scheme of the application and its core idea; ordinary skilled in the art should understand that: it can still modify the technical scheme recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. An electronic device, characterized in that, include: First substrate; A semiconductor layer is disposed on one side of the first substrate. The semiconductor layer includes a plurality of active portions, each of which includes a source contact portion, a drain contact portion, and a channel portion located between the source contact portion and the drain contact portion. A first metal layer is disposed on the side of the semiconductor layer away from the first substrate, and includes a plurality of sources and a plurality of data lines. One end of a source is electrically connected to a corresponding data line, and the other end is electrically connected to a source contact portion of an active portion. The plurality of data lines are arranged along a first direction and extend along a second direction, wherein the first direction and the second direction are different. A second metal layer is disposed on the side of the semiconductor layer away from the first substrate and is disposed in a different layer from the first metal layer. The second metal layer includes a plurality of drains, and one of the drains is electrically connected to the drain contact portion of the active portion. The first metal layer includes multiple data line groups, and each data line group includes multiple data lines. The distance between any two adjacent data line groups is less than the distance between any two adjacent data lines within any data line group. The electronic device includes multiple pixel regions, each of which includes a first sub-pixel region, a second sub-pixel region adjacent to the first sub-pixel region along the first direction, a third sub-pixel region adjacent to the first sub-pixel region along the second direction, and a fourth sub-pixel region adjacent to the third sub-pixel region along the first direction and adjacent to the second sub-pixel region along the second direction. Each data line group includes a first data line, a second data line, and a third data line. The first sub-pixel area and the third sub-pixel area in a pixel area are both located between the first data line and the second data line in the corresponding data line group. The second sub-pixel area in a pixel area is located between the second data line and the third data line in the corresponding data line group. The plurality of sources include a plurality of first sources, a plurality of second sources, and a plurality of third sources; the plurality of drains include a plurality of first drains, a plurality of second drains, and a plurality of third drains; the first data line is electrically connected to the pixel electrode of the first sub-pixel region through the first source and the first drain in sequence; the second data line is electrically connected to the pixel electrode of the second sub-pixel region through the second source and the second drain in sequence; and the third data line is electrically connected to the pixel electrode of the third sub-pixel region through the third source and the third drain in sequence. In the same pixel region and the corresponding data line group, the first drain is located between the first data line and the second data line, the second drain is located between the second data line and the third data line, and the third drain is located in the fourth sub-pixel region between the second data line and the third data line.

2. The electronic device according to claim 1, characterized in that, The second metal layer is disposed on the side of the first metal layer away from the semiconductor layer, and the electronic device further includes a spacer layer disposed between the first metal layer and the second metal layer.

3. The electronic device according to claim 1, characterized in that, The orthographic projection of the drain electrode on the first substrate corresponds to the orthographic projection of two adjacent data lines within the data line group on the first substrate.

4. The electronic device according to claim 3, characterized in that, The width of each drain electrode along the first direction is greater than or equal to 2 micrometers.

5. The electronic device according to claim 3, characterized in that, The width of the drain electrode along the first direction is less than or equal to the spacing between two adjacent data lines within the corresponding data line group.

6. The electronic device according to claim 1, characterized in that, The first data line in one of the data line groups is adjacent to the third data line in an adjacent data line group. The distance between the first data line and the third data line in the two adjacent data line groups is less than the distance between the first data line and the second data line in one data line group, or less than the distance between the second data line and the third data line in one data line group.

7. The electronic device according to claim 1, characterized in that, The electronic device further includes a second substrate disposed on the side of both the first metal layer and the second metal layer away from the first substrate, and a color resist layer disposed on the side of the second substrate close to the first substrate. The color resist layer includes a plurality of first color resist blocks, a plurality of second color resist blocks and a plurality of third color resist blocks disposed corresponding to each pixel area. Wherein, a first color resist block is disposed in a first sub-pixel area and partially overlaps with the adjacent first data line and the second data line; a second color resist block is disposed in a second sub-pixel area and partially overlaps with the adjacent second data line and the third data line; and a third color resist block is disposed in a third sub-pixel area and partially overlaps with the adjacent first data line and the second data line.

8. The electronic device according to claim 7, characterized in that, The length of the overlapping portion of the first color resist block and the first data line along the first direction is equal to the width of the first data line along the first direction, and the length of the overlapping portion of the first color resist block and the second data line along the first direction is less than the width of the second data line along the first direction. The length of the overlapping portion of the second color resist block and the second data line along the first direction is less than the width of the second data line along the first direction, and the length of the overlapping portion of the second color resist block and the third data line along the first direction is equal to the width of the third data line along the first direction. The length of the overlapping portion of the third color block and the first data line along the first direction is equal to the width of the first data line along the first direction, and the length of the overlapping portion of the third color block and the second data line along the first direction is less than or equal to the width of the second data line along the first direction.

9. The electronic device according to claim 7, characterized in that, The third color block is disposed within the third sub-pixel area and extends partially into the fourth sub-pixel area.

10. The electronic device according to claim 9, characterized in that... The first drain, the second drain, and the third source are arranged along the first direction and located between two adjacent pixel regions along the second direction.

11. The electronic device according to claim 10, characterized in that, The electronic device further includes a third metal layer disposed on the side of both the first metal layer and the second metal layer close to the semiconductor layer, and the third metal layer includes a plurality of scan lines extending along the first direction and arranged along the second direction, each scan line being located between two adjacent pixel regions arranged along the second direction, and the first drain, the second drain and the third source being located on the side of the scan lines away from the first substrate.

12. The electronic device according to claim 11, characterized in that, The electronic device further includes a black matrix layer disposed on the side of the second substrate close to the first substrate, and the black matrix layer is disposed around each of the first sub-pixel regions, each of the second sub-pixel regions and each of the third sub-pixel regions; The orthographic projections of the scan line, the first drain, the second drain, and the third source on the first substrate are all located within the coverage area of ​​the orthographic projection of the black matrix layer on the first substrate.

13. The electronic device according to claim 12, characterized in that, The black matrix layer includes a first sub-part disposed between the first sub-pixel region and the third sub-pixel region and located between two adjacent scan lines, and a second sub-part disposed between two adjacent pixel regions along the second direction, wherein the length of the first sub-part along the second direction is less than the length of the second sub-part along the second direction; The orthographic projection of the scan line on the first substrate, the orthographic projection of the first drain on the first substrate, the orthographic projection of the second drain on the first substrate, and the orthographic projection of the third source on the first substrate are all located within the coverage area of ​​the orthographic projection of the second sub-part on the first substrate.

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