Thin film transistor and method of manufacturing the same, electronic device

Abstract

This application provides a thin-film transistor (TFT), its fabrication method, and an electronic device. The TFT includes a substrate, an active layer, a gate layer, and source / drain layers. The active layer is disposed on one side of the substrate and includes a doped layer and a channel layer. The channel layer is disposed on the doped layer. The gate layer is disposed on the side of the active layer away from the substrate, and the source / drain layers are disposed on the side of the gate layer away from the active layer. The doped layer includes lightly doped and heavily doped portions, which are horizontally intersecting. The source / drain layers are connected to the heavily doped portions. By using the active layer as both the doped layer and the channel layer, during the crystallization of the channel layer, the high crystallization temperature causes the crystal within the doped layer to be in a molten state, leading to ion diffusion and direct formation of both the heavily doped and lightly doped portions. This eliminates the need for ion implantation, reducing the number of process steps in electronic device fabrication and improving fabrication efficiency.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor and its fabrication method, as well as electronic devices. Background Technology

[0002] In existing display devices, thin-film transistors (TFTs) are used for control. To improve the reliability of TFTs and reduce leakage current, existing TFTs incorporate a lightly doped region between the channel region and the heavily doped region. However, this design requires two ion implantations of the active layer, resulting in numerous fabrication steps and lower efficiency in the display device manufacturing process.

[0003] Therefore, existing display devices suffer from a technical problem where the fabrication efficiency is low because the active layer requires two ion implantations. Summary of the Invention

[0004] This application provides a thin-film transistor and its fabrication method, as well as an electronic device, to alleviate the technical problem that existing display devices require two ion implantations during the fabrication of the active layer, resulting in low fabrication efficiency.

[0005] This application provides a thin-film transistor, which includes:

[0006] Substrate;

[0007] An active layer is disposed on one side of the substrate, the active layer including a doped layer and a channel layer, the channel layer being disposed on the doped layer;

[0008] A gate layer is disposed on the side of the active layer away from the substrate;

[0009] The source and drain layers are disposed on the side of the gate layer away from the active layer;

[0010] The doped layer includes a lightly doped portion and a heavily doped portion, which are arranged to cross each other in a horizontal direction. The source and drain layers are connected to the heavily doped portion.

[0011] In some embodiments, the channel layer includes a channel portion, the lightly doped portion includes a first lightly doped portion and a second lightly doped portion, the heavily doped portion includes a first heavily doped portion and a second heavily doped portion, the first lightly doped portion is disposed between the first heavily doped portion and the channel portion, and the second heavily doped portion is disposed between the second lightly doped portion and the channel portion.

[0012] In some embodiments, the source-drain layer includes a source and a drain, the source being connected to the second heavily doped portion and the drain being connected to the first heavily doped portion.

[0013] In some embodiments, the projection of the gate layer onto the substrate overlaps with the projection of the first lightly doped portion onto the substrate.

[0014] In some embodiments, the channel layer has a via in the region corresponding to the heavily doped portion, the source and drain layers pass through the via and are connected to the heavily doped portion, and the sidewalls of the source and drain layers are in contact with the channel layer.

[0015] In some embodiments, the thin-film transistor further includes a gate insulating layer and an interlayer insulating layer. The gate insulating layer is disposed between the gate layer and the active layer, and the interlayer insulating layer is disposed between the gate layer and the source / drain layer. The interlayer insulating layer is in contact with the doped layer, and the source / drain layer is connected to the heavily doped portion through a via in the interlayer insulating layer.

[0016] In some embodiments, the material of the doped layer includes amorphous silicon doped with ions, wherein the concentration of doped ions in the lightly doped portion is less than the concentration of doped ions in the heavily doped portion.

[0017] In some embodiments, the thickness of the doped layer ranges from 200 angstroms to 1000 angstroms.

[0018] Meanwhile, this application provides a method for fabricating a thin-film transistor, which fabricates a thin-film transistor as described in any of the above embodiments. The method includes:

[0019] Provide substrate;

[0020] A doped layer is formed on the substrate;

[0021] A channel layer is formed on the doped layer, and the channel layer is crystallized using a blue laser diode annealing process to allow ion diffusion to occur in the doped layer in a molten state, resulting in lightly doped and heavily doped portions.

[0022] A gate layer is formed on the active layer;

[0023] Source and drain layers are formed on the gate layer.

[0024] Meanwhile, this application provides an electronic device, which includes a thin-film transistor as described in any of the above embodiments.

[0025] Beneficial Effects: This application provides a thin-film transistor and its fabrication method, as well as an electronic device. The thin-film transistor includes a substrate, an active layer, a gate layer, and source / drain layers. The active layer is disposed on one side of the substrate and includes a doped layer and a channel layer. The channel layer is disposed on the doped layer. The gate layer is disposed on the side of the active layer away from the substrate, and the source / drain layers are disposed on the side of the gate layer away from the active layer. The doped layer includes lightly doped and heavily doped portions, which are arranged horizontally and intersecting each other. The source / drain layers are connected to the heavily doped portions. By setting the active layer as both the doped layer and the channel layer, during the crystallization of the channel layer, due to the high crystallization temperature, the crystals within the doped layer are in a molten state, leading to ion diffusion. This allows for the direct formation of both heavily doped and lightly doped portions without the need for ion implantation, reducing the process steps in electronic device fabrication and improving the fabrication efficiency. Attached Figure Description

[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of a thin-film transistor provided in an embodiment of this application.

[0028] Figure 2 A flowchart illustrating a thin-film transistor fabrication method provided in an embodiment of this application.

[0029] Figure 3 This is a first schematic diagram of a thin-film transistor corresponding to each step in the fabrication method of the thin-film transistor provided in the embodiments of this application.

[0030] Figure 4 This is a second schematic diagram of the thin-film transistor corresponding to each step in the fabrication method of the thin-film transistor provided in the embodiments of this application.

[0031] Figure 5 A schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] This application addresses the technical problem of low fabrication efficiency in existing display devices due to the need for two ion implantations during the fabrication of the active layer, and provides a thin-film transistor, its fabrication method, and an electronic device thereof.

[0038] like Figure 1 As shown, this application embodiment provides a thin-film transistor, the thin-film transistor 1 including:

[0039] Substrate 11;

[0040] An active layer 13 is disposed on one side of the substrate 11. The active layer 13 includes a doped layer 134 and a channel layer 133, with the channel layer 133 disposed on the doped layer 134.

[0041] A gate layer 15 is disposed on the side of the active layer 13 away from the substrate 11;

[0042] The source-drain layer 17 is disposed on the side of the gate layer 15 away from the active layer 13;

[0043] The doped layer 134 includes a lightly doped portion 131 and a heavily doped portion 132, which are arranged to cross each other in the horizontal direction. The source-drain layer 17 is connected to the heavily doped portion 132.

[0044] This application provides a thin-film transistor. By setting the active layer as a doped layer and the channel layer, when the channel layer is crystallized, the crystal in the doped layer is in a molten state due to the high crystallization temperature, which leads to ion diffusion. This allows for the direct formation of heavily doped and lightly doped portions without the need for ion implantation, reducing the process steps in electronic device fabrication and improving the fabrication efficiency of electronic devices.

[0045] Specifically, such as Figure 1As shown, compared to current display devices where the active layer places the lightly doped region between the heavily doped region and the channel region, but this approach requires ion implantation on both sides, the embodiment of this application achieves the active layer 13, including a lightly doped portion 131 and a heavily doped portion 132, through ion diffusion of the doped layer, without the need for ion implantation. However, since laser annealing is performed in one direction during the fabrication process, the direction of ion diffusion is along the direction of laser annealing, resulting in the lightly doped portion 131 and the heavily doped portion being interleaved in the active layer, rather than the lightly doped portion being located between the heavily doped portion and the channel region. Figure 1 As can be seen, from right to left along the horizontal direction, there are the first heavily doped part 132a, the first lightly doped part 131a, the second heavily doped part 132b, and the second lightly doped part 131b, that is, the heavily doped part and the lightly doped part are arranged alternately.

[0046] In one embodiment, such as Figure 1 As shown, the channel layer 133 includes a channel portion 133a, the lightly doped portion 131 includes a first lightly doped portion 131a and a second lightly doped portion 131b, and the heavily doped portion 132 includes a first heavily doped portion 132a and a second heavily doped portion 132b. The first lightly doped portion 131a is disposed between the first heavily doped portion 132a and the channel portion 133a, and the second heavily doped portion 132b is disposed between the second lightly doped portion 131b and the channel portion 133a. By sequentially arranging the first heavily doped portion, the first lightly doped portion, the channel portion, the second heavily doped portion, and the second lightly doped portion, the source and drain layers can be connected to the first heavily doped portion and the second heavily doped portion, realizing a lightly doped drain region structure and reducing leakage current. Furthermore, the first heavily doped portion, the first lightly doped portion, the channel portion, the second heavily doped portion, and the second lightly doped portion can be formed by diffusion of the heavily doped portion, eliminating the need for ion implantation, reducing process steps, lowering costs, and improving the fabrication efficiency of thin-film transistors.

[0047] This addresses the technical problem that high leakage current in thin-film transistors leads to lower reliability. In one embodiment, such as... Figure 1 As shown, the source-drain layer 17 includes a source 171 and a drain 172. The source 171 is connected to the second heavily doped portion 132b, and the drain 172 is connected to the first heavily doped portion 132a. By connecting the source to the second heavily doped portion and the drain to the first heavily doped portion, when the thin-film transistor is working, the charge carriers will move along the source, the second heavily doped portion, the first lightly doped portion, the first heavily doped portion, and the drain. Therefore, when the thin-film transistor is in the off state, due to the presence of the first lightly doped portion and the first heavily doped portion, there is no voltage driving the charge carriers, making it difficult for them to move to the drain and generate current. This reduces the leakage current of the thin-film transistor and improves its reliability.

[0048] Specifically, such as Figure 1 As shown, the source 171 is connected to the second heavily doped section 132b and the drain 172 is connected to the first heavily doped section 132a. It can be seen that a first lightly doped section 131a is provided between the channel section 133a and the first heavily doped section 132a. When driving the thin film transistor, the charge carriers need to travel from the channel section 133a to the first lightly doped section 131a and then to the first heavily doped section 132a. However, when the thin film transistor is not driven by voltage, the impedance of the first lightly doped section is relatively large, which prevents the charge carriers from reaching the drain to form a leakage current, thereby reducing the leakage current of the thin film transistor and improving the reliability of the thin film transistor.

[0049] Specifically, such as Figure 1 As shown, Figure 1 The diagram shows a first lightly doped portion 131a located to the right of a second heavily doped portion 132b, and a drain 172 located to the right of a source 171. However, the embodiments of this application are not limited to this. For example, if the first lightly doped portion is located to the left of the second heavily doped portion, then the drain is located to the left of the source. In this case, the doped layer includes a second lightly doped portion, a second heavily doped portion, a first lightly doped portion, and a first heavily doped portion arranged sequentially from right to left. The source is connected to the second heavily doped portion, and the drain is connected to the first heavily doped portion, thereby reducing leakage current and improving the reliability of the thin-film transistor.

[0050] This addresses the technical problem that the presence of undiffused regions outside the channel of a thin-film transistor (TFT) leads to high resistance and consequently low TFT mobility. In one embodiment, such as... Figure 1 As shown, the projection of the gate layer 15 onto the substrate 11 overlaps with the projection of the first lightly doped portion 131a onto the substrate 11. By making the projection of the gate layer onto the substrate overlap with the projection of the first lightly doped portion onto the substrate, the region outside the channel becomes a region with ion diffusion, reducing the resistance of the active layer outside the channel, improving the mobility of the thin-film transistor, and avoiding the region outside the channel being a region without ion diffusion, which would result in excessive resistance and low mobility of the thin-film transistor.

[0051] Specifically, such as Figure 1 As shown, at least a portion of the projection of the first lightly doped portion 131a onto the substrate 11 is located within the projection of the gate layer 15 onto the substrate 11, so that the active layer outside the corresponding region of the gate layer is ion-doped, thereby reducing the impedance of the active layer outside the channel portion and improving the mobility of the thin film transistor.

[0052] Specifically, the projection of the gate layer on the substrate is in contact with the projection of the heavily doped portion on the substrate, so that the boundary of the projection of the second heavily doped portion on the substrate is in contact with the boundary of the projection of the gate layer on the substrate. The impedance of the active layer located on the side of the second heavily doped portion is smaller, thereby improving the mobility of the thin film transistor.

[0053] Specifically, the gate layer materials include copper and molybdenum. Using copper and molybdenum as gate layer materials improves the conductivity of the gate layer.

[0054] Specifically, the thickness of the gate layer ranges from 2000 angstroms to 5500 angstroms, making the gate layer thicker and reducing its impedance.

[0055] In one embodiment, such as Figure 1 As shown, the channel layer 133 has vias in the region corresponding to the heavily doped portion 132. The source / drain layer 17 passes through the vias and connects to the heavily doped portion 132, with the side surface of the source / drain layer 17 contacting the channel layer 133. By forming vias in the channel layer, the source / drain layer can be connected to the heavily doped portion. Therefore, when the thin-film transistor is operating, signals can be transmitted through the connection between the source / drain layer and the heavily doped portion, avoiding excessive impedance in the channel portion that could prevent the thin-film transistor from transmitting signals.

[0056] Specifically, when the channel layer is placed on the doped layer, in order to connect the source and drain layers to the doped layer, vias can be made in the channel layer so that the source and drain layers can pass through the vias to connect to the doped layer, thus avoiding excessive impedance in the channel section that would prevent the thin-film transistor from transmitting signals.

[0057] Specifically, when a via is formed in the channel layer, the source and drain layers will directly contact the channel layer. However, due to the high impedance of the channel layer, it is difficult for charge carriers to pass through the channel layer, and the thin film transistor cannot transmit signals. Therefore, the source and drain layers can be made to contact the side of the channel layer to reduce the complexity of the process.

[0058] Specifically, such as Figure 1 As shown, the thin-film transistor 1 further includes a gate insulating layer 14 and an interlayer insulating layer 16. The gate insulating layer 14 is disposed between the gate layer 15 and the active layer 13, and the interlayer insulating layer 16 is disposed between the gate layer 15 and the source / drain layer 17. The gate insulating layer 14 and the interlayer insulating layer 16 have vias formed in each other. The source / drain layer 17 passes through the vias in the gate insulating layer 14 and the interlayer insulating layer 16 and connects to the heavily doped portion 132. When connecting the source / drain layer to the heavily doped portion, vias can be formed in the interlayer insulating layer, the gate insulating layer, and the channel layer. The source / drain layer can connect to the heavily doped portion through these vias, allowing signals to be transmitted along the source, the heavily doped portion, the channel portion, and the drain, preventing the source / drain from only contacting the channel portion, where excessive impedance would prevent the thin-film transistor from transmitting signals.

[0059] Specifically, the gate insulating layer material includes silicon oxide or a stack of silicon nitride and silicon oxide. By using a stack of silicon oxide or silicon nitride and silicon oxide as the gate insulating layer material, the insulation effect of the gate insulating layer is improved, and the ability of the thin film transistor to block water and oxygen is enhanced.

[0060] Specifically, the thickness of the gate insulating layer ranges from 1000 angstroms to 2000 angstroms. By making the thickness of the gate insulating layer range from 1000 angstroms to 2000 angstroms, short circuits caused by contact between the gate and the active layer are avoided, allowing the thin-film transistor to work normally.

[0061] Specifically, the interlayer insulating layer material includes silicon oxide or a stack of silicon nitride and silicon oxide. By using a stack of silicon oxide or silicon nitride and silicon oxide as the interlayer insulating layer material, the insulation effect of the interlayer insulating layer is improved, and the ability of the thin film transistor to block water and oxygen is enhanced.

[0062] Specifically, the thickness of the interlayer insulating layer ranges from 2000 angstroms to 6000 angstroms. This range helps to prevent excessive parasitic capacitance between the source / drain layer and the gate layer from causing a performance degradation in the thin-film transistor.

[0063] This invention addresses the technical problem that direct contact between the source / drain layers and the channel, or direct contact between the channel and the heavily doped portion, can lead to leakage current in thin-film transistors (TFTs) and result in poor device performance. In one embodiment, the TFT further includes a gate insulating layer and an interlayer insulating layer. The gate insulating layer is disposed between the gate layer and the active layer, and the interlayer insulating layer is disposed between the gate layer and the source / drain layers. The interlayer insulating layer contacts the doped layer, and the source / drain layers connect to the heavily doped portion through vias in the interlayer insulating layer. By making the interlayer insulating layer contact the doped layer and etching the gate insulating layer and the channel layer, the source / drain layers can directly connect to the heavily doped portion without contacting the channel layer, thereby preventing leakage current in the TFT and improving its performance.

[0064] Specifically, when forming a thin-film transistor, after forming the gate layer, the gate insulating layer and the channel layer can be etched to expose the heavily doped portion. Then, an interlayer insulating layer is formed on the gate layer, and vias are formed in the interlayer insulating layer so that the source and drain layers can pass through the vias to connect to the doped layer, thereby avoiding leakage current in the thin-film transistor and improving its performance.

[0065] In one embodiment, the doped layer material comprises ion-doped amorphous silicon, wherein the concentration of doped ions in the lightly doped region is less than the concentration of doped ions in the heavily doped region. By using ion-doped amorphous silicon as the material of the doped layer, during the formation of the active layer and the crystallization of the channel layer by laser annealing, the amorphous silicon of the doped layer can be kept in a molten state. Ion diffusion automatically occurs in the doped layer to form lightly doped and heavily doped regions, eliminating the need for ion implantation, reducing the number of process steps in electronic device fabrication, and improving the fabrication efficiency of electronic devices. Furthermore, the ion concentration in the lightly doped region is less than that in the heavily doped region, thereby enabling the thin-film transistor to form a lightly doped drain region structure, reducing leakage current and improving the performance of the thin-film transistor.

[0066] In one embodiment, the thickness of the doped layer ranges from 200 angstroms to 1000 angstroms. By making the thickness of the doped layer range from 200 angstroms to 1000 angstroms, it avoids the doped layer being etched through due to its thinness, and also avoids the impedance being too high due to its thinness. At the same time, the thickness of the doped layer is not too large, which would result in an excessively large device size for the thin-film transistor.

[0067] Specifically, the thickness of the doped layer is 200 to 600 angstroms.

[0068] To address the technical problem that the performance of the active layer deteriorates when exposed to light, in one embodiment, the thin-film transistor further includes a light-shielding layer disposed between the substrate and the active layer. The projection of the light-shielding layer onto the substrate at least covers the projection of the channel layer onto the substrate. By ensuring that the projection of the light-shielding layer onto the substrate at least covers the projection of the channel layer onto the substrate, the light-shielding layer can prevent external light from illuminating the channel portion, thus preventing the active layer from experiencing performance degradation due to light exposure.

[0069] Specifically, the thickness of the light-shielding layer ranges from 2000 angstroms to 5500 angstroms. By making the thickness of the light-shielding layer from 2000 angstroms to 5500 angstroms, the light-shielding layer has a better light-blocking effect and a lower impedance. When the light-shielding layer is connected to other film layers, it can reduce the impedance of other film layers.

[0070] Specifically, the material of the light-shielding layer includes at least one of molybdenum and aluminum.

[0071] In one embodiment, such as Figure 1 As shown, the thin-film transistor 1 further includes a buffer layer 12, which is disposed between the substrate 11 and the active layer 13. By providing a buffer layer between the substrate and the active layer, the buffer layer can block water and oxygen, preventing water and oxygen intrusion from causing performance degradation of the thin-film transistor and improving the thin-film transistor's ability to block water and oxygen.

[0072] Specifically, the buffer layer material includes silicon oxide or a stack of silicon nitride and silicon oxide. Using a stack of silicon oxide or silicon nitride and silicon oxide as the buffer layer material improves the buffer layer's ability to block water and oxygen.

[0073] Specifically, the thickness of the buffer layer ranges from 1500 angstroms to 4000 angstroms. By making the thickness of the buffer layer range from 1500 angstroms to 4000 angstroms, the buffer layer has a good ability to block water and oxygen, and the thickness of the buffer layer is not too large, which would cause the size of the thin film transistor to be too large.

[0074] In one embodiment, the channel layer material includes polycrystalline silicon, so that the channel portion is made of polycrystalline silicon. When the amorphous silicon is laser annealed and crystallized, the amorphous silicon of the doped layer can undergo ion diffusion in the molten state without ion implantation, thereby enabling the thin film transistor to form a lightly doped drain region structure, reducing leakage current and improving the performance of the thin film transistor.

[0075] At the same time, such as Figure 2 As shown, this application provides a method for fabricating a thin-film transistor, which fabricates a thin-film transistor as described in any of the above embodiments. The method includes:

[0076] S1, providing a substrate; the structure of the thin-film transistor corresponding to this step is as follows: Figure 3 As shown in (a) in the middle;

[0077] Specifically, after providing the substrate, the process further includes: forming a light-shielding layer on the substrate, which can be achieved by physical vapor deposition, and then forming a patterned light-shielding layer by photolithography and etching processes.

[0078] Specifically, after forming a light-shielding layer on the substrate, the process further includes forming a buffer layer on the light-shielding layer. This buffer layer can be deposited using plasma-enhanced chemical vapor deposition (PECVD). The structure of the thin-film transistor corresponding to this step is as follows: Figure 3 As shown in (b) of the diagram.

[0079] S2, a doped layer is formed on the substrate; the structure of the thin-film transistor corresponding to this step is as follows: Figure 3 As shown in (b);

[0080] Specifically, amorphous silicon doped with phosphorus ions can be deposited by chemical vapor deposition, and then patterned doped layers can be formed by photolithography and etching processes. The angle of the cone formed after etching is less than 45 degrees, and the length of the cone is 0.5 micrometers to 2 micrometers.

[0081] S3, a channel layer is formed on the doped layer, and the channel layer is crystallized using a blue laser diode annealing process to allow ion diffusion to occur in the doped layer in a molten state, resulting in lightly doped and heavily doped portions; the structure of the thin-film transistor corresponding to this step is as follows. Figure 3 As shown in (c);

[0082] Specifically, amorphous silicon with low hydrogen content is deposited on the doped layer using chemical vapor deposition. The annealing temperature is set to 450°C to 600°C for 0.5 to 2 hours to remove hydrogen from the amorphous silicon, resulting in a hydrogen content of less than 0.5%. Then, a blue laser diode annealing process is used to crystallize the channel layer with a crystallization current of 700 mA to 1200 mA, allowing ion diffusion to occur in the molten state of the doped layer to obtain lightly doped and heavily doped portions. Finally, a patterned channel layer is formed by sequentially using photolithography and etching processes.

[0083] S4, Form a gate layer on the active layer; the structure of the thin-film transistor corresponding to this step is as follows. Figure 4 As shown in (a) in the middle;

[0084] Specifically, before the step of forming a gate layer on the active layer, the method further includes: forming a gate insulating layer on the active layer, which can be done by depositing the gate insulating layer using a plasma-enhanced chemical vapor deposition process, then depositing the gate layer using a physical vapor deposition process, and then sequentially forming a patterned gate layer using photolithography and etching processes.

[0085] S5, forming source and drain layers on the gate layer; the structure of the thin-film transistor corresponding to this step is as follows: Figure 1 As shown.

[0086] Specifically, before the step of forming the source and drain layers on the gate layer, the method further includes: forming an interlayer insulating layer on the gate layer, and creating openings in the channel layer, the gate insulating layer, and the interlayer insulating layer; the structure of the thin-film transistor corresponding to this step is as follows: Figure 4 As shown in (b) of the diagram.

[0087] Specifically, chemical vapor deposition can be used to form an interlayer insulating layer, and photolithography and etching processes can be used sequentially to form vias, ensuring that the doped layer is not etched through and the channel layer is etched through.

[0088] This application provides a method for fabricating a thin-film transistor. This method involves sequentially forming a doped layer and a channel layer. During the crystallization of the channel layer, due to the high crystallization temperature, the crystals within the doped layer are in a molten state, leading to ion diffusion. This allows for the direct formation of heavily doped and lightly doped portions without the need for ion implantation, reducing the number of process steps in electronic device fabrication and improving the fabrication efficiency of electronic devices.

[0089] Specifically, compared to current display devices that utilize temperature differences for ion activation, this application embodiment achieves ion diffusion by keeping the amorphous silicon in a molten state during crystallization (crystallization temperature greater than 1400 degrees Celsius), eliminating the need for ion implantation. This allows the thin-film transistor to form a lightly doped drain region structure, reducing leakage current and improving the performance of the thin-film transistor.

[0090] Meanwhile, this application provides an electronic device, which includes a thin-film transistor as described in any of the above embodiments.

[0091] Specifically, electronic devices include organic light-emitting diode display panels and liquid crystal display panels.

[0092] Specifically, such as Figure 5 As shown, the electronic device includes a thin-film transistor, a passivation layer 21, a pixel electrode layer 22, a pixel definition layer 23, a light-emitting material layer 24, a common electrode layer 25, and an encapsulation layer 26.

[0093] As can be seen from the above embodiments:

[0094] This application provides a thin-film transistor and its fabrication method, as well as an electronic device. The thin-film transistor includes a substrate, an active layer, a gate layer, and source / drain layers. The active layer is disposed on one side of the substrate and includes a doped layer and a channel layer. The channel layer is disposed on the doped layer. The gate layer is disposed on the side of the active layer away from the substrate, and the source / drain layers are disposed on the side of the gate layer away from the active layer. The doped layer includes lightly doped and heavily doped portions, which are arranged horizontally and intersecting each other. The source / drain layers are connected to the heavily doped portions. By setting the active layer as both the doped layer and the channel layer, during the crystallization of the channel layer, due to the high crystallization temperature, the crystals within the doped layer are in a molten state, leading to ion diffusion. This allows for the direct formation of both heavily doped and lightly doped portions without the need for ion implantation, reducing the process steps in electronic device fabrication and improving the fabrication efficiency.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0096] The foregoing has provided a detailed description of a thin-film transistor and its fabrication method, as well as an electronic device, according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin film transistor, characterized by comprising: The thin film transistor comprises: a substrate; an active layer arranged on one side of the substrate, the active layer comprising a doped layer and a channel layer, the channel layer being arranged on the doped layer; a gate layer arranged on a side of the active layer away from the substrate; a source-drain layer arranged on a side of the gate layer away from the active layer; wherein the doped layer comprises a lightly doped portion and a heavily doped portion, the lightly doped portion and the heavily doped portion are arranged to cross each other in a horizontal direction, the source-drain layer is connected to the heavily doped portion; the channel layer covers the doped layer; the thin film transistor adopts a laser annealing process to crystallize the channel layer, so that the doped layer undergoes ion diffusion in a molten state to obtain the lightly doped portion and the heavily doped portion.

2. The thin film transistor according to claim 1, wherein The channel layer comprises a channel portion, the lightly doped portion comprises a first lightly doped portion and a second lightly doped portion, the heavily doped portion comprises a first heavily doped portion and a second heavily doped portion, the first lightly doped portion is arranged between the first heavily doped portion and the channel portion, and the second heavily doped portion is arranged between the second lightly doped portion and the channel portion.

3. The thin film transistor according to claim 2, wherein The source-drain layer comprises a source and a drain, the source is connected to the second heavily doped portion, and the drain is connected to the first heavily doped portion.

4. The thin film transistor according to claim 2, wherein A projection of the gate layer on the substrate overlaps a projection of the first lightly doped portion on the substrate.

5. The thin film transistor according to claim 1, wherein The channel layer is provided with a via hole in a region corresponding to the heavily doped portion, the source-drain layer is connected to the heavily doped portion through the via hole, and a side surface of the source-drain layer is in contact with the channel layer.

6. The thin film transistor according to claim 1, wherein The thin film transistor further comprises a gate insulating layer and an interlayer insulating layer, the gate insulating layer is arranged between the gate layer and the active layer, the interlayer insulating layer is arranged between the gate layer and the source-drain layer, the interlayer insulating layer is in contact with the doped layer, and the source-drain layer is connected to the heavily doped portion through a via hole of the interlayer insulating layer.

7. The thin film transistor according to claim 1, wherein The material of the doped layer comprises amorphous silicon doped with ions, and the concentration of the doped ions of the lightly doped portion is less than the concentration of the doped ions of the heavily doped portion.

8. The thin film transistor according to claim 1, wherein The thickness of the doped layer ranges from 200 angstroms to 1000 angstroms.

9. A method of fabricating a thin film transistor, comprising: The thin film transistor preparation method comprises: providing a substrate; forming a doped layer on the substrate; forming a channel layer on the doped layer and crystallizing the channel layer by adopting a blue laser diode annealing process, so that the doped layer undergoes ion diffusion in a molten state to obtain a lightly doped portion and a heavily doped portion; forming a gate layer on the active layer; forming a source-drain layer on the gate layer.

10. An electronic device, characterized by The electronic device comprises the thin film transistor as claimed in any one of claims 1 to 8.

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