Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate including a resistance region; forming isolation structures in the substrate; forming an insulating layer in the substrate between the isolation structures of the resistance region, the insulating layer being formed by oxidizing the substrate; forming a resistance structure on the insulating layer; forming an interlayer dielectric layer on the substrate at the side of the resistance structure, the interlayer dielectric layer exposing a top of the resistance structure; removing part of the resistance structure at the interface between the resistance structure and the interlayer dielectric layer along the extension direction of the resistance structure to form an opening surrounded by the interlayer dielectric layer and the remaining resistance structure; forming an electrode in the opening; and forming a conductive plug electrically connected to the electrode on the top of the electrode. The area between the isolation structures is an active region, and the probability of over-polishing the active region during the planarization process of forming the isolation structures is low. Therefore, the insulating layer is formed in the active region, effectively reducing the probability of recess defects in the insulating layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Integrated circuits usually include active devices and passive devices. The active devices include MOS transistors, and the passive devices include resistors. The resistors are indispensable components in integrated circuit design, and in integrated circuit design, the resistors can be polysilicon resistors or metal resistors.

[0003] Among them, the semiconductor structure uses a polysilicon resistor structure. Non-doped polysilicon has a high resistivity, and at present, the resistivity of the polysilicon resistor structure is usually changed by ion doping. The doping ions can be N-type ions or P-type ions. In addition, at present, the polysilicon resistor is usually formed on an isolation structure. When a high potential is applied to the resistor structure, in order to avoid breakdown of the isolation structure, the isolation structure is usually thick. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate including a resistor region; an isolation structure in the substrate; an insulating layer in the substrate between the isolation structures of the resistor region, the insulating layer being formed by oxidizing the substrate; a resistor structure on the insulating layer; an interlayer dielectric layer on the substrate at the side of the resistor structure, the interlayer dielectric layer exposing the top of the resistor structure; an electrode along the extension direction of the resistor structure, the electrode being between the resistor structure and the interlayer dielectric layer, and the top of the electrode being flush with the top of the resistor structure; and a conductive plug on the top of the electrode and electrically connected to the electrode.

[0006] Correspondingly, embodiments of the present application also provide a forming method of a semiconductor structure, comprising: providing a substrate including a resistor region; forming an isolation structure in the substrate; forming an insulating layer in the substrate between the isolation structures of the resistor region, the insulating layer being formed by oxidizing the substrate; forming a resistor structure on the insulating layer; forming an interlayer dielectric layer on the substrate at the side of the resistor structure, the interlayer dielectric layer exposing the top of the resistor structure; removing part of the resistor structure at the junction of the resistor structure and the interlayer dielectric layer along the extension direction of the resistor structure, to form an opening surrounded by the interlayer dielectric layer and the remaining resistor structure; forming an electrode in the opening; and forming a conductive plug on the top of the electrode and electrically connected to the electrode.

[0007] Compared with the prior art, the technical scheme of the semiconductor structure provided by the embodiment of the present application has the following advantages:

[0008] In the semiconductor structure provided by the embodiment of the present application, the insulating layer is formed in the base between the isolation structures of the resistance region by oxidizing the base; in the process of forming the isolation structure, generally, the process includes forming an isolation material layer and then planarizing the isolation material layer, and if the size of the isolation structure is large, the top surface of the isolation structure is prone to serious concave defects; however, in the embodiment of the present application, the region between the isolation structures is an active area (AA), and the insulating layer and the resistance structure are located in the active area, so compared with the scheme in which the resistance structure is located on the isolation structure of the resistance region, in the process of forming the semiconductor structure provided by the embodiment of the present application, the probability of over-grinding the active area is low when the isolation material layer is planarized, thereby effectively reducing the probability of concave defects on the top surface of the base between the isolation structures of the resistance region in the planarization process, which correspondingly improves the flatness of the top surface of the resistance structure; the electrode is located between the resistance structure and the interlayer dielectric layer, and the top of the electrode is flush with the top of the resistance structure, which ensures the formation quality of the electrode, thereby improving the electrical connection reliability between the conductive plug and the electrode, and further improving the performance of the semiconductor structure.

[0009] The forming method of the semiconductor structure provided by the embodiment of the present application includes: forming an isolation structure in the substrate; forming an insulating layer in the substrate between the isolation structures of the resistance region by oxidizing the substrate; and forming a resistance structure on the insulating layer; wherein, in the process of forming the isolation structure, generally, the process includes forming an isolation material layer and then planarizing the isolation material layer, and when the isolation material layer is planarized, if the size of the isolation structure is large, the top surface of the isolation structure is prone to have serious concave defects; however, in the embodiment of the present application, the area between the isolation structures is an active area (AA), and the insulating layer and the resistance structure are formed in the active area, so compared with the scheme of forming the resistance structure directly on the isolation structure of the resistance region, the probability of over-grinding the active area in the process of planarizing the isolation material layer is low, and thus the probability of the top surface of the substrate between the isolation structures of the resistance region having concave defects in the planarization process is effectively reduced. This correspondingly improves the flatness of the top surface of the resistance structure, so that the whole top surface of the resistance structure can be exposed by the interlayer dielectric layer, so as to remove part of the resistance structure at the junction of the resistance structure and the interlayer dielectric layer, form a groove, and form an electrode in the groove, thereby improving the electrical connection reliability between the conductive plug and the electrode, and further improving the performance of the semiconductor structure.

[0010] In an optional solution, the method for forming the insulating layer includes: forming a first groove in the substrate between the isolation structures of the resistance region; and performing oxidation treatment on the substrate exposed by the first groove to form the insulating layer in the first groove. By forming the first groove, a relatively thick insulating layer can be formed, which not only ensures that the height of the resistance structure formed on the insulating layer can meet the process requirements, but also reduces the probability of the insulating layer being broken down when the resistance structure is subjected to a high voltage, thereby improving the performance of the semiconductor structure.

[0011] In an optional solution, the substrate further includes a device region, and in the step of forming the first groove in the substrate between the isolation structures of the resistance region, a second groove is also formed in the substrate between the isolation structures of the device region, and in the step of forming the insulating layer in the first groove, a gate oxide layer is also formed in the second groove; thus, in the embodiment of the present application, the gate oxide layer is formed simultaneously with the insulating layer in the process of forming the gate oxide layer, which has high process compatibility and can simplify the process steps and reduce the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1 to 5 FIG. 1 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0013] Figure 6is a structural schematic diagram of an embodiment of a semiconductor structure of the present application;

[0014] Figures 7 to 14 is a structural schematic diagram corresponding to each step in an embodiment of a forming method of a semiconductor structure of the present application. DETAILED DESCRIPTION

[0015] The performance of the semiconductor structure still needs to be improved. The reason why the performance of the semiconductor structure still needs to be improved is analyzed in combination with a forming method of a semiconductor structure.

[0016] Reference Figures 1 to 5 is shown a structural schematic diagram corresponding to each step in a forming method of a semiconductor structure.

[0017] Reference Figure 1 A substrate 10 is provided, and a first trench 20 and a second trench 23 are formed in the substrate 10, the line width size of the first trench 20 is greater than the line width size of the second trench 23.

[0018] Reference Figure 2 A deposition process is used to form a shallow trench isolation material layer 21 in the first trench 20 (as shown in Figure 1 ) and the second trench 23 (as shown in Figure 1 ), the shallow trench isolation material layer 21 covers the top of the substrate 10.

[0019] Reference Figure 3 A planarization process is performed on the shallow trench isolation material layer 21 (as shown in Figure 2 ), and a shallow trench isolation layer 22 is formed in the first trench 20 (as shown in Figure 1 ) and the second trench 23 (as shown in Figure 1 ).

[0020] Since the material hardness of the shallow trench isolation material layer 21 is low, and the line width size of the first trench 20 is large, after the planarization process, the top of the shallow trench isolation layer 22 in the first trench 20 is prone to sag.

[0021] Reference Figure 4 A resistance structure 30 is formed on the shallow trench isolation layer 22 in the first trench 20, and an interlayer dielectric layer 31 is formed on the substrate 10 at the side of the resistance structure 30, the interlayer dielectric layer 31 exposes the top of the resistance structure 30.

[0022] Specifically, in the actual process, a hard mask layer (not shown in the figure) is formed on the top of the resistance structure 30, and the hard mask layer is usually removed in the planarization process of forming the interlayer dielectric layer 31, and then part of the resistance structure 30 at the junction of the resistance structure 30 and the interlayer dielectric layer 31 is removed to form an opening, and then an electrode (not shown in the figure) is formed in the opening.

[0023] Because the top of the shallow trench isolation layer 22 in the first trench 20 is recessed, the top of the resistance structure 30 on the shallow trench isolation layer 22 is also recessed, so that in the planarization process of the interlayer dielectric layer 31, it is difficult to remove part of the hard mask layer at the junction of the resistance structure 30 and the interlayer dielectric layer 31, and under the blocking action of the hard mask layer, part of the resistance structure 30 at the junction of the resistance structure 30 and the interlayer dielectric layer 31 cannot be removed, further causing it difficult to form the electrode.

[0024] Reference Figure 5 The conductive plug 41 electrically connected to the electrode is formed on the top of the resistance structure 30.

[0025] Specifically, as shown by the dashed line in the figure, because the electrode cannot be formed at the junction of the resistance structure 30 and the interlayer dielectric layer 31, the conductive plug 41 cannot be electrically connected to the resistance structure 30.

[0026] In order to solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate comprising a resistance region; forming an isolation structure in the substrate; forming an insulating layer in the substrate between the isolation structures of the resistance region, the insulating layer being formed by oxidizing the substrate; forming a resistance structure on the insulating layer; forming an interlayer dielectric layer on the substrate at the side of the resistance structure, the interlayer dielectric layer exposing the top of the resistance structure; removing part of the resistance structure at the junction of the resistance structure and the interlayer dielectric layer along the extension direction of the resistance structure to form an opening surrounded by the interlayer dielectric layer and the remaining resistance structure; forming an electrode in the opening; and forming a conductive plug electrically connected to the electrode on the top of the electrode.

[0027] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming an isolation structure in a substrate; forming an insulating layer in the substrate between the isolation structures of a resistance region by oxidizing the substrate; and forming a resistance structure on the insulating layer.

[0028] In order to make the above objectives, characteristics and advantages of the embodiments of the present application more apparent, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0029] Reference Figure 6 Fig. 1 shows a structural schematic diagram of an embodiment of the semiconductor structure of the present application.

[0030] The semiconductor structure comprises: a substrate 101 comprising a resistance region 101R; an isolation structure 121 in the substrate 101; an insulating layer 221 in the substrate 101 between the isolation structures 121 of the resistance region 101R, the insulating layer 221 being formed by oxidizing the substrate 101; a resistance structure 301 on the insulating layer 221; an interlayer dielectric layer 311 on the substrate 101 at the side of the resistance structure 301, the interlayer dielectric layer 311 exposing the top of the resistance structure 301; an electrode 321 along the extension direction of the resistance structure 301, the electrode 321 being between the resistance structure 301 and the interlayer dielectric layer 311, and the top of the electrode 321 being flush with the top of the resistance structure 301; and a conductive plug 411 on the top of the electrode 321 and electrically connected to the electrode 321.

[0031] In the semiconductor structure provided by the embodiment, the insulating layer 221 is formed in the substrate 101 between the isolation structures 121 of the resistor region 101R by oxidizing the substrate 101; in the process of forming the isolation structures 121, generally, the process includes forming an isolation material layer and then planarizing the isolation material layer, and when the isolation material layer is planarized, if the size of the isolation structure 121 is large, the top surface of the isolation structure 121 is prone to have serious concave defects; in the embodiment, the region between the isolation structures 121 is an active region, and the insulating layer 221 and the resistor structure 301 are located in the active region, so compared with the scheme that the resistor structure 301 is located on the isolation structure 121 of the resistor region 101R, in the process of forming the semiconductor structure provided by the embodiment, when the isolation material layer is planarized, the probability of over-grinding the active region is low, so the probability of the top surface of the substrate 101 between the isolation structures 121 of the resistor region 101R having concave defects in the planarization process is effectively reduced, which correspondingly improves the flatness of the top surface of the resistor structure, wherein the electrode 321 is located between the resistor structure 301 and the interlayer dielectric layer 311, and the top of the electrode 321 is flush with the top of the resistor structure 301, which ensures the formation quality of the electrode 321, thereby improving the electrical connection reliability between the conductive plug 411 and the electrode 321, and further improving the performance of the semiconductor structure.

[0032] The substrate 101 provides a process operation basis for the forming process of the semiconductor structure.

[0033] In the embodiment, the material of the substrate 101 is silicon, and in other embodiments, the material of the substrate 101 can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate 101 can be a material suitable for process needs or easy to integrate.

[0034] In the embodiment, the substrate 101 includes a resistor region 101R and a device region 101H. The resistor region 101R is used to form a resistor structure, and the device region 101H is used to form a MOS transistor.

[0035] The isolation structure 121 is used to realize insulation between different devices, for example, in a CMOS manufacturing process, an isolation structure is usually formed between an NMOS transistor and a PMOS transistor. Specifically, the isolation structure 121 is a shallow trench isolation (STI) structure.

[0036] The material of the isolation structure 121 is insulating material. As an example, the material of the isolation structure 121 is silicon oxide.

[0037] The insulating layer 221 is located in the substrate 101 between the isolation structures 121 of the resistance region 101R, that is, the bottom of the insulating layer 221 is lower than the top of the substrate 101.

[0038] The insulating layer 221 is used to isolate the resistance structure 301 on the insulating layer 221 and the substrate 101, so as to prevent short circuit between the resistance structure 301 and the well region in the substrate 101.

[0039] The top of the insulating layer 221 cannot be too high or too low than the top of the substrate 101. If the top of the insulating layer 221 is too high than the top of the substrate 101, the top of the resistance structure 301 on the insulating layer 221 is also too high. Since the interlayer dielectric layer 311 on both sides of the resistance structure 301 is planarized, if the top of the resistance structure 301 is too high, the resistance structure 301 is easily damaged too much in the planarization process, which affects the resistance value of the resistance structure 301. If the insulating layer 221 is too low than the top of the substrate 101, the top of the resistance structure 301 on the insulating layer 221 is also too low. Since the top of the resistance structure 301 is usually formed with a hard mask layer before the interlayer dielectric layer 311 is formed, it is difficult to remove the hard mask layer on the top of the resistance structure 301 after the interlayer dielectric layer 311 is planarized, so that it is difficult to expose the top of the resistance structure 301, which leads to difficulty in etching the resistance structure 301 and providing a space position for the formation of the electrode 321, and further leads to difficulty in forming an effective electrode 321.

[0040] In this embodiment, the top of the insulating layer 221 is flush with the top of the substrate 101.

[0041] The insulating layer 221 is formed by oxidation process, so that the density of the insulating layer 221 is high, thereby the insulating layer 221 can have good insulating effect and reduce the probability of breakdown of the insulating layer 221 when the resistance structure 301 is applied with high voltage. In addition, in the process of forming the insulating layer 221, no planarization process is needed, and the probability of concave problem on the top surface of the insulating layer 221 is also low.

[0042] The material of the insulating layer 221 includes one or both of SiO2 and SiON. The insulating layer 221 is formed by oxidation process, so that it is easy to obtain the insulating layer 221 with the material of SiO2 and SiON.

[0043] In the embodiment, the insulating layer 221 is made of SiO2. The insulating layer 221 is made of SiO2, so that the oxidation process can be used, and the SiO2 can provide good insulation effect.

[0044] The substrate 101 includes a device region 101H, which is used to form a MOS transistor.

[0045] In the embodiment, the device region 101H is a high-voltage (HV) device region, which is used to form a high-voltage device. As an example, the working voltage of the high-voltage device is greater than 10V.

[0046] It should be noted that the substrate 101 can also include a low-voltage device region (not shown in the figure) used to form a low-voltage device. The working voltage of the low-voltage device is less than that of the high-voltage device. As an example, the working voltage of the low-voltage device is less than 2V.

[0047] In the embodiment, the semiconductor structure further includes a gate oxide layer 231 in the substrate 101 between the isolation structures 121 of the device region 101H.

[0048] The device region 101H is used to form a MOS transistor, and the gate oxide layer 231 is used as a gate dielectric layer of the MOS transistor formed in the device region 101H.

[0049] In the embodiment, the gate oxide layer 231 and the insulating layer 221 are made of the same material, have the same thickness, and have the same top. That is, the gate oxide layer 231 and the insulating layer 221 are formed in the same step in the process of forming the semiconductor structure, so that the process steps of forming the semiconductor structure are simplified, and the process cost is reduced. Accordingly, the insulating layer 221 is formed by oxidizing the substrate 101, so that the process of forming the insulating layer 221 is compatible with the process of forming the gate oxide layer 231. The working voltage of the high-voltage device is relatively high, so the thickness of the gate oxide layer 231 is usually large, so that the thickness requirement of the insulating layer 221 is easily met, and the probability of the insulating layer 221 being broken when the resistance structure 301 is at a high potential is low.

[0050] Correspondingly, the material of the gate oxide layer 231 includes SiO2 and SiON.

[0051] The thickness of the insulating layer 221 cannot be too large or too small. If the thickness of the insulating layer 221 is too large, the top of the resistance structure 301 on the insulating layer 221 is too high. Since the interlayer dielectric layer 311 on both sides of the resistance structure 301 is planarized during formation, if the top of the resistance structure 301 is too high, the resistance structure 301 is easily damaged during planarization, affecting the resistance of the resistance structure 301. If the thickness of the insulating layer 221 is too small, when the resistance structure 301 is subjected to a high potential, the probability of the insulating layer 221 being broken down is increased, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the insulating layer 221 is 80 nm to 110 nm. For example, the thickness of the insulating layer 221 is 100 nm.

[0052] The resistance structure 301 is used as a passive device in an integrated circuit.

[0053] In this embodiment, the material of the resistance structure 301 includes polysilicon. It should be noted that undoped polysilicon has a high resistivity, and therefore, the resistance structure 301 usually also has doping ions to change the resistivity of the polysilicon. The doping ions can be N-type ions or P-type ions.

[0054] The interlayer dielectric layer 311 is used to isolate adjacent devices.

[0055] In this embodiment, the material of the interlayer dielectric layer 311 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0056] Along the extension direction of the resistance structure 301, the electrode 321 is located between the resistance structure and the interlayer dielectric layer 311, that is, the electrode 321 is connected to the end of the resistance structure 301.

[0057] The electrode 321 is used to electrically connect with a conductive plug, thereby realizing electrical connection of the resistance structure 301 with other circuits.

[0058] The electrode 321 is located at the end of the resistance structure 301. Since the longer the resistance structure 301 is, the greater the resistance of the resistance structure 301 is, by locating the electrode 321 at the end of the resistance structure 301, the length of the resistance structure 301 can be maximized, so that the resistance structure 301 obtains a greater resistance.

[0059] In this embodiment, the electrode 321 comprises a metal gate structure. The metal gate structure has good conductivity, and using the metal gate structure as the electrode 321 helps to improve the electrical performance of the semiconductor structure.

[0060] In this embodiment, the electrode 321 has the same material and stack structure as the metal gate structure in the MOS transistor, so that the electrode 321 and the metal gate structure in the MOS transistor can be formed in the same process. For example, the device gate structure used in the low-voltage device region is a metal gate structure, and using the metal gate structure helps to improve the electrical performance of the MOS transistor and reduce the leakage current.

[0061] Correspondingly, in the process of forming the semiconductor structure, the electrode 321 is formed simultaneously in the step of forming the metal gate structure.

[0062] In this embodiment, the metal gate structure is formed by using a high-k first metal gate last process, so the metal gate structure comprises a work function layer (not shown in the figure) and a gate electrode layer (not shown in the figure) on the work function layer.

[0063] The work function layer is used to adjust the threshold voltage of the MOS transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0064] The gate electrode layer is used to lead out the electrical property of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In other embodiments, the metal gate structure can further comprise a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0065] In this embodiment, the semiconductor structure further comprises a covering dielectric layer 401 covering the interlayer dielectric layer 311, the resistance structure 301 and the electrode 321.

[0066] The covering dielectric layer 401 is used to provide a process platform for forming the conductive plug 411.

[0067] The material of the covering dielectric layer 401 includes silicon oxide, low dielectric constant material (low dielectric constant material refers to dielectric material with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or ultra low dielectric constant material (ultra low dielectric constant material refers to dielectric material with relative dielectric constant less than 2.6).

[0068] In this embodiment, the conductive plug 411 penetrates the covering dielectric layer 401 on the top of the electrode 321 and electrically connects the electrode 321.

[0069] The conductive plug 411 is used to realize the electrical connection of the electrode 321.

[0070] In this embodiment, the material of the conductive plug 411 includes tungsten, ruthenium or cobalt.

[0071] In this embodiment, the substrate 101 further includes a device region 101H for forming a MOS transistor, wherein the MOS transistor serves as an active device in the integrated circuit.

[0072] Therefore, in this embodiment, the semiconductor structure can further include a device gate structure (not shown) on the substrate 101 in the device region 101H.

[0073] In this embodiment, the device region 101H is a high-voltage device region, and therefore the device gate structure in the device region 101H is a polysilicon gate structure, i.e., the device gate structure in the device region 101H has the same material and thickness as the resistive structure 301.

[0074] Correspondingly, in this embodiment, the interlayer dielectric layer 311 is also on the substrate 101 at the side of the device gate structure and covers the sidewall of the device gate structure.

[0075] In this embodiment, the covering dielectric layer 401 also correspondingly covers the device gate structure.

[0076] Figures 7 to 14 is a structure schematic diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present application.

[0077] Referring to Figure 7 , a substrate 100 is provided, including a resistive region 100R.

[0078] The substrate 100 provides a process operation basis for subsequent processes.

[0079] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate 100 can also be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium arsenide. The substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 can be a material that is suitable for a process need or is easy to integrate.

[0080] In this embodiment, the substrate 100 includes a resistive region 100R for forming a resistive structure.

[0081] In this embodiment, the substrate 100 also includes a device region 100H for forming a MOS transistor. The MOS transistor is an active device in an integrated circuit.

[0082] In this embodiment, the device region 100H is a high-voltage device region for forming a high-voltage device. As an example, the high-voltage device has an operating voltage greater than 10V.

[0083] It is noted that the substrate 100 can also include a low-voltage device region (not shown) for forming a low-voltage device. The low-voltage device has an operating voltage less than the operating voltage of the high-voltage device. As an example, the low-voltage device has an operating voltage less than 2V.

[0084] Continuing to refer to FIG. 1, an isolation structure 120 is formed in the substrate 100. Figure 7

[0085] The isolation structure 120 is used to isolate different devices. For example, in a CMOS manufacturing process, an isolation structure is typically formed between an NMOS transistor and a PMOS transistor. Specifically, the isolation structure 120 is a shallow trench isolation (STI) structure.

[0086] The isolation structure 120 is made of an insulating material. As an example, the isolation structure 120 is made of silicon oxide.

[0087] ​In the process of forming the isolation structure 120, generally includes forming an isolation material layer, and then planarizing the isolation material layer. If the size of the isolation structure 120 is large, the top surface of the isolation structure 120 is prone to serious concave defects. In the embodiment, since the area between the isolation structures 120 is the active region, the probability of over-grinding the active region is low in the process of planarizing the isolation material layer, thereby effectively reducing the probability of concave defects on the top surface of the substrate 100 between the isolation structures 120 of the resistance region 100R in the planarization process. Subsequently, an insulating layer 220 is formed in the substrate 100 between the isolation structures 120 of the resistance region 100R. The insulating layer 220 is formed by oxidizing the substrate 100. Then, a resistance structure 300 is formed on the insulating layer 220. Subsequently, an interlayer dielectric layer 310 is formed on the substrate 100 at the side of the resistance structure 300, and the interlayer dielectric layer 310 exposes the top of the resistance structure 300. Therefore, compared with the scheme of directly forming a resistance structure on the isolation structure of the resistance region, the embodiment is beneficial to improve the flatness of the top surface of the resistance structure 300, so that the entire top surface of the resistance structure 300 can be exposed by the interlayer dielectric layer 310, so as to remove part of the resistance structure 300 at the junction of the resistance structure 300 and the interlayer dielectric layer 310, form a groove, and form an electrode in the groove, thereby improving the electrical connection reliability between the conductive plug and the electrode, and further improving the performance of the semiconductor structure.

[0088] In the step of providing the substrate 100, a hard mask material layer (not shown) is also formed on the substrate 100. The hard mask material layer is used to form a hard mask layer. The material of the hard mask material layer includes silicon nitride.

[0089] Therefore, in the embodiment, the step of forming the isolation structure 120 includes: etching the hard mask material layer to form a patterned hard mask layer 110; etching a part of the thickness of the substrate 100 to form a groove (not shown) in the substrate 100, with the hard mask layer 110 as a mask; forming an isolation material layer (not shown) in the groove, the isolation material layer covering the top of the hard mask layer 110; and planarizing the isolation material layer to form the isolation structure 120 in the groove.

[0090] The groove is formed to provide a spatial position for subsequent formation of the isolation structure 120.

[0091] The isolation material layer is used to form the isolation structure 120.

[0092] The isolation material layer is planarized to improve the flatness of the top of the substrate 100 and the top of the isolation structure 120. In this embodiment, a chemical mechanical polishing process is used to planarize the isolation material layer.

[0093] It should be noted that the material of the hard mask layer 110 is relatively hard, so that the hard mask layer 110 is less likely to be damaged during the planarization of the isolation material layer, and the top surface of the hard mask layer 110 is less likely to be recessed. The hard mask layer 110 can protect the top surface of the substrate 100 between the isolation structures 120, which is conducive to improving the flatness of the top surface of the substrate 100 between the isolation structures 120.

[0094] In this embodiment, after the isolation structure 120 is formed, the hard mask layer 110 is removed.

[0095] The hard mask layer 110 is removed to expose the surface of the substrate 100, thereby preparing for the subsequent formation of an insulating layer and a gate oxide layer.

[0096] In combination with reference to Figure 8 and Figure 9 An insulating layer 220 is formed in the substrate 100 between the isolation structures 120 of the resistor region 100R. The insulating layer 220 is formed by oxidizing the substrate 100.

[0097] The insulating layer 220 is used to isolate the resistor structure formed on the insulating layer 220 from the substrate 100, so as to prevent short circuit between the resistor structure and the well region in the substrate 100.

[0098] As described above, the flatness of the surface of the substrate 100 between the isolation structures 120 in the resistor region 100R is high, which makes the top surface of the insulating layer 220 also have high flatness. Moreover, the insulating layer 220 is formed by oxidizing the substrate 100, so that the top surface of the insulating layer 220 is guaranteed to have high flatness without planarization during the formation of the insulating layer 220.

[0099] Specifically, referring to Figure 8 The method for forming the insulating layer 220 includes forming a first groove 200 in the substrate 100 between the isolation structures 120 of the resistor region 100R.

[0100] The first groove 200 is used to provide a spatial position for a subsequent insulating layer. By forming the first groove 200, a thicker insulating layer 220 can be formed, which not only ensures that the height of a resistance structure formed on the insulating layer 220 can meet the process requirements, but also reduces the probability that the insulating layer 220 is broken down when the resistance structure is applied with a high potential, thereby improving the performance of the semiconductor structure.

[0101] In this embodiment, a dry etching process is used to etch the substrate 100 of the resistance region 100R to form the first groove 200.

[0102] The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce the damage to the remaining substrate 100 at the bottom of the first groove 200. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and size accuracy of the first groove 200.

[0103] The depth of the first groove 200 cannot be too large or too small. If the depth of the first groove 200 is too large, then after the insulating layer 220 is formed in the first groove 200, when the thickness of the insulating layer 220 reaches the target thickness, there is a risk that the groove 200 cannot be filled, that is, the insulating layer 220 is lower than the top of the substrate 100, and then the top of the resistance structure formed on the insulating layer 220 is too low. The top of the resistance structure is usually formed with a hard mask layer, and then the interlayer dielectric layer is planarized on both sides of the resistance structure. The hard mask layer needs to be removed during the planarization process. If the top of the resistance structure on the insulating layer is too low, it is difficult to remove the hard mask layer on the top of the resistance structure during the planarization process, which increases the difficulty of subsequent process. If the depth of the groove 200 is too small, since the insulating layer 220 formed in the groove 200 is formed by an oxidation process, the oxidation process grows downward and upward from the bottom of the groove 200. When the depth of the groove 200 is too small, the insulating layer 220 grown by the oxidation process may protrude too much from the top of the substrate 100. Then the top of the resistance structure formed on the insulating layer 220 is too high. Since the interlayer dielectric layer is planarized when the interlayer dielectric layer is formed on both sides of the resistance structure, if the top of the resistance structure is too high, it is easy to cause excessive damage to the resistance structure during the planarization process, which affects the resistance value of the resistance structure. Therefore, in this embodiment, the depth of the groove 200 is 30nm to 60nm. For example, the depth of the groove 200 is 45nm.

[0104] In the embodiment, the second recess 210 is formed in the substrate 100 between the isolation structures 120 of the device region 101H in the step of forming the first recess 200 in the substrate 100 between the isolation structures 120 of the resistor region 101R.

[0105] The second recess 210 is used to provide a space position for forming a gate oxide layer.

[0106] In the embodiment, the first recess 200 and the second recess 210 are formed in the same step, which simplifies the process flow and saves the process cost.

[0107] With reference to Figure 9 The method of forming the insulating layer 220 further includes: performing an oxidation treatment on the exposed substrate 100 of the first recess 200 to form the insulating layer 220 in the first recess 200.

[0108] By performing the oxidation treatment on the exposed substrate 100 of the first recess 200, the insulating layer 220 is formed in the first recess 200, and no planarization treatment is needed to be performed on the insulating layer 220, so the probability of the top surface of the insulating layer 220 being recessed is also low.

[0109] The top of the insulating layer 220 cannot be higher than the top of the substrate 100, nor can it be lower than the top of the substrate 100. If the top of the insulating layer 220 is higher than the top of the substrate 100, the top of the resistor structure 300 located on the insulating layer 220 is also high. Since the interlayer dielectric layer 310 is formed on both sides of the resistor structure 300, the interlayer dielectric layer 310 is planarized, so if the top of the resistor structure 300 is too high, the resistor structure 300 is easily damaged during the planarization process, which affects the resistance value of the resistor structure 300. If the insulating layer 220 is lower than the top of the substrate 100, the top of the resistor structure 300 located on the insulating layer 220 is also low. Since a hard mask layer is usually formed on the top of the resistor structure 300 before the interlayer dielectric layer 310 is formed, it is difficult to remove the hard mask layer on the top of the resistor structure 300 after the interlayer dielectric layer 310 is planarized, so it is difficult to expose the top of the resistor structure 300, which makes it difficult to etch the resistor structure 300 and provide a space position for forming the electrode 320, and further makes it difficult to form an effective electrode 320.

[0110] In the embodiment, the top of the insulating layer 220 is flush with the top of the substrate 100 in the step of forming the insulating layer 220 in the first recess 200.

[0111] In the embodiment, the oxidation process includes a furnace tube oxidation process. The furnace tube oxidation process can form the insulation layer 220 with uniform thickness and high density, and can make the top corner of the groove 200 arc-shaped, so that the electric field density at the top corner is stepwise uniform, thereby reducing the leakage current of the semiconductor structure in operation and improving the performance of the semiconductor structure.

[0112] In the embodiment, the furnace tube oxidation process uses oxygen, silane or hydrogen as the gas, and the process temperature is 800-1000℃.

[0113] The material of the insulation layer 220 includes one or both of SiO2 and SiON. The insulation layer 220 is formed by the oxidation process, so it is easy to obtain the insulation layer 220 with the material of SiO2 and SiON.

[0114] In the embodiment, the material of the insulation layer 220 is SiO2. The insulation layer 220 is formed by the oxidation process, and the insulation layer 220 uses the material of SiO2, which is easy to use the oxidation process and can achieve good insulation effect.

[0115] In the embodiment, in the step of forming the insulation layer 220 in the first groove 200, a gate oxide layer 230 is also formed in the second groove 210. The gate oxide layer 230 is used as the gate dielectric layer of the MOS transistor formed in the device region 100H.

[0116] In the embodiment, the gate oxide layer 230 and the insulation layer 220 are formed in the same step, and the process of forming the insulation layer 220 is compatible with the process of forming the gate oxide layer 230, thereby simplifying the process steps of forming the semiconductor structure and reducing the process cost. Therefore, the gate oxide layer 230 and the insulation layer 220 have the same material and equal thickness. The working voltage of the high-voltage device is high, so the thickness of the gate oxide layer 230 is usually large, thereby easily meeting the thickness requirement of the insulation layer 220, and the probability of the insulation layer 220 being broken down when the resistance structure is at high voltage is low.

[0117] Correspondingly, the material of the gate oxide layer 230 includes SiO2 and SiON.

[0118] The thickness of the insulating layer 220 cannot be too large or too small. If the thickness of the insulating layer 220 is too large, the top of the resistance structure formed subsequently on the insulating layer 220 is too high, and since the interlayer dielectric layer is planarized at the two sides of the resistance structure, if the top of the resistance structure is too high, the resistance structure is easily damaged too much in the planarization process, affecting the resistance value of the resistance structure. If the thickness of the insulating layer 220 is too small, when the resistance structure is subjected to a high potential, the probability of breakdown of the insulating layer 220 is increased, affecting the performance of the semiconductor structure. Therefore, in the embodiment, the thickness of the insulating layer 220 is 80 nm to 110 nm. For example, the thickness of the insulating layer 220 is 100 nm.

[0119] Reference Figure 10 The resistance structure 300 is formed on the insulating layer 220.

[0120] The resistance structure 300 serves as a passive device in an integrated circuit.

[0121] In the embodiment, the method for forming the resistance structure 300 includes: forming a resistance structure material layer (not labeled) covering the substrate 100 and the insulating layer 220; forming a hard mask layer (not labeled) on the resistance structure material layer, the hard mask layer being located above the insulating layer 220; and performing a patterning process on the resistance structure material layer with the hard mask layer as a mask to form the resistance structure 300 on the insulating layer 220.

[0122] The patterning process is used to remove the resistance structure material layer located on the substrate 100, and the process is simple and convenient, and the resistance structure 300 formed does not contact the substrate 100, so that the resistance structure 300 does not short-circuit with the substrate 100.

[0123] In the embodiment, the resistance structure material layer is formed by a deposition process, and the resistance structure material layer covers the insulating layer 220. Therefore, in the embodiment, the top surface morphology of the resistance structure 300 is affected by the top surface morphology of the insulating layer 220.

[0124] Specifically, the deposition process is a chemical vapor deposition process.

[0125] In the embodiment, the material of the resistance structure 300 includes polysilicon. It should be noted that undoped polysilicon has a high resistivity. Therefore, the forming method can further include: performing ion doping on the resistance structure 300 to change the resistivity of the polysilicon. The doped ions can be N-type ions or P-type ions.

[0126] The hard mask layer serves as a mask for patterning the resistive structure material layer. As an example, the material of the hard mask layer is silicon nitride.

[0127] In this embodiment, the forming method further comprises: forming a gate structure 340 on the substrate 100 of the device region 100H.

[0128] Specifically, the gate structure 340 is located on the gate oxide layer 230 of the device region 100H.

[0129] The gate structure 340 is used to control the opening or closing of the channel of the transistor.

[0130] In this embodiment, the device region 100H is a high-voltage device region, and therefore the gate structure 340 of the device region 100H is a polysilicon gate structure.

[0131] In this embodiment, the gate structure 340 and the resistive structure 300 are formed in the same step, thereby simplifying the process steps of forming the semiconductor structure. Therefore, the material of the gate structure 340 is the same as that of the resistive structure 300.

[0132] Reference Figure 11 An interlayer dielectric layer 310 is formed on the substrate 100 at the side of the resistive structure 300, and the interlayer dielectric layer 310 exposes the top of the resistive structure 300.

[0133] The interlayer dielectric layer 310 is used to isolate adjacent devices.

[0134] Specifically, the step of forming the interlayer dielectric layer 310 comprises: forming an interlayer dielectric material layer (not shown in the figure) on the substrate 100, and performing a planarization process on the interlayer dielectric material layer to form the interlayer dielectric layer 310.

[0135] In this embodiment, the interlayer dielectric material layer is formed by a chemical vapor deposition process.

[0136] In this embodiment, the material of the interlayer dielectric layer 310 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0137] In this embodiment, a hard mask layer is formed on the top of the resistive structure 300, and therefore the hard mask layer is also removed in the planarization process of forming the interlayer dielectric layer 310, thereby exposing the top of the resistive structure 300 to facilitate the subsequent formation of an electrode in the resistive structure 300.

[0138] Correspondingly, in the embodiment, the interlayer dielectric layer 310 is also located on the substrate 100 at the side of the gate structure 340 and covers the sidewall of the gate structure 310.

[0139] Referring to Figure 12 , along the extending direction of the resistance structure 300, part of the resistance structure 300 at the junction of the resistance structure 300 and the interlayer dielectric layer 310 is removed, forming an opening 330 surrounded by the interlayer dielectric layer 310 and the remaining resistance structure 300.

[0140] The opening 330 is used to provide a spatial position for the subsequent formation of an electrode.

[0141] In the embodiment, the opening 330 is formed by using a dry etching process.

[0142] In the embodiment, the bottom of the opening 330 exposes the insulating layer 220.

[0143] It should be noted that, in order to increase the process window of the photolithography process, part of the interlayer dielectric layer 310 at the junction of the resistance structure 300 and the interlayer dielectric layer 310 can also be removed in the process of forming the opening 330.

[0144] Referring to Figure 13 , an electrode 320 is formed in the opening 330 (as shown in Figure 12 ).

[0145] In the embodiment, along the extending direction of the resistance structure 300, the electrode 320 is located between the resistance structure and the interlayer dielectric layer 310, that is, the electrode 320 is connected to the end of the resistance structure 300.

[0146] The electrode 320 is located at the end of the resistance structure 300. Since the longer the length of the resistance structure 300 is, the greater the resistance of the resistance structure 300 is, and the electrode 320 is located at the end of the resistance structure 300, the length of the resistance structure 300 can be maximized, so that the resistance structure 300 obtains a larger resistance.

[0147] The electrode 320 is used to realize electrical connection with a conductive plug, so as to realize electrical connection between the resistance structure 300 and other circuits.

[0148] In the embodiment, the electrode 320 includes a metal gate structure. The metal gate structure has good conductivity, and using the metal gate structure as the electrode 320 is conducive to reducing the contact resistance between the conductive plug and the electrode 320, thereby improving the electrical performance of the semiconductor structure.

[0149] In this embodiment, the electrode 320 has the same material and stack structure as the metal gate structure in the MOS transistor, so that the electrode 320 and the metal gate structure in the MOS transistor can be formed in the same process. For example, the device gate structure in the low-voltage device region is a metal gate structure, which is beneficial to improve the electrical performance of the MOS transistor and reduce the leakage current.

[0150] Correspondingly, in this embodiment, the electrode 320 is formed at the same time in the step of forming the metal gate structure of the MOS transistor, so that the process steps of forming the semiconductor structure are simplified.

[0151] In this embodiment, the metal gate structure is formed by using a high-k first metal gate last process, so that the metal gate structure includes a work function layer (not shown in the figure) on the high-k gate dielectric layer and a gate electrode layer (not shown in the figure) on the work function layer.

[0152] The work function layer is used to adjust the threshold voltage of the MOS transistor. When the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0153] The gate electrode layer is used to lead out the electrical property of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In other embodiments, the metal gate structure can further include a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0154] Reference Figure 14 A conductive plug 410 electrically connected to the electrode 320 is formed on top of the electrode 320.

[0155] The conductive plug 410 is used to realize the electrical connection of the electrode 320.

[0156] In this embodiment, the material of the conductive plug 410 includes tungsten, ruthenium or cobalt.

[0157] In this embodiment, before forming the conductive plug 410, further comprising forming a covering dielectric layer 400 covering the ILD layer 310, the resistive structure 300 and the electrode 320.

[0158] The covering dielectric layer 400 is used to provide a process platform for forming the conductive plug 410.

[0159] The material of the covering dielectric layer 400 includes silicon oxide, low-k material (low-k material refers to dielectric material with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or ultra low-k material (ultra low-k material refers to dielectric material with relative dielectric constant less than 2.6).

[0160] In this embodiment, the covering dielectric layer 400 also covers the gate structure 340.

[0161] In this embodiment, the step of forming the conductive plug 410 electrically connecting the electrode 320 on the top of the electrode 320 includes: forming a conductive hole (not shown) through the top of the electrode 320 and exposing the electrode 320; and forming the conductive plug 410 in the conductive hole.

[0162] The conductive plug 410 penetrates the covering dielectric layer 400 on the top of the electrode 320, thereby electrically connecting the electrode 320.

[0163] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a resistor region; isolation structures in the substrate, the region between the isolation structures being an active region; an insulating layer in the substrate between the isolation structures of the resistor region and the active region, the insulating layer being formed by oxidizing the substrate; a resistor structure on the insulating layer; an interlayer dielectric layer on the substrate at the side of the resistor structure, the interlayer dielectric layer exposing the top of the resistor structure; an electrode along the extension direction of the resistor structure, the electrode being between the resistor structure and the interlayer dielectric layer, and the top of the electrode being flush with the top of the resistor structure; a conductive plug on the top of the electrode and electrically connected to the electrode.

2. The semiconductor structure of claim 1, wherein, The top of the insulating layer is flush with the top of the substrate.

3. The semiconductor structure of claim 1, wherein, The substrate further comprises a device region. The semiconductor structure further comprises a gate oxide layer in the substrate between the isolation structures of the device region. The gate oxide layer and the insulating layer are of the same material, have the same thickness, and have flush tops.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a cover dielectric layer covering the interlayer dielectric layer, the resistor structure, and the electrode. The conductive plug penetrates the cover dielectric layer on the top of the electrode and is electrically connected to the electrode.

5. The semiconductor structure of claim 1, wherein, The material of the insulating layer comprises one or both of SiO2 and SiON.

6. The semiconductor structure of claim 1, wherein, The thickness of the insulating layer is 80-110 nm.

7. The semiconductor structure of claim 1, wherein, The material of the resistor structure comprises polysilicon.

8. The semiconductor structure of claim 1, wherein, The electrode comprises a metal gate structure.

9. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: providing a substrate comprising a resistor region; forming isolation structures in the substrate, the region between the isolation structures being an active region; forming an insulating layer in the substrate between the isolation structures of the resistor region and the active region, the insulating layer being formed by oxidizing the substrate; forming a resistor structure on the insulating layer; forming an interlayer dielectric layer on the substrate at the side of the resistor structure, the interlayer dielectric layer exposing the top of the resistor structure; removing part of the resistor structure at the interface between the resistor structure and the interlayer dielectric layer along the extension direction of the resistor structure, forming an opening surrounded by the interlayer dielectric layer and the remaining resistor structure; forming an electrode in the opening; forming a conductive plug on the top of the electrode and electrically connected to the electrode.

10. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, a hard mask material layer is also formed on the substrate. The step of forming the isolation structures comprises: etching the hard mask material layer to form a patterned hard mask layer; etching a portion of the thickness of the substrate to form a trench in the substrate using the hard mask layer as a mask; forming an isolation material layer in the trench, the isolation material layer covering the top of the hard mask layer; planarizing the isolation material layer to form the isolation structures in the trench; after forming the isolation structures, before forming the insulating layer on the substrate between the isolation structures of the resistor region, further comprising removing the hard mask layer.

11. The method of forming a semiconductor structure of claim 9, wherein, The method of forming the insulating layer comprises forming a first recess in the substrate between the isolation structures of the resistor region; The substrate exposed by the first recess is subjected to an oxidation process to form an insulating layer in the first recess.

12. The method of forming a semiconductor structure of claim 11, wherein, The substrate further comprises a device region; In the step of forming a first recess in the substrate between the isolation structures of the resistance region, a second recess is also formed in the substrate between the isolation structures of the device region; In the step of forming the insulating layer in the first recess, a gate oxide layer is also formed in the second recess.

13. The method of forming a semiconductor structure of claim 11, wherein, In the step of forming the insulating layer in the first recess, the top of the insulating layer is flush with the top of the substrate.

14. The method of forming a semiconductor structure of claim 9, wherein, The method of forming the resistance structure comprises: forming a layer of resistance structure material covering the substrate and the insulating layer; The resistance structure material layer is subjected to a patterning process to form the resistance structure on the insulating layer.

15. The method of forming a semiconductor structure of claim 9, wherein, The oxidation process comprises a furnace tube oxidation process.

16. The method of forming a semiconductor structure of claim 9, wherein, Before forming the conductive plug, a cover medium layer is further formed covering the interlayer dielectric layer, the resistance structure and the electrode. The step of forming the conductive plug electrically connected to the electrode on the top of the electrode comprises: forming the conductive plug through the cover medium layer on the top of the electrode.

17. The method of forming a semiconductor structure of claim 9, wherein, The material of the insulating layer comprises one or both of SiO2 and SiON.

18. The method of forming a semiconductor structure of claim 11, wherein, A dry etching process is used to etch the substrate of the resistance region to form the first recess.

19. The method of forming a semiconductor structure of claim 11, wherein, The depth of the first recess is 30-60 nm.

20. The method of forming a semiconductor structure of claim 9, wherein, The material of the resistance structure comprises polysilicon.

21. The method of forming a semiconductor structure of claim 9, wherein, The electrode comprises a metal gate structure.

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