A manufacturing process for a fully dielectrically isolated silicon magnetically sensitive triode

Abstract

The present invention discloses a fully dielectrically isolated silicon magnetically sensitive triode and a manufacturing process thereof. The fully dielectrically isolated silicon magnetically sensitive triode comprises an SOI silicon magnetically sensitive triode and a dielectric isolation ring. The SOI silicon magnetically sensitive triode comprises a device silicon (1), a substrate silicon (2) and a buried silicon dioxide (3). The silicon magnetically sensitive triode is arranged on the device silicon (1), and the dielectric isolation ring and the buried silicon dioxide (3) form a fully dielectrically isolated structure. The fully dielectrically isolated silicon magnetically sensitive triode disclosed by the present invention is wrapped by a dielectric layer, effectively achieving isolation between components, while limiting the degree of carrier deflection under the action of a magnetic field, and improving the magnetic sensitivity and temperature characteristics of the silicon magnetically sensitive triode. In addition, the present invention also discloses a silicon magnetically sensitive triode prepared by integrating micro-electromechanical system technology and SOI technology, achieving miniaturization and integration, and laying a foundation for the mass production of high-performance silicon magnetically sensitive triodes.

Description

Technical Field

[0001] The present invention relates to the field of sensor technology, in particular to a magnetic field sensor, and more particularly to a manufacturing process of a silicon magnetic sensitive triode with a full dielectric isolation structure. Background Art

[0002] Silicon magnetic sensitive transistor is a bipolar semiconductor transistor that has a magnetic sensitive effect to an external magnetic field. Its magnetic sensitivity characteristics are the result of the dual effects of carrier injection effect and Lorentz force. Therefore, the degree of carrier deflection in the magnetic field has a great influence on the magnetic sensitivity, cross interference and other characteristics of the silicon magnetic sensitive transistor.

[0003] Theoretical analysis shows that silicon magnetic-sensitive transistors with a three-dimensional structure have good magnetic sensitivity characteristics. The alloy method can realize the three-dimensional structure of germanium magnetic-sensitive transistors. However, the structure size of silicon magnetic-sensitive transistors is small, and only planar structures can be produced through microelectronic processes. With the development of microelectromechanical systems (MEMS) technology, breakthroughs have been made in key process technologies, and the three-dimensional structure of silicon magnetic-sensitive transistors has been realized. However, the three-dimensional silicon magnetic-sensitive transistors have parasitic effects and other phenomena, which seriously affect the magnetic sensitivity and temperature characteristics. Effectively limiting the deflection of carriers under the action of the magnetic field and reducing parasitic effects can improve their performance. In summary, the three-dimensional silicon magnetic-sensitive transistor needs to consider component isolation. The integration of MEMS technology and isolation process can limit the degree of carrier deflection in the three-dimensional silicon magnetic-sensitive transistor under the magnetic field.

[0004] Isolation in bipolar integrated circuits includes PN junction isolation, dielectric isolation, and PN junction-dielectric hybrid isolation. Among them, PN junction isolation is a relatively common isolation method. However, the PN junction isolation depth of a three-dimensional silicon magnetic sensitive transistor needs to reach 20 to 40 μm. The diffusion time to reach this depth is long, and both longitudinal and lateral diffusion will occur during the diffusion process, making the isolation area wider, seriously affecting the integration of the device.

[0005] Therefore, it is an urgent problem to manufacture miniaturized and integrated silicon magnetic-sensitive transistors so that they can effectively limit the degree of carrier deflection in the magnetic field, reduce the influence of parasitic effects on the silicon magnetic-sensitive transistors, and have good radiation resistance, magnetic sensitivity and temperature characteristics. Summary of the Invention

[0006] In order to overcome the above problems, the inventors conducted intensive research and designed a fully dielectrically isolated silicon magnetic-sensitive triode and its manufacturing process. By integrating MEMS technology and silicon on insulating substrate (SOI) technology, a silicon magnetic-sensitive triode with a fully dielectric isolation structure was produced on the device silicon. While realizing the three-dimensional structure of the silicon magnetic-sensitive triode, isolation between components was effectively achieved, and at the same time, the degree of carrier deflection under the action of the magnetic field was limited, thereby improving the magnetic sensitivity and temperature characteristics of the silicon magnetic-sensitive triode, thereby completing the present invention.

[0007] Specifically, the purpose of the present invention is to provide the following aspects:

[0008] In a first aspect, a fully dielectrically isolated silicon magnetically sensitive triode is provided, wherein the fully dielectrically isolated silicon magnetically sensitive triode comprises an SOI silicon magnetically sensitive triode and a dielectric isolation ring, wherein the SOI silicon magnetically sensitive triode comprises a device silicon 1, a substrate silicon 2, and a buried silicon dioxide 3, wherein a silicon magnetically sensitive triode is arranged on the device silicon 1.

[0009] The dielectric isolation ring and the buried silicon dioxide layer 3 form a full dielectric isolation structure.

[0010] In a second aspect, a manufacturing process for a fully dielectrically isolated silicon magnetically sensitive triode is provided, which is preferably used to manufacture the fully dielectrically isolated silicon magnetically sensitive triode described in the first aspect, and the manufacturing process comprises the following steps:

[0011] Step 1: Clean wafer 1 and perform photolithography on the upper surface of wafer 1 to etch the registration mark;

[0012] Step 2: Clean the wafer 2 and grow a silicon dioxide layer on both sides;

[0013] Step 3, bonding the lower surface of the wafer to the upper surface of the second wafer;

[0014] Step 4: Secondary photolithography to transfer the registration marks on the upper surface of wafer one to the lower surface of wafer two;

[0015] Step 5: Thinning, polishing, and cleaning the upper surface of the wafer to form an SOI wafer;

[0016] Step 6: perform three photolithography steps to etch the isolation grooves of the dielectric isolation ring and the base region deep grooves on the upper surface of the device silicon 1;

[0017] Step 7: Inject boron ions into the deep trench of the base region to form p + heavily doped regions;

[0018] Step 8: growing a silicon dioxide layer on the upper surface of the device silicon 1 to fill the isolation trench and the base region deep trench to form a dielectric isolation ring and a base region.

[0019] In a third aspect, a fully dielectrically isolated silicon magnetic-sensitive triode prepared by the manufacturing process described in the second aspect is provided.

[0020] The beneficial effects of the present invention include:

[0021] (1) The fully dielectrically isolated silicon magnetic-sensitive triode provided by the present invention forms a fully dielectrically isolated structure by fabricating a dielectric isolation ring on the device silicon, so that the dielectric isolation ring and the buried silicon dioxide layer form a fully dielectrically isolated structure, which wraps the silicon magnetic-sensitive triode, thereby achieving effective isolation from the load resistor and the substrate, limiting the deflection of carriers, reducing the parasitic effect of the substrate, improving the radiation resistance of the silicon magnetic-sensitive triode, and improving the magnetic sensitivity and temperature characteristics;

[0022] (2) The manufacturing process of the fully dielectrically isolated silicon magnetic-sensitive triode provided by the present invention integrates MEMS technology and SOI technology. The fully dielectrically isolated structure manufactured is compatible with the integration process, thus realizing the miniaturization and integration of the silicon magnetic-sensitive triode;

[0023] (3) The fully dielectrically isolated silicon magnetic-sensitive triode prepared by the manufacturing process provided by the present invention not only realizes the three-dimensional structure of the silicon magnetic-sensitive triode, but also limits the degree of carrier deflection under the action of the magnetic field, laying the foundation for the mass production of high-performance silicon magnetic-sensitive triodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the overall structure of a fully dielectrically isolated silicon magnetic-sensitive triode according to a preferred embodiment of the present invention is shown;

[0025] Figure 2 A schematic top view of a fully dielectrically isolated silicon magnetic-sensitive triode according to a preferred embodiment of the present invention is shown;

[0026] Figure 3 An equivalent circuit diagram of a fully dielectrically isolated silicon magnetic-sensitive triode according to a preferred embodiment of the present invention is shown;

[0027] Figures 4-1 to 4-10 A flowchart showing a manufacturing process of a fully dielectrically isolated silicon magnetic-sensitive triode according to a preferred embodiment of the present invention is provided;

[0028] Figures 5-1 to 5-3 The I of the silicon magnetic sensitive transistor without isolation structure, the silicon magnetic sensitive transistor with PN junction isolation structure and the silicon magnetic sensitive transistor with full dielectric isolation structure described in Experimental Example 1 of the present invention are shown. C -V CE Characteristic curve diagram;

[0029] Figures 6-1 to 6-3 The I of the silicon magnetic sensitive transistor without isolation structure, the silicon magnetic sensitive transistor with PN junction isolation structure and the silicon magnetic sensitive transistor with full dielectric isolation structure under different magnetic fields in Experimental Example 1 of the present invention are shown.C -V CE Characteristic curve diagram;

[0030] Figures 7-1 to 7-3 The I of the silicon magnetic sensitive transistor without isolation structure, the silicon magnetic sensitive transistor with PN junction isolation structure and the silicon magnetic sensitive transistor with full dielectric isolation structure at different temperatures in Experimental Example 1 of the present invention are shown. C -V CE Characteristic curve diagram.

[0031] Description of Figure Numbers:

[0032] 1-Device silicon;

[0033] 2-substrate silicon;

[0034] 3-buried silicon dioxide;

[0035] 4-launching area;

[0036] 51- medium isolation ring 1;

[0037] 52- medium isolation ring 2;

[0038] 53-Dielectric isolation ring three;

[0039] 6-collector area;

[0040] 7-base region;

[0041] 8-silicon dioxide layer;

[0042] 91-metal Al layer 1;

[0043] 92-metal Al layer 2;

[0044] B-base;

[0045] C-collector;

[0046] E-emitter;

[0047] R b - Base load resistor;

[0048] R L - Collector load resistor;

[0049] V DD -power supply;

[0050] GND-ground;

[0051] V out - output voltage;

[0052] SMST - Silicon Magnetic Sensitive Transistor. DETAILED DESCRIPTION

[0053] The present invention will be further described in detail below by the accompanying drawings and Examples. Through these descriptions, the features and advantages of the present invention will become more clear and distinct. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0054] In a first aspect of the present invention, a fully dielectrically isolated silicon magnetic-sensitive triode is provided, which includes an SOI silicon magnetic-sensitive triode and a dielectric isolation ring. The SOI silicon magnetic-sensitive triode includes a device silicon 1, a substrate silicon 2, and a buried silicon dioxide 3. The silicon magnetic-sensitive triode is provided on the device silicon 1.

[0055] Among them, the dielectric isolation ring and the buried silicon dioxide form a full dielectric isolation structure to achieve full dielectric isolation of the silicon magnetic sensitive transistor, such as Figure 1 shown.

[0056] Wherein, the SOI is silicon on an insulating substrate.

[0057] According to a preferred embodiment of the present invention, the device silicon 1 is <100> Crystalline double-sided polished high-resistance p-type single crystal silicon wafer with a thickness of 20-40μm.

[0058] Preferably, the thickness of the device silicon 1 is 30 μm;

[0059] More preferably, the resistivity of the device silicon 1 is greater than 100Ω·cm.

[0060] According to a preferred embodiment of the present invention, the substrate silicon 2 is <100> Crystal orientation double-sided polished high-resistance p-type single crystal silicon wafer, thickness 450 ~ 600μm.

[0061] Preferably, the silicon substrate 2 has a thickness of 500 μm and a resistivity greater than 100 Ω·cm.

[0062] In a further preferred embodiment, the buried silicon dioxide layer 3 is formed between the device silicon 1 and the substrate silicon 2, and has a thickness of 500-1000 nm, preferably 800 nm.

[0063] According to a preferred embodiment of the present invention, the dielectric isolation ring includes a dielectric isolation ring 1 51, a dielectric isolation ring 2 52 and a dielectric isolation ring 3 53. Figure 1 As shown, they are all arranged in the device silicon 1.

[0064] Preferably, the dielectric isolation ring 1 is arranged in the middle of the device silicon 1, the dielectric isolation ring 2 and the dielectric isolation ring 3 are arranged on both sides of the dielectric isolation ring 1, and the three dielectric isolation rings are independent of each other.

[0065] More preferably, the distance between the dielectric isolation ring 1 and the dielectric isolation ring 2 is greater than or equal to 2 μm, preferably 2 μm, and the distance between the dielectric isolation ring 2 and the dielectric isolation ring 3 is greater than or equal to 2 μm, preferably 2 μm.

[0066] In the present invention, due to the limitations of lithography and process, the spacing between adjacent dielectric isolation rings cannot be made too small, while too large a spacing will affect the integration of the overall structure. After repeated experiments, the inventors found that setting the spacing between the three dielectric isolation rings to be greater than or equal to 2μm, preferably 2μm, can both meet the processing technology requirements and ensure the integration of the overall structure.

[0067] In a further preferred embodiment, the isolation ring dielectrics of the dielectric isolation ring 1, dielectric isolation ring 2 and dielectric isolation ring 3 are all silicon dioxide.

[0068] In a further preferred embodiment, the depths of the dielectric isolation ring 1, the dielectric isolation ring 2 and the dielectric isolation ring 3 are all consistent with the thickness of the device silicon 1, and are all 20-40 μm, preferably 30 μm.

[0069] Preferably, the width of the dielectric isolation ring is 1-2 μm, preferably 1.5 μm.

[0070] The width of the dielectric isolation ring refers to the width of the isolation groove of the dielectric isolation ring, that is, the width of the dielectric filled in the isolation groove along the x-axis and y-axis directions. Figure 1 As shown (x, y, z represent coordinate axes).

[0071] In the present invention, the dielectric isolation ring 1, the dielectric isolation ring 2 and the dielectric isolation ring 3 form a full dielectric isolation structure with the buried silicon dioxide layer 3, thereby achieving effective isolation between the silicon magnetic sensitive transistor, the load resistor and the substrate.

[0072] According to a preferred embodiment of the present invention, the silicon magnetic-sensitive triode includes an emitter region 4, a collector region 6 and a base region 7, all of which are arranged inside a dielectric isolation ring.

[0073] In a further preferred embodiment, the collector region 6 is formed on the upper surface of the device silicon 1 and its doping type is n + Heavily doped, doping concentration is 1E15~1E16cm -3 , preferably 1E15cm -3 ;

[0074] The base region 7 is made on the upper surface of the device silicon 1 and its doping type is p + Heavily doped, doping concentration is 1E18~1E19cm -3 , preferably 1E18cm -3 .

[0075] Preferably, ICP (inductively coupled plasma) is used to etch a base region deep groove on the upper surface of the device silicon 1, and boron ions are injected through the base region deep groove to form p + The heavily doped region serves as a base region, wherein the base region deep trench etching depth is 25-30 μm, preferably 25 μm, and the width is 2-4 μm, preferably 3 μm.

[0076] The inventors have found that the above method for producing the base region can increase the depth of boron ion implantation, effectively modulate the recombination of carriers in the base region, and improve the magnetic sensitivity of the silicon magnetic sensitive triode.

[0077] In a further preferred embodiment, the emitter region 4 is made on the lower surface of the device silicon 1 and its doping type is n + Heavily doped, doping concentration is 1E18~1E20cm -3 , preferably 1E20cm -3 .

[0078] Preferably, an emitter region etching pit is formed on the lower surface of the substrate silicon 2, and the etching position corresponds to the collector region 6 on the upper surface of the device silicon 1. Phosphorus ions are injected through the emitter region etching pit to form an n-type ion on the lower surface of the device silicon 1. + A heavily doped region serving as an emitter region 4;

[0079] The depth of the etching pit in the emitter region is consistent with the thickness of the substrate silicon 2, both being 450-600 μm, preferably 500 μm.

[0080] More preferably, the base region length of the silicon magnetic sensitive transistor is the distance between the emitter region 4 and the base region 7, preferably 150-180 μm, such as 180 μm;

[0081] The base width is the distance between the emitter region 4 and the collector region 6, and is preferably 20-40 μm, such as 30 μm.

[0082] Among them, when the base region length and base region width are within the above preferred ranges, the magnetic sensitive transistor can have better magnetic sensitive characteristics.

[0083] According to a preferred embodiment of the present invention, a base load resistor R is also fabricated on the device silicon 1. b and the collector load resistor R L , where the base load resistor R b Set inside the dielectric isolation ring 2, the collector load resistor R L Set inside the dielectric isolation ring three.

[0084] In a further preferred embodiment, the base load resistor R b and the collector load resistor R L Both are n- Doping, the doping ion type is phosphorus ion, the doping concentration is 5E14~5E15cm -3 , preferably 5E14cm -3 ;

[0085] Base load resistor R b and the collector load resistor R L The resistance value is 1.5 to 3.0 kΩ, preferably 1.5 kΩ.

[0086] The inventors have found that the base load resistor R b and the collector load resistor R L All by n - The doped region is formed, and the three dielectric isolation rings are independent of each other, which can effectively suppress the over-deflection of carriers under the action of the magnetic field and realize electrical isolation between components.

[0087] According to a preferred embodiment of the present invention, a silicon dioxide layer 8 is provided on both the upper surface of the device silicon 1 and the lower surface of the substrate silicon 2 to play an insulating or passivation role;

[0088] The thickness of the silicon dioxide layer 8 is 500-1000 nm, preferably 800 nm.

[0089] In a further preferred embodiment, a lead hole is etched on the surface of the silicon dioxide layer 8 on the upper surface of the device silicon 1, and a metal Al layer 91 is vacuum-deposited on the upper surface of the lead hole.

[0090] A metal Al layer 92 is vacuum-deposited on the surface of the silicon dioxide layer 8 on the lower surface of the silicon substrate 2.

[0091] Preferably, the first metal Al layer is reverse-etched to form the collector C, the base B, the metal interconnection line and the bonding pad, and the second metal Al layer formed by evaporation forms the emitter E.

[0092] In a further preferred embodiment, Figure 2 As shown, the base and base load resistor R b Connect one end of the collector to the collector load resistor R L One end of the connection,

[0093] The base load resistor R b The other end of the collector load resistor R L The other end is connected to the power supply V DD connect,

[0094] The emitter is grounded GND.

[0095] Among them, the collector and R LThe connection is used as the output voltage V out end.

[0096] In the present invention, Figure 3 As shown, when V DD When an external magnetic field is applied along the magnetic sensitive direction, the collector current of the silicon magnetic sensitive transistor SMST will change, so R L The voltage at both ends will also change, that is, the collector voltage will change with the change of the external magnetic field. The size of the external magnetic field along the magnetic sensitive direction can be obtained through the change of the collector voltage.

[0097] The silicon magnetic-sensitive triode provided by the present invention adopts a full dielectric isolation structure to achieve effective isolation between the silicon magnetic-sensitive triode, the load resistor and the substrate, effectively realizes isolation between components, and at the same time limits the degree of deflection of carriers under the action of the magnetic field, thereby improving the magnetic sensitivity and temperature characteristics of the silicon magnetic-sensitive triode.

[0098] The second aspect of the present invention provides a process for manufacturing a fully dielectrically isolated silicon magnetic-sensitive triode, preferably used to manufacture the silicon magnetic-sensitive triode described in the first aspect, the manufacturing process comprising the following steps: Figures 4-1 to 4-10 As shown:

[0099] Step 1: clean wafer 1, perform photolithography on the upper surface of wafer 1, and etch the alignment mark.

[0100] Wherein, the wafer 1 is <100> Double-sided polished high-resistance p-type single-crystal silicon wafer with a resistivity greater than 100Ω·cm.

[0101] Preferably, the wafer is cleaned using the RCA standard cleaning method.

[0102] Step 2: Clean the wafer and grow a silicon dioxide layer on both sides. Figure 4-1 shown.

[0103] Preferably, the wafer <100> Double-sided polished high-resistance p-type single-crystal silicon wafer with a resistivity greater than 100Ω·cm.

[0104] More preferably, a silicon dioxide layer is grown on both sides by thermal oxidation, with a buried silicon dioxide layer 3 grown on the upper surface of the wafer and a silicon dioxide layer 8 grown on the lower surface;

[0105] The thickness is 500 to 1000 nm, preferably 800 nm.

[0106] Step 3: Bond the lower surface of the wafer to the upper surface of the second wafer.

[0107] Step 4: Secondary photolithography to transfer the alignment marks on the upper surface of wafer one to the lower surface of wafer two.

[0108] Among them, it is preferred to use a double-sided photolithography process to transfer the registration mark.

[0109] Step 5: Thinning the upper surface of the wafer, polishing, and cleaning to form an SOI wafer. Figure 4-2 shown.

[0110] Among them, it is preferred to use a wafer thinning machine to thin the upper surface of the wafer to 20μm-40μm, preferably 30μm.

[0111] After thinning, wafer 1 is device silicon 1, and wafer 2 is substrate silicon 2.

[0112] Step 6, three times of photolithography, etching the isolation groove of the dielectric isolation ring and the base deep groove on the upper surface of the device silicon 1, such as Figure 4-3 shown.

[0113] Among them, dry etching of the isolation trench and the base region deep trench is preferably adopted.

[0114] In the present invention, the base region width of the three-dimensional silicon magnetic-sensitive transistor is 20 to 40 μm. The existing technology has the problem of insufficient single etching depth when manufacturing a dielectric isolation ring in a silicon magnetic-sensitive transistor. In order to solve the above problem, the present invention preferably etches an isolation groove with a depth of 10-20 μm on the lower surface of the wafer during the manufacturing process, and then bonds the lower surface of the wafer to the upper surface of the second wafer to form an SOI wafer, and then continues to etch the isolation groove on the upper surface of the device silicon 1 until the isolation groove formed by the two etchings is penetrated, and then fills the dielectric and performs flattening treatment. The problem of insufficient etching depth in a single process is solved by using a double process.

[0115] According to a preferred embodiment of the present invention, the depth of the etched isolation groove is consistent with the thickness of the device silicon, both of which are 20 μm-40 μm, preferably 30 μm; the width of the isolation groove is 1-2 μm, preferably 1.5 μm;

[0116] The depth of the etched base region deep trench is 25-30 μm, preferably 25 μm; the width of the base region deep trench is 2-4 μm, preferably 3 μm.

[0117] Step 7: Inject boron ions into the deep trench of the base region to form p + Heavily doped region.

[0118] Preferably, the ICP technology is used to etch the base region deep trench, and the doping concentration of the base region is 1E18-1E19cm -3 , preferably 1E18cm -3 .

[0119] More preferably, the inner side surface of the etched base region is an inclined surface, and the angle between the inner side surface and the z-axis is 5-10°.

[0120] The inventors have found that using ICP to etch deep trenches in the base region is beneficial to increasing the depth of boron ion implantation, effectively modulating the recombination of carriers in the base region, and improving the magnetic sensitivity of the silicon magnetic sensitive triode.

[0121] Step 8: grow a silicon dioxide layer on the upper surface of the device silicon 1, fill the isolation trench and the base deep trench, and form a dielectric isolation ring and base region, as shown in FIG. Figure 4-4 shown.

[0122] Preferably, a silicon dioxide layer is grown on the upper surface of the device silicon 1 by vapor phase epitaxy, and the isolation trenches and the base deep trenches are filled with silicon dioxide to achieve effective isolation between the components.

[0123] After the isolation trench and the base deep trench are filled, the upper surface of the device silicon 1 is polished to form the dielectric isolation ring 1, the dielectric isolation ring 2, the dielectric isolation ring 3 and the base region 7.

[0124] Step 9: Clean the SOI wafer and grow a thin layer of oxygen on the upper surface of the device silicon 1.

[0125] The thickness of the thin oxide layer is 30 to 50 nm.

[0126] Step 10, four times of photolithography, etching the collector load resistor R on the upper surface of the device silicon 1 L Window and base load resistors R b window, and implant phosphorus ions to form n - doped region, serving as the collector load resistor R L and the base load resistor R b ,like Figure 4-5 shown.

[0127] Preferably, the collector load resistor R L and the base load resistor R b The doping concentration is 5E14~5E15cm -3 , preferably 5E14cm -3 ;

[0128] Base load resistor R b and the collector load resistor R L The resistance value is 1.5 to 3.0 kΩ, preferably 1.5 kΩ.

[0129] Step 11, five times of photolithography, etching the collector window on the surface of the device silicon 1, and injecting phosphorus ions to form n + The heavily doped region, serving as the collector region 6, is Figure 4-6 shown.

[0130] Preferably, the doping concentration of the collector region is 1E15-1E16 cm -3 , preferably 1E15cm-3 .

[0131] Step 12: clean the SOI wafer and perform high-temperature annealing to form the collector region 6, the base region 7 and the load resistor, and remove the thin oxygen layer.

[0132] Step 13: clean the SOI wafer and grow a silicon dioxide layer on the upper surface of the device silicon 1.

[0133] Preferably, a silicon dioxide layer is grown on the upper surface of the device silicon 1 by chemical vapor deposition (CVD) as an insulating layer.

[0134] More preferably, the thickness of the silicon dioxide layer is 400 to 800 nm, preferably 500 nm.

[0135] Step 14, six times of photolithography, etching lead holes on the upper surface of the device silicon 1 to form the lead holes of the collector region 6, the base region 7 and the load resistor, as shown in FIG. Figure 4-7 shown.

[0136] Step 15, seven times of photolithography, etching the emitter window on the lower surface of the substrate silicon 2 to form an etching pit, and injecting phosphorus ions to form n + The heavily doped region, serving as the emitter region 4, is Figure 4-8 shown.

[0137] Wherein, ICP is used to etch the emitter window, and the etching position of the emitter etching pit corresponds to the collector region 6 on the upper surface of the device silicon 1;

[0138] Preferably, the doping concentration of phosphorus ions in the emission region is 1E18-1E20 cm -3 , preferably 1E20cm -3 .

[0139] Step 16: clean the SOI wafer and perform high-temperature annealing to form the emitter region 4.

[0140] Step 17: clean the SOI wafer and grow an Al layer on the upper surface of the device silicon 1.

[0141] Preferably, a metal Al layer is grown on the upper surface of the device silicon 1 by vacuum evaporation method.

[0142] The thickness is 400 nm to 600 nm, preferably 500 nm.

[0143] Step 18, eight times of photolithography, reverse etching the metal Al layer 1, forming metal Al interconnects and electrodes on the upper surface of the device silicon 1, as shown in FIG. Figure 4-9 shown.

[0144] Step 19, clean the SOI wafer and grow a second metal Al layer on the lower surface of the silicon substrate 2, as shown in FIG. Figure 4-10 shown.

[0145] The second metal Al layer is grown on the lower surface of the silicon substrate 2 by using a vacuum evaporation method.

[0146] Step 20: alloying to form an ohmic contact.

[0147] Preferably, the alloying is performed at 420° C. in a vacuum or nitrogen environment for 30 minutes.

[0148] The third aspect of the present invention provides a fully dielectrically isolated silicon magnetic-sensitive triode manufactured by the manufacturing process described in the second aspect.

[0149] Among them, the silicon magnetic-sensitive transistor adopts a non-magnetized packaging process to package the chip, completing the production of a fully dielectric-isolated silicon magnetic-sensitive transistor.

[0150] The silicon magnetic-sensitive triode with a full dielectric isolation structure manufactured by integrating MEMS technology and SOI process described in the present invention can effectively realize isolation between components, while limiting the degree of deflection of carriers under the action of magnetic field, improving the magnetic sensitivity and temperature characteristics of the silicon magnetic-sensitive triode, realizing the miniaturization and integration of the silicon magnetic-sensitive triode, and laying the foundation for the mass production of high-performance silicon magnetic-sensitive triodes.

[0151] Example

[0152] Example 1

[0153] Follow the steps below to make a fully dielectrically isolated silicon magnetic-sensitive transistor:

[0154] Step 1: clean wafer 1, perform photolithography on the upper surface of wafer 1, and etch the alignment mark.

[0155] Wherein, the wafer 1 is <100> Double-sided polished high-resistance p-type single-crystal silicon wafer with a resistivity greater than 100Ω·cm.

[0156] Preferably, the wafer is cleaned using the RCA standard cleaning method.

[0157] Step 2: Clean wafer 2 and grow a silicon dioxide layer on both sides.

[0158] The wafer two <100> Double-sided polished high-resistance p-type single-crystal silicon wafer with a resistivity greater than 100Ω·cm.

[0159] The silicon dioxide layer is grown on both sides by thermal oxidation method, with buried silicon dioxide grown on the upper surface of the wafer and silicon dioxide layer grown on the lower surface.

[0160] The thickness is 800nm.

[0161] Step 3: Bond the lower surface of the wafer to the upper surface of the second wafer.

[0162] Step 4: Secondary photolithography to transfer the alignment marks on the upper surface of wafer one to the lower surface of wafer two.

[0163] Among them, a double-sided photolithography process is used to transfer the registration marks.

[0164] Step 5: Thinning, polishing and cleaning the upper surface of the wafer to form an SOI wafer.

[0165] Among them, a wafer thinning machine is used to thin the upper surface of the wafer to 30μm.

[0166] After thinning, wafer one is device silicon, and wafer two is substrate silicon.

[0167] Step 6: perform three photolithography operations to etch the isolation grooves of the dielectric isolation ring and the base region deep grooves on the upper surface of the device silicon 1.

[0168] Wherein, the isolation trench and the base region deep trench are etched by dry etching.

[0169] According to a preferred embodiment of the present invention, the depth of the etched isolation groove is consistent with the thickness of the device silicon, both of which are 30 μm; the width of the isolation groove is 1.5 μm;

[0170] The depth of the etched base region deep trench is 25 μm; the width of the base region deep trench is 3 μm.

[0171] Step 7: Inject boron ions into the deep trench of the base region to form p + Heavily doped region.

[0172] Preferably, the ICP technique is used to etch the base region deep trench, and the doping concentration of the base region is 1E18cm -3 .

[0173] The inner side surface of the etched base region is an inclined surface, and the angle between the inner side surface and the z-axis is 5 to 10 degrees.

[0174] The inventors have found that using ICP to etch deep trenches in the base region is beneficial to increasing the depth of boron ion implantation, effectively modulating the recombination of carriers in the base region, and improving the magnetic sensitivity of the silicon magnetic sensitive triode.

[0175] Step 8: growing a silicon dioxide layer on the upper surface of the device silicon to fill the isolation trench and the base region deep trench to form a dielectric isolation ring and a base region.

[0176] A silicon dioxide layer is grown on the upper surface of the device silicon using the vapor phase epitaxy method, and the isolation trench and the base deep trench are filled with silicon dioxide to achieve effective isolation between the components.

[0177] After the isolation trench and the base region deep trench are filled, the upper surface of the device silicon is polished to form a dielectric isolation ring 1, a dielectric isolation ring 2, a dielectric isolation ring 3 and a base region.

[0178] Step 9: Clean the SOI wafer and grow a thin layer of oxygen on the upper surface of the device silicon.

[0179] The thickness of the thin oxide layer is 30 nm.

[0180] Step 10: Photolithography is performed four times to etch the collector load resistor R on the upper surface of the device silicon. L Window and base load resistors R b window, and implant phosphorus ions to form n - doped region, serving as the collector load resistor R L and the base load resistor R b .

[0181] Preferably, the collector load resistor R L and the base load resistor R b The doping concentration is 5E14cm -3 ;

[0182] Base load resistor R b and the collector load resistor R L The resistance value is 1.5kΩ.

[0183] Step 11, five times of photolithography, etching the collector window on the silicon surface of the device, and injecting phosphorus ions to form n + The heavily doped region serves as the collector region.

[0184] Preferably, the doping concentration of the collector region is 1E15 cm -3 .

[0185] Step 12: Clean the SOI wafer and perform high-temperature annealing to form a collector region, a base region, and a load resistor, and remove the thin oxygen layer.

[0186] Step 13: clean the SOI wafer and grow a silicon dioxide layer on the upper surface of the device silicon.

[0187] A silicon dioxide layer is grown on the upper surface of the device silicon using the CVD method as an insulating layer.

[0188] More preferably, the thickness of the silicon dioxide layer is 500 nm.

[0189] Step 14: perform six photolithography steps to etch lead holes on the upper surface of the device silicon to form lead holes for the collector region, base region, and load resistor.

[0190] Step 15, seven times of photolithography, etching the emitter window on the lower surface of the substrate silicon to form an etch pit, and injecting phosphorus ions to form n+ The heavily doped region serves as the emitter region.

[0191] Wherein, ICP is used to etch the emitter window, and the etching position of the emitter etching pit corresponds to the collector area on the upper surface of the device silicon;

[0192] Preferably, the doping concentration of phosphorus ions in the emission region is 1E20 cm -3 .

[0193] Step 16: clean the SOI wafer and perform high-temperature annealing to form an emitter region.

[0194] Step 17: clean the SOI wafer and grow an Al layer on the upper surface of the device silicon.

[0195] A metal Al layer with a thickness of 500 nm is grown on the upper surface of the device silicon by vacuum evaporation method.

[0196] Step 18: perform eight photolithography operations to reverse the metal Al layer 1 and form metal Al interconnects and electrodes on the upper surface of the device silicon.

[0197] Step 19: clean the SOI wafer and grow a second metal Al layer on the lower surface of the silicon substrate.

[0198] The second metal Al layer is grown on the lower surface of the silicon substrate 2 by using a vacuum evaporation method.

[0199] Step 20: alloying to form an ohmic contact.

[0200] The alloying is preferably performed at 420° C. in a vacuum or nitrogen environment for 30 minutes.

[0201] The non-magnetized packaging process is used to package the chip and complete the preparation of the silicon magnetic sensitive triode.

[0202] Experimental example

[0203] Experimental Example 1

[0204] In this experimental example, TCAD-Athena software is used to construct process simulation models of silicon magnetic sensitive transistors without isolation structure, silicon magnetic sensitive transistors with PN junction isolation structure, and silicon magnetic sensitive transistors with full dielectric isolation structure described in Example 1 of the present invention. The I of silicon magnetic sensitive transistors under different magnetic fields and temperatures is simulated and studied. C -V CE Characteristics(I C is the collector current, V CE is the collector voltage), the comparison results are as follows Figures 5-1 to 5-3 、 Figures 6-1 to 6-3 and Figures 7-1 to 7-3 shown.

[0205] in, Figures 5-1 to 5-3 The silicon magnetic sensitive transistor without isolation structure, the silicon magnetic sensitive transistor with PN junction isolation structure and the silicon magnetic sensitive transistor with full dielectric isolation structure according to embodiment 1 of the present invention are shown respectively. C -V CE Characteristics, at room temperature (T = 300K) and without an external magnetic field, the setting conditions are as follows: collector voltage V CE The range is 0V~5V, the step size is 0.25V, and the base injection current I B The range is 0mA to 5mA, with a step size of 1mA.

[0206] Depend on Figures 5-1 to 5-3 It can be seen that the amplification factor β of the three structures of silicon magnetic sensitive transistors is less than 1. Under the same conditions, the collector current I C (2.3mA) for comparison, the collector current I C (2.4mA) is larger, and the collector current I C (2.2mA) has decreased, so the silicon magnetic sensitive transistor I made based on the full dielectric isolation structure C -V CE Good characteristics.

[0207] Figures 6-1 to 6-3 The I of the silicon magnetic sensitive transistor without isolation structure, the silicon magnetic sensitive transistor with PN junction isolation structure and the silicon magnetic sensitive transistor with full dielectric isolation structure under different magnetic fields are shown respectively. C -V CE Characteristics, at room temperature (T = 300K) set conditions are as follows: collector voltage V CE The range is 0V~5V, the step size is 0.25V, and the base injection current I B The current is 5 mA, and a magnetic field of ±0.3T is applied to the magnetic sensitive directions of the silicon magnetic sensitive transistors of the three structures respectively.

[0208] Depend on Figures 6-1 to 6-3 It can be seen that the magnetic sensitivity S (0.88mA / T) of the silicon magnetic sensitive transistor with full dielectric isolation structure is the largest, the magnetic sensitivity S (0.75mA / T) of the silicon magnetic sensitive transistor with PN junction isolation structure is second, and the magnetic sensitivity S (0.74mA / T) of the silicon magnetic sensitive transistor without isolation structure is the smallest. Therefore, the magnetic sensitivity of the silicon magnetic sensitive transistor made based on full dielectric isolation structure is better.

[0209] Figures 7-1 to 7-3 The I of silicon magnetic sensitive transistors without isolation structure, PN junction isolation structure and full dielectric isolation structure are shown at different temperatures. C -V CECharacteristics, when there is no external magnetic field, the conditions are as follows: collector voltage V CE The range is 0V~5V, the step size is 0.25V, and the base injection current I B The current is 5mA, and the temperature variation range of the three structures of silicon magnetic sensitive transistors is -40℃~85℃, with a step size of 20℃.

[0210] As shown in Figure 7, the temperature coefficient a of the silicon magnetic sensitive transistor with a full dielectric isolation structure is the smallest (1629ppm / °C), followed by the temperature coefficient a of the silicon magnetic sensitive transistor with a PN junction isolation structure (1669ppm / °C), and the temperature coefficient a of the silicon magnetic sensitive transistor without isolation structure is the largest (1676ppm / °C). Therefore, the temperature drift of the silicon magnetic sensitive transistor made based on the full dielectric isolation structure is the smallest.

[0211] In summary, the manufacturing process described in the present invention, that is, the silicon magnetic sensitive transistor with a full dielectric isolation structure designed and manufactured on the device silicon by integrating MEMS technology and SOI technology, can effectively realize isolation between components, while limiting the degree of deflection of carriers under the action of the magnetic field, improving the magnetic sensitivity and temperature characteristics of the silicon magnetic sensitive transistor, realizing the miniaturization and integration of the silicon magnetic sensitive transistor, and laying the foundation for the mass production of high-performance silicon magnetic sensitive transistors.

[0212] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", "front", "back", etc. indicate orientations or positional relationships based on the orientations or positional relationships in the working state of the present invention. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0213] The present invention has been described above with reference to preferred embodiments, but these embodiments are merely exemplary and serve only as illustrations. On this basis, various replacements and improvements can be made to the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A process for manufacturing a fully dielectrically isolated silicon magnetically sensitive triode, which is used to manufacture a fully dielectrically isolated silicon magnetically sensitive triode, characterized in that: The fully dielectrically isolated silicon magnetic-sensitive triode comprises an SOI silicon magnetic-sensitive triode and a dielectric isolation ring. The SOI silicon magnetic-sensitive triode comprises device silicon (1), substrate silicon (2) and buried silicon dioxide (3). The silicon magnetic-sensitive triode is arranged on the device silicon (1). A base load resistor (R b ) and the collector load resistor (R L ), inductively coupled plasma is used to etch a base region deep groove on the upper surface of the device silicon (1), and boron ions are injected through the base region deep groove to form p + The heavily doped region, serving as the base region, The dielectric isolation ring and the buried silicon dioxide (3) form a full dielectric isolation structure. The dielectric isolation ring comprises a dielectric isolation ring 1 (51), a dielectric isolation ring 2 (52) and a dielectric isolation ring 3 (53), all of which are arranged in the device silicon (1), and the three dielectric isolation rings are independent of each other; The silicon magnetic sensitive transistor is arranged inside the dielectric isolation ring (51), and the base load resistor (R b ) is set inside the dielectric isolation ring 2 (52), the collector load resistor (R L ) is arranged inside the dielectric isolation ring three (53); The manufacturing process comprises the following steps: Step 1: Clean wafer 1 and perform photolithography on the upper surface of wafer 1 to etch the registration mark; Step 2: Clean the wafer 2 and grow a silicon dioxide layer on both sides; Step 3, bonding the lower surface of the wafer to the upper surface of the second wafer; Step 4: Secondary photolithography to transfer the registration marks on the upper surface of wafer one to the lower surface of wafer two; Step 5: Thinning, polishing, and cleaning the upper surface of the wafer to form an SOI wafer; Step 6, photolithography three times, etching the isolation groove of the dielectric isolation ring and the base region deep groove on the upper surface of the device silicon (1); Step 7: Inject boron ions into the deep trench of the base region to form p + heavily doped regions; Step 8, growing a silicon dioxide layer on the upper surface of the device silicon (1), filling the isolation trench and the base region deep trench, and forming a dielectric isolation ring and a base region; In step 6, an isolation groove with a depth of 10-20 μm is first etched on the lower surface of the wafer, and then the lower surface of the wafer is bonded to the upper surface of the second wafer to form an SOI wafer. Then, the isolation groove is further etched on the upper surface of the device silicon (1) until the isolation groove formed by the two etchings is penetrated, and then the dielectric is filled and flattened.

2. The manufacturing process of the fully dielectrically isolated silicon magnetic sensitive triode according to claim 1, characterized in that: The depths of the dielectric isolation ring 1 (51), dielectric isolation ring 2 (52) and dielectric isolation ring 3 (53) are all consistent with the thickness of the device silicon (1). The width of the isolation grooves of the dielectric isolation ring 1 (51), the dielectric isolation ring 2 (52) and the dielectric isolation ring 3 (53) are all 1 to 2 μm.

3. The manufacturing process of the fully dielectrically isolated silicon magnetic sensitive triode according to claim 1, characterized in that: The silicon magnetic sensitive triode comprises an emitter region (4), a collector region (6) and a base region (7), all of which are arranged inside a dielectric isolation ring (51).

4. The manufacturing process of the fully dielectrically isolated silicon magnetic sensitive triode according to claim 1, characterized in that: The base load resistor (R b ) and the collector load resistor (R L ) are both n - Doping, the doping ion type is phosphorus ion, the doping concentration is 5E14~5E15cm -3 .

5. The manufacturing process of the fully dielectrically isolated silicon magnetic sensitive triode according to claim 1, characterized in that: After step 8, the following steps are further included: Step 9, cleaning the SOI wafer and growing a thin layer of oxygen on the upper surface of the device silicon (1); Step 10, four times of photolithography, etching the collector load resistor window and the base load resistor window on the upper surface of the device silicon (1), and injecting phosphorus ions to form n - doped region, serving as the collector load resistor (R L ) and the base load resistor (R b ); Step 11, five times of photolithography, etching the collector window on the upper surface of the device silicon (1), and injecting phosphorus ions to form n + A heavily doped region serving as a collector region (6); Step 12, cleaning the SOI wafer, performing high temperature annealing treatment, forming a collector region (6), a base region (7) and a load resistor, and removing the thin oxygen layer; Step 13, cleaning the SOI wafer and growing a silicon dioxide layer on the upper surface of the device silicon (1); Step 14, six times of photolithography to etch lead holes on the upper surface of the device silicon (1) to form lead holes for the collector region (6), the base region (7) and the load resistor; Step 15, seven times of photolithography, etching the emitter window on the lower surface of the substrate silicon (2) to form an etching pit, and injecting phosphorus ions to form n + A heavily doped region serving as an emitter region (4); Step 16, cleaning the SOI wafer and performing high temperature annealing to form an emitter region (4); Step 17, cleaning the SOI wafer and growing an Al layer on the upper surface of the device silicon (1); Step 18, eight times of photolithography, reverse etching the metal Al layer 1 (91), forming metal Al interconnection lines and electrodes on the upper surface of the device silicon 1; Step 19, cleaning the SOI wafer, and growing a second metal Al layer (92) on the lower surface of the silicon substrate (2); Step 20: alloying to form an ohmic contact.

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