High-voltage reverse blocking power semiconductor device based on super junction structure and manufacturing method thereof

Abstract

The application relates to a high-voltage reverse resistance type power semiconductor device based on a super-junction structure and a preparation method. The device comprises a semiconductor substrate and a cell region; the semiconductor substrate comprises a first-conductivity-type substrate, a first-conductivity-type drift region and a first-conductivity-type epitaxial layer; a super-junction structure is arranged in the first-conductivity-type drift region; cells in the cell region correspond to the first-conductivity-type epitaxial layer; second-conductivity-type columns in the super-junction structure are separated from second-conductivity-type base regions in the cell region through the first-conductivity-type epitaxial layer; and the second-conductivity-type columns in the super-junction structure are separated from second-conductivity-type collector regions arranged on the back of the first-conductivity-type substrate through the first-conductivity-type substrate. The application can reduce the difficulty of high-voltage super-junction high-aspect-ratio deep groove etching and filling, can reduce the on-state voltage drop and static loss while realizing high withstand voltage, and can realize bidirectional withstand voltage due to the forward and reverse withstand voltage PN junction.

Description

TECHNICAL FIELD

[0001] The present application relates to a power semiconductor device and a preparation method, in particular to a high-voltage reverse resistance type power semiconductor device based on super junction structure and a preparation method. BACKGROUND

[0002] In order to achieve a good compromise between on-state voltage drop and off-state loss, the existing IGBT (insulated gate bipolar transistor) device generally sets a high-doped FS layer near the collector, the existence of the FS layer is used to modulate the injection efficiency of the back P+ region. Due to the existence of the high-doped FS layer, the cell back surface cannot withstand voltage in the reverse voltage, therefore, the bidirectional voltage IGBT generally adopts a relatively thick NPT (No Punch Through) structure in the drift region. Due to the existence of the relatively thick NPT structure, the on-state voltage drop of the IGBT device will be very large, and the static loss will be very high, especially for the IGBT device with higher voltage demand, the drift region thickness increases accordingly, and the high loss causes the device to be unable to develop in the high voltage direction. SUMMARY

[0003] The purpose of the present application is to overcome the shortcomings in the prior art, and to provide a high-voltage reverse resistance type power semiconductor device based on super junction structure and a preparation method, which can effectively achieve high voltage while reducing on-state voltage drop, and can achieve bidirectional voltage, and is compatible with the existing process, safe and reliable.

[0004] According to the technical scheme provided by the present application, the high-voltage reverse resistance type power semiconductor device based on super junction structure comprises a semiconductor substrate with a first conductivity type, a cell region prepared in the center region of the semiconductor substrate, and a back electrode structure prepared on the back surface of the semiconductor substrate; the semiconductor substrate comprises a first conductivity type substrate, a first conductivity type drift region arranged on the front surface of the first conductivity type substrate, and a first conductivity type epitaxial layer arranged on the first conductivity type drift region by epitaxy;

[0005] The super junction structure is arranged in the first conductivity type drift region, the heights of the first conductivity type columns and the second conductivity type columns in the super junction structure are less than the thickness of the first conductivity type drift region, the cells in the cell region correspond to the first conductivity type epitaxial layer, the second conductivity type columns in the super junction structure are isolated from the second conductivity type base region in the cell region through the first conductivity type epitaxial layer, and the second conductivity type columns in the super junction structure are isolated from the second conductivity type collector region in the back electrode structure through the first conductivity type substrate, and the second conductivity type collector region is adjacent to the first conductivity type substrate.

[0006] The first-conductivity-type drift region comprises a plurality of drift base layers sequentially grown by an epitaxial process, and the drift base layers are stacked on the first-conductivity-type substrate.

[0007] After the epitaxial growth of a drift base layer, the grown drift base layer is etched to obtain a drift base layer groove, and the drift base layer groove is filled with impurities of the second conductivity type to form a drift base layer column of the second conductivity type after filling.

[0008] The drift base layer columns in each drift base layer correspond to each other, and the drift base layer columns in adjacent drift base layers contact each other, so that the drift base layer columns contact each other to form a second-conductivity-type column when all the drift base layers are used to form a required first-conductivity-type drift region, and a super-junction structure is obtained in the formed first-conductivity-type drift region, and the first-conductivity-type columns and the second-conductivity-type columns in the super-junction structure are alternately distributed in the first-conductivity-type drift region.

[0009] When the voltage is withstood, the first-conductivity-type columns and the second-conductivity-type columns of the drift base layer columns have the same amount of charges after mutual depletion.

[0010] In a cross section of the power semiconductor device, the cells in the cell region comprise a second-conductivity-type base region disposed in the first-conductivity-type epitaxial layer and a cell trench disposed in the first-conductivity-type epitaxial layer, the cell trench penetrates the second-conductivity-type base region, the bottom of the cell trench is located below the second-conductivity-type base region, the second-conductivity-type base region is in contact with the outer sidewall of the cell trench, and the depth of the cell trench is less than the thickness of the first-conductivity-type epitaxial layer.

[0011] An insulating oxide layer is disposed on the sidewall and the bottom wall of the cell trench, and a gate conductive polysilicon is filled in the cell trench with the insulating oxide layer; a first-conductivity-type source region is disposed in the second-conductivity-type base region, the first-conductivity-type source region is in contact with the outer sidewall of the cell trench, and the second-conductivity-type base region and the first-conductivity-type source region are in ohmic contact with an emitter metal layer above the first-conductivity-type epitaxial layer.

[0012] A second-conductivity-type implanted region is further disposed in the second-conductivity-type base region, the second-conductivity-type implanted region has a doping concentration greater than that of the second-conductivity-type base region, and the second-conductivity-type implanted region is in ohmic contact with the emitter metal layer.

[0013] The back electrode structure comprises a second-conductivity-type collector region disposed on the back surface of the first-conductivity-type substrate and a collector metal layer disposed on the second-conductivity-type collector region, and the collector metal layer is in ohmic contact with the second-conductivity-type collector region.

[0014] A preparation method of a high-voltage reverse blocking power semiconductor device based on a super-junction structure, the preparation method comprising the following steps:

[0015] Step 1, providing a first conductive type substrate;

[0016] Step 2, preparing a first conductive type drift region and a super junction structure in the first conductive type drift region on the front surface of the substrate by an epitaxial process, wherein the corresponding height of the first conductive type column and the second conductive type column in the super junction structure is less than the thickness of the first conductive type drift region, the first conductive type drift region includes several drift base layers sequentially grown by the epitaxial process, and the drift base layers are distributed in a stack on the first conductive type substrate;

[0017] After a drift base layer is grown by epitaxy, a photolithography and trench etching process is performed on the grown drift base layer to obtain a drift base layer groove, and the drift base layer groove is filled with a second conductive type impurity to form a second conductive type drift base layer column after filling;

[0018] The drift base layer columns in each drift base layer correspond to each other, and the drift base layer columns in adjacent drift base layers contact each other, so that the second conductive type column is formed by the mutually contacting drift base layer columns when all the drift base layers are used to form the required first conductive type drift region, and the super junction structure is obtained in the formed first conductive type drift region, and the first conductive type column and the second conductive type column in the super junction structure are alternately distributed in the first conductive type drift region;

[0019] Step 3, preparing a first conductive type epitaxial layer on the above-mentioned first conductive type drift region by an epitaxial growth process, the first conductive type epitaxial layer is supported on the first conductive type drift region, and the second conductive type column in the super junction structure is in contact with the first conductive type epitaxial layer;

[0020] Step 4, preparing a cell region corresponding to the first conductive type epitaxial layer, the cell region includes a plurality of cells, and the cell region includes a second conductive type base region, the second conductive type base region is isolated from the second conductive type column in the super junction structure by the first conductive type epitaxial layer;

[0021] Step 5, preparing a required back electrode structure on the back surface of the first conductive type substrate, and the second conductive type collector region in the back electrode structure is isolated from the second conductive type column in the super junction structure by the first conductive type substrate.

[0022] In the cross section of the power semiconductor device, the cell in the cell region includes a second conductive type base region arranged in the first conductive type epitaxial layer and a cell trench arranged in the first conductive type epitaxial layer, the cell trench penetrates the second conductive type base region, the bottom of the cell trench is located below the second conductive type base region, the second conductive type base region is in contact with the outer sidewall of the cell trench, and the depth of the cell trench is less than the thickness of the first conductive type epitaxial layer.

[0023] An insulating oxide layer is arranged on the side wall and bottom wall of the cell trench, and a gate conductive polysilicon is filled in the cell trench with the insulating oxide layer; a first conductive type source region is arranged in the second conductive type base region, the first conductive type source region is in contact with the outer side wall of the cell trench, and the second conductive type base region and the first conductive type source region are in ohmic contact with the emitter metal on the first conductive type epitaxial layer.

[0024] The back electrode structure comprises a second conductive type collector region arranged on the back surface of the first conductive type substrate and a collector metal layer arranged on the second conductive type collector region, and the collector metal layer is in ohmic contact with the second conductive type collector region.

[0025] The material of the substrate comprises silicon, and the depth of the cell trench is 5-6 μm.

[0026] Among the two of the first conductive type and the second conductive type, for an N-type power semiconductor device, the first conductive type refers to N-type, and the second conductive type refers to P-type; for a P-type power semiconductor device, the types referred to by the first conductive type and the second conductive type are just opposite to those of the N-type power semiconductor device.

[0027] The advantages of the present application are as follows: in the preparation of the first conductive type drift region and the super-junction structure, the drift base layer in the first conductive type drift region can be prepared by an epitaxial process; in the preparation of the super-junction structure, the second conductive type column and the first conductive type column alternately distributed with the second conductive type column can be finally formed by etching and filling processes; in the preparation of the first conductive type drift region and the super-junction structure in the first conductive type drift region, the high-aspect-ratio etching and filling difficulty can be reduced while achieving compatibility with the existing process, a relatively thin first conductive type drift region with a relatively low doping concentration can be obtained, thereby the demand for high withstand voltage can be met, and the present application is especially suitable for high-voltage IGBT devices of 1200 V or above; the high-doped and thinner first conductive type drift region can sharply reduce the on-state voltage drop of the entire power semiconductor device, reduce the on-state loss, and be beneficial to the improvement of the device performance.

[0028] In the forward withstand voltage, the first conductive type epitaxial layer and the second conductive type base region form a PN junction depletion layer and expand to the first conductive type drift region, and due to the high potential of the first conductive type drift region, the first conductive type column and the second conductive type column are mutually depleted, and the electric field of the first conductive type drift region expands to the back surface region; in the reverse withstand voltage, the first conductive type substrate and the second conductive type collector region form a PN junction depletion layer, and in the same way, the middle super-junction structure is mutually depleted, and the electric field reaches the front surface region; no matter in the forward or reverse direction, the mutual depletion can be achieved, thereby the bidirectional withstand voltage is realized. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a sectional view of the power semiconductor device of the present application.

[0030] Figures 2 to 8 is a sectional view of the specific implementation process step of the present application, wherein

[0031] Figure 2 is a sectional view of the N-type substrate of the present application.

[0032] Figure 3 is a sectional view of the present application after the first drift base layer is prepared.

[0033] Figure 4 is a sectional view of the present application after the drift base layer groove is etched from the first drift base layer.

[0034] Figure 5 is a sectional view of the present application after the first drift base layer column is filled in the first drift base layer.

[0035] Figure 6 is a sectional view of the present application after the second drift base layer and the second drift base layer column filled in the second drift base layer are prepared.

[0036] Figure 7 is a sectional view of the present application after the epitaxial layer is prepared.

[0037] Figure 8 is a sectional view of the present application after the back electrode structure is prepared.

[0038] BRIEF DESCRIPTION OF DRAWINGS 1 - gate conductive polysilicon, 2 - insulating oxide layer, 3 - second drift base layer column, 4 - first drift base layer column, 5 - P-type injection region, 6 - N+ source region, 7 - emitter metal, 8 - N column, 9 - collector metal layer, 10 - N-type epitaxial layer, 11 - P-type base region, 12 - N-type substrate, 13 - P+ collector region, 14 - first drift base layer, 15 - first drift base layer groove, and 16 - second drift base layer. DETAILED DESCRIPTION

[0039] The present application will be further described below in conjunction with specific drawings and examples.

[0040] As shown in Figure 1 and Figure 8 : In order to effectively achieve high voltage resistance while reducing on-state voltage drop, taking an N-type power semiconductor device as an example, the present application comprises a semiconductor substrate with N conduction type, a cell region prepared in the center region of the semiconductor substrate, and a back electrode structure prepared on the back surface of the semiconductor substrate; the semiconductor substrate comprises an N-type substrate 12, an N-type drift region arranged on the front surface of the N-type substrate 12, and an N-type epitaxial layer 10 arranged on the N-type drift region in epitaxy;

[0041] The super junction structure is arranged in the N-type drift region, the N columns 8 and the P columns in the super junction structure have a height less than the thickness of the N-type drift region, the cells in the cell region correspond to the N-type epitaxial layer 10, the P columns in the super junction structure are isolated from the P-type base region 11 in the cell region through the N-type epitaxial layer 10, and the P columns in the super junction structure are isolated from the P+ collector region 13 in the back electrode structure through the N-type substrate 12, and the P+ collector region 13 is adjacent to the N-type substrate 12.

[0042] Specifically, the semiconductor substrate has an N conductive type, the cell region can be prepared in the central region of the semiconductor substrate through a semiconductor process commonly used in the technical field, and the function and specific preparation process of the cell region can be selected according to actual needs, and the actual needs are used as the criterion. Generally, a terminal region can also be arranged at the outer ring of the cell region, and the terminal region is used to protect the cell region. The protection principle of the terminal region to the cell region can be consistent with the prior art, and details are not described herein.

[0043] In the embodiment of the application, the semiconductor substrate includes an N-type substrate 12, an N-type drift region and an N-type epitaxial layer 10, wherein the N-type drift region is arranged on the N-type substrate 12, and the N-type epitaxial layer 10 is arranged on the N-type drift region, that is, the conductive types of the N-type substrate 12, the N-type drift region and the N-type epitaxial layer 10 are all N-type, and the N-type epitaxial layer 10 is arranged on the N-type drift region through an epitaxial process, that is, the N-type drift region is located between the N-type substrate 12 and the N-type epitaxial layer 10, and the N-type drift region is in contact with the N-type substrate 12 and the N-type epitaxial layer 10.

[0044] In the specific implementation, the super junction structure is arranged in the N-type drift region. As known by those skilled in the art, the super junction structure in the N-type drift region includes a plurality of alternately distributed N columns 8 and P columns, the heights of the N columns 8 and the P columns in the super junction structure are less than the thickness of the N-type drift region, and the super junction structure can adopt a form commonly used in the prior art, and details are not described herein. The cells in the cell region correspond to the N-type epitaxial layer 10. Generally, at least one P-type base region 11 needs to be arranged in the cell region, the P-type base region 11 is located in the N-type epitaxial layer 10, the depth of the P-type base region 11 in the N-type epitaxial layer 10 is less than the thickness of the N-type epitaxial layer 10, so that the P columns in the super junction structure are isolated from the P-type base region 11 through the N-type epitaxial layer 10, and in addition, the P columns in the super junction structure are isolated from the P+ collector region 13 through the N-type substrate 12. In the embodiment of the application, after the super junction structure is arranged in the N-type drift region, a transverse electric field can be introduced in the N-type drift region during work, and through the introduced transverse electric field, the electric field can be changed from a triangular distribution to a trapezoidal distribution, the breakdown voltage is improved, the thickness of the N-type drift region can be reduced, and the resistivity of the N-type drift region can also be reduced under the condition of a lower thickness of the N-type drift region, that is, the on-state voltage drop can be reduced while the high withstand voltage is effectively realized.

[0045] In the implementation, the reverse blocking specifically refers to that the power semiconductor device has bidirectional voltage resistance, i.e., the power semiconductor device has PN junctions on the front surface and the back surface; in the embodiment of the application, the P-type base region 11 and the N-type epitaxial layer 10 form a PN junction for front surface voltage resistance, and the P+ collector region 13 and the N-type N-type substrate 12 form a PN junction for back surface voltage resistance. In order to meet the voltage resistance requirement, the resistivity of the N-type epitaxial layer 10 and the N-type substrate 12 can be set to 20 ohm*cm-40 ohm*cm.

[0046] Further, the N-type drift region includes a plurality of drift base layers sequentially grown by an epitaxial process, and the drift base layers are stacked on the N-type substrate 12.

[0047] After the epitaxial growth of a drift base layer, the drift base layer is etched to obtain a drift base layer groove, and the drift base layer groove is filled with P-type impurities to form a P-type drift base layer column after the filling.

[0048] The drift base layer columns in each drift base layer correspond to each other, and the drift base layer columns in adjacent drift base layers contact each other, so that the P columns are formed by the drift base layer columns contacting each other when all the drift base layers are used to form the required N-type drift region, and the N columns 8 are formed in the N-type drift region, i.e., the N columns 8 and the P columns are alternately distributed in the N-type drift region.

[0049] In the embodiment of the application, in order to adapt to the voltage resistance requirement in the high-voltage field, the N-type drift region includes a plurality of drift base layers sequentially grown by an epitaxial process, and the plurality of drift base layers are stacked above the N-type substrate 12, i.e., each drift base layer is prepared by an epitaxial process, and the drift base layers prepared by the sequential epitaxial process can finally form the N-type drift region. In the implementation, the number of drift base layers in the N-type drift region is related to the voltage resistance requirement of the power semiconductor device, for example, when the voltage resistance of the power semiconductor device is 1200V, at least two drift base layers are generally required in the N-type drift region, and the specific number is subject to the actual voltage resistance requirement, which will not be described herein.

[0050] In order to form a super-junction structure in the N-type drift region, after the epitaxial growth of a drift base layer, the drift base layer is etched to obtain a plurality of drift base layer grooves, and the drift base layer grooves are filled with P-type impurities, and the P-type impurities filled in the drift base layer grooves can form drift base layer columns. In all the drift base layers of the N-type drift region, the drift base layer columns correspond to each other, and the drift base layer columns in adjacent drift base layers contact each other, so that the P columns are formed by the drift base layer columns contacting each other when all the drift base layers are used to form the required N-type drift region, and the N-type drift region between adjacent P columns forms the N columns 8, i.e., the N columns 8 and the P columns are alternately distributed in the N-type drift region.

[0051] Figure 1 and Figure 8 In the specific implementation case shown in the figure, the N-type drift region is provided with two drift base layers, a plurality of first drift base layer columns 4 are provided in the drift base layer supported on the N-type substrate 12, and a plurality of second drift base layer columns 3 are provided in the drift base layer adjacent to the N-type epitaxial layer 10. The first drift base layer columns 4 correspond to the second drift base layer columns 3 one by one, and the first drift base layer columns 4 and the second drift base layer columns 3 are adjacent to each other. A P column can be formed by using the adjacent first drift base layer columns 4 and the second drift base layer columns 3. The P columns formed by using a plurality of first drift base layer columns 4 and second drift base layer columns 3 can obtain the N columns 8 and the P columns alternately distributed in the N-type drift region.

[0052] In summary, the drift base layer is prepared by the epitaxial process, and the drift base layer column is obtained by the trench etching and filling process. When the super junction structure is formed by using the drift base layer columns that are opposite and in contact, the etching and filling difficulty of the high aspect ratio trench can be effectively reduced. When the N-type drift region with a relatively thin and low resistivity is prepared, the N-type drift region can be compatible with the existing process. The resistivity of the N-type drift region can be adjusted according to actual needs, and the specific resistivity is subject to the actual application.

[0053] In the specific implementation, the doping concentration of the drift base layer is not higher than the doping concentration of the N-type substrate 12. When the voltage is withstood, the charge amount of the N column and the P column of the drift base layer after depletion is the same. In the embodiment of the application, the charge amount of the P column of the drift base layer after depletion is the same as the charge amount of the N column of the drift base layer. In the specific implementation, the width and the doping concentration of the P column and the N column can be adjusted to make the charge amount of the N column and the P column after depletion the same when the voltage is withstood. The specific configuration of the N column and the P column in the super junction structure after depletion can be selected as needed to make the charge amount of the N column and the P column after depletion the same. The doping concentration of the drift base layer is not higher than the doping concentration of the N-type substrate 12, that is, the doping concentration of the drift base layer is lower than or equal to the doping concentration of the N-type substrate 12. The doping concentration can be selected as needed.

[0054] Further, on the cross section of the power semiconductor device, the cells in the cell region include a P-type base region 11 provided in the N-type epitaxial layer 10 and a cell trench provided in the N-type epitaxial layer 10. The cell trench penetrates the P-type base region 11, the bottom of the cell trench is located below the P-type base region 11, the P-type base region 11 is in contact with the outer sidewall of the cell trench, and the depth of the cell trench is less than the thickness of the N-type epitaxial layer 10.

[0055] An insulating oxide layer 2 is arranged on the side wall and bottom wall of the cell trench, and the gate conductive polysilicon 1 is filled in the cell trench with the insulating oxide layer 2 arranged therein; an N+ source region 6 is arranged in the P-type base region 11, and the N+ source region 6 is in contact with the outer side wall of the cell trench, and the P-type base region 11 and the N+ source region 6 are in ohmic contact with the emitter metal 7 above the N-type epitaxial layer 10.

[0056] Figure 1 And Figure 8 In the cell trench structure, a plurality of cell trenches are arranged in the N-type epitaxial layer 10, and the depth of the cell trench is less than the thickness of the N-type epitaxial layer 10, and the depth of the cell trench is 5-6 μm. The P-type base region 11 is arranged in the N-type epitaxial layer 10, generally, the P-type base region 11 penetrates the center region of the N-type epitaxial layer 10, that is, the P-type base region 11 penetrates the entire cell region, and the P-type base region 11 generally extends vertically downward from the upper end surface of the N-type epitaxial layer 10, and the P-type base region 11 is above the bottom of the cell trench, so that the cell trench penetrates the P-type base region 11, and the P-type base region 11 is in contact with the outer side wall of the cell trench.

[0057] After the cell trench is prepared, the insulating oxide layer 2 is arranged on the side wall and bottom wall of the cell trench, the insulating oxide layer 2 is a silicon dioxide layer, and the insulating oxide layer 2 can be grown by a thermal oxidation process. The gate conductive polysilicon 1 is filled in the cell trench with the insulating oxide layer 2 grown therein, and the gate conductive polysilicon 1 is insulated and separated from the side wall and bottom wall of the cell trench by the insulating oxide layer 2.

[0058] The N+ source region 6 is arranged in the P-type base region 11, and the N+ source region 6 is in contact with the outer side wall of the cell trench, and the depth of the N+ source region 6 is much less than the depth of the P-type base region 11. In order to obtain the emitter of the power semiconductor device, the emitter metal 7 needs to be prepared above the N-type epitaxial layer 10, the emitter metal 7 is in ohmic contact with the P-type base region 11 and the N+ source region 6, and the emitter metal 7 is insulated and separated from the gate conductive polysilicon 1. Of course, when the emitter metal 7 is prepared, the gate metal is generally also prepared, the gate metal can be electrically connected with the gate conductive polysilicon 1, and the gate electrode of the power semiconductor device can be formed by using the electrical connection between the gate metal and the gate conductive polysilicon 1, which is consistent with the prior art and is well known to those skilled in the art, and thus will not be described here.

[0059] Further, the P-type implanted region 5 is also arranged in the P-type base region 11, the doping concentration of the P-type implanted region 5 is greater than that of the P-type base region 11, and the P-type implanted region 5 is in ohmic contact with the emitter metal 7.

[0060] In the embodiment of the present application, the depth of the P-type implant region 5 can be consistent with the N+ source region 6, and the doping concentration of the P-type implant region 5 is greater than the doping concentration of the P-type base region 11. For the adjacent cell trench, the P-type implant region 5 is in contact with the N+ source region 6 on both sides. When the P-type implant region 5 is arranged in the P-type base region 11, the emitter metal 7 is in ohmic contact with the P-type implant region 5, and the P-type base region 11 is electrically connected with the emitter metal 7 by the P-type implant region 5.

[0061] Of course, in the specific implementation, the cell can also take other forms, such as a planar cell, which can be selected according to actual needs to meet the specific voltage withstand requirements, and details are not described here.

[0062] Further, the back electrode structure includes a collector metal layer 9 arranged on the P+ collector region 13, and the collector metal layer 9 is in ohmic contact with the P+ collector region 13.

[0063] In the embodiment of the present application, the P+ collector region 13 is arranged on the back surface of the N-type substrate 12, and the collector metal layer 9 is arranged on the P+ collector region 13, and the collector metal layer 9 is in ohmic contact with the P+ collector region 13. The back electrode structure formed by the collector metal layer 9 and the P+ collector region 13 makes the power semiconductor device form an IGBT device.

[0064] When the formed power semiconductor device is an IGBT device, the P pillars in the super junction structure are isolated from the P+ collector region 13 by the N-type substrate 12. When the IGBT device is working: in forward voltage resistance, the space charge region starts to expand outward from the PN junction formed by the P-type base region 11 and the N-type epitaxial layer 10 on the front surface, and the N-type impurities in the N pillars 8 can be compensated with the P-type impurities in the P pillars, thereby exhibiting electrically neutral characteristics, so that the longitudinal electric field is in a trapezoidal distribution, thereby improving the breakdown voltage; in reverse voltage resistance, the space charge region starts to expand outward from the PN junction formed by the N-type substrate 12 and the P+ collector region 13, and the N-type impurities in the N pillars 8 can be depleted with the P pillars to form a voltage resistance layer, thereby enabling the formed IGBT device to have bidirectional voltage resistance capability.

[0065] As shown in Figures 2 to 8 The high-voltage reverse blocking power semiconductor device based on the super junction structure can be prepared by the following process. Specifically, the preparation method includes the following steps:

[0066] Step 1, providing an N-type substrate 12 of N conductivity type;

[0067] As shown in Figure 2As shown, the N-type substrate 12 can be of a commonly used form, such as a silicon substrate. The thickness and resistivity of the N-type substrate 12 can be selected according to actual needs, which are well known to those skilled in the art and will not be described in detail here.

[0068] Step 2: An N-type drift region and a superjunction structure within the N-type drift region are prepared on the front side of the N-type substrate 12 by epitaxial process. The heights of the N-pillars 8 and P-pillars in the superjunction structure are both less than the thickness of the N-type drift region. The N-type drift region includes several drift base layers that are sequentially grown by epitaxial process. The drift base layers are stacked on the N-type substrate 12.

[0069] After an epitaxial growth is obtained to form a drift base layer, the grown drift base layer is subjected to photolithography and trench etching processes to obtain drift base layer trenches. P-type impurities are filled into the drift base layer trenches to form P-conductive drift base layer pillars after filling.

[0070] Each drift base layer has a corresponding drift base column, and the drift base columns in adjacent drift base layers are in contact with each other. When all drift base layers are used to form the required N-type drift region, P columns are formed through the contacting drift base columns to obtain a superjunction structure in the formed N-type drift region. N columns 8 and P columns are alternately distributed in the N-type drift region within the superjunction structure.

[0071] Specifically, the prepared N-type drift region and superjunction structure can be described in the above description. The following is a detailed explanation of the specific process, taking the N-type drift region containing two drift base layers as an example.

[0072] like Figure 3 The diagram shows a first drift base layer 14 fabricated on the front side of an N-type substrate 12 using an epitaxial process. The thickness and resistivity of the first drift base layer 14 can be selected according to actual needs, and the resistivity of the first drift base layer 14 is not higher than that of the N-type substrate 12.

[0073] like Figure 4 As shown, after the first drift base layer 14 is prepared, the first drift base layer 14 is selectively masked and etched so that a first drift base layer groove 15 can be etched in the first drift base layer 14. The depth of the first drift base layer groove 15 is less than the thickness of the first drift base layer 14. The specific etching process and conditions for obtaining the first drift base layer groove 15 are consistent with the existing methods and are well known to those skilled in the art, and will not be described in detail here. Figure 4The specific case of the existence of a first drift base layer groove 15 in the first drift base layer 14 is shown, but in the actual process, a plurality of first drift base layer grooves 15 are provided in the first drift base layer 14, all of the first drift base layer grooves 15 are the same process step layer, and the distance between adjacent first drift base layer grooves 15 can be set to be the same.

[0074] As shown in Figure 5 After the first drift base layer groove 15 is obtained, filling of P-type impurities is performed to obtain the first drift base layer column 4. In specific implementation, a sacrificial oxide layer can be grown on the first drift base layer 14, and then etched and removed, and then an epitaxial filling process is performed, and after filling, etching and CMP processes are performed to form the first drift base layer column 4 filling the first drift base layer groove 15.

[0075] After the first drift base layer column 4 is prepared in the first drift base layer 14, the second drift base layer 16 is prepared on the first drift base layer 14 using an epitaxial process, and the thickness and resistivity of the second drift base layer 16 can be the same as those of the first drift base layer 14. The process conditions and processes for epitaxially growing the second drift base layer 16 can be consistent with the existing ones.

[0076] After the second drift base layer 16 is prepared, the second drift base layer 16 is etched using the above process to obtain a second drift base layer groove that penetrates the second drift base layer 16. The second drift base layer groove in the second drift base layer 16 corresponds to the first drift base layer groove 15 in the first drift base layer 14, that is, the same photomask can be used for etching the first drift base layer 14 and the second drift base layer 16. The specific way of etching the second drift base layer 16 to obtain the second drift base layer groove is well known to those skilled in the art, and will not be described here.

[0077] After the second drift base layer groove is prepared in the second drift base layer 16, the second drift base layer column 3 is obtained using the filling process described above. After the second drift base layer column 3 is filled, the lower end of the second drift base layer column 3 is in contact with the upper end of the first drift base layer column 4, as shown in Figure 6 .

[0078] When the N-type drift region is composed of the first drift base layer 14 and the second drift base layer 16, the P column can be formed by the first drift base layer column 4 and the second drift base layer column 3 in contact with each other, and the region between adjacent P columns forms the N column 8. The specific implementation is consistent with the existing one, and will not be described here.

[0079] When the number of drift base layers in the N-type drift region is more than two, the process of the second drift base layer 16 can be referred to to obtain a plurality of drift base layers stacked and distributed, and the height of the P-pillar formed in the N-type drift region is different when the number of drift base layers is different, which is well known to those skilled in the art and will not be described here.

[0080] Step 3, preparing an N-type epitaxial layer 10 on the N-type drift region by an epitaxial growth process, the N-type epitaxial layer 10 is supported on the N-type drift region, and the P-pillar in the super junction structure is in contact with the N-type epitaxial layer 10;

[0081] Specifically, after the N-type drift region is prepared, the N-type epitaxial layer 10 is prepared by using the epitaxial process commonly used in the technical field, and the N-type epitaxial layer 10 is supported on the N-type drift region, as shown in Figure 7 Generally, the doping concentration of the N-type epitaxial layer 10 is consistent with the doping concentration of the N-type substrate 12, and the process conditions and processes for preparing the N-type epitaxial layer 10 can be consistent with the existing ones, which are well known to those skilled in the art and will not be described here.

[0082] Step 4, preparing a cell region corresponding to the N-type epitaxial layer 10, the cell region including a plurality of cells, and the cell region including a P-type base region 11, the P-type base region 11 being isolated from the P-pillar in the super junction structure by the N-type epitaxial layer 10;

[0083] Specifically, after the N-type epitaxial layer 10 is prepared, the required cells are prepared by using the technical means commonly used in the technical field, that is, the cell region is obtained, and the specific structural form of the cells in the cell region can refer to the specific implementation of Figure 1 and Figure 8 Of course, the cells can also adopt other forms, and the structure of the cells is different, and the corresponding preparation process is different, which can be selected according to actual needs, so as to obtain the required cells and cell regions. Here, it will not be described here.

[0084] Step 5, preparing a required back electrode structure on the back surface of the N-type substrate 12, and the P+ collector region 13 in the back electrode structure being isolated from the P-pillar in the super junction structure by the N-type substrate 12.

[0085] Specifically, when the cell region and the corresponding front structure are prepared, the back electrode structure needs to be prepared on the back surface of the N-type substrate 12, and the specific case of the back electrode structure can refer to the above description Figure 1 , Figure 8 and the above description, which is well known to those skilled in the art and will not be described here.

[0086] In summary, in the preparation of the N-type drift region, the drift base layer in the N-type drift region can be prepared by an epitaxy process; in the preparation of the super-junction structure, the P columns and the N columns 8 alternately distributed with the P columns can be finally formed by etching and filling processes, in the preparation of the N-type drift region and the super-junction structure in the N-type drift region, the etching and filling difficulty of high aspect ratio can be reduced, a thinner N-type drift region with a lower doping concentration can be obtained, so that the demand for high withstand voltage can be met, and the high-voltage IGBT device of 1200V or more is especially suitable. The high-doped and thinner N-type drift region sharply reduces the on-state voltage drop of the entire power semiconductor device, reduces the on-state loss, and is beneficial to the improvement of the device performance.

[0087] In the forward withstand voltage, the N-type epitaxial layer 10 and the P-type base region 11 form a PN junction depletion layer and expand to the N-type drift region. Since the N-type drift region has a high potential, the N columns 8 and the P columns in the N-type drift region are mutually depleted, and the electric field of the N-type drift region expands to the back region. In the reverse withstand voltage, the N-type substrate 12 and the P+ collector region 13 form a PN junction depletion layer, which is mutually depleted in the same way to the middle super-junction structure, and the electric field reaches the front region. In both the forward and reverse directions, the PN junctions can be mutually depleted, thereby realizing the bidirectional withstand voltage.

[0088] As can be seen from the above description, the present process is compatible with the existing process, that is, the difficulty of deep trench etching and filling of high-voltage super-junction high aspect ratio can be reduced, the on-state voltage drop and static loss can be reduced while realizing high withstand voltage, and bidirectional withstand voltage can be realized due to the forward and reverse withstand voltage PN junctions, which is suitable for reverse blocking IGBT structure.

Claims

1. A high voltage reverse blocking power semiconductor device based on super junction structure, comprising a semiconductor substrate with a first conductivity type, a cell region prepared in a central region of the semiconductor substrate, and a back electrode structure prepared in a back surface of the semiconductor substrate; characterized in that: The semiconductor substrate comprises a first conductive type substrate, a first conductive type drift region arranged on the front surface of the first conductive type substrate, and a first conductive type epitaxial layer arranged on the first conductive type drift region in an epitaxial manner; The super-junction structure is arranged in the first conductive type drift region, the first conductive type column and the second conductive type column in the super-junction structure have a height less than the thickness of the first conductive type drift region, the cells in the cell region correspond to the first conductive type epitaxial layer, the second conductive type column in the super-junction structure is isolated from the second conductive type base region in the cell region through the first conductive type epitaxial layer, and the second conductive type column in the super-junction structure is isolated from the second conductive type collector region in the back electrode structure through the first conductive type substrate, the second conductive type collector region is adjacent to the first conductive type substrate; The first conductive type drift region comprises a plurality of drift base layers sequentially grown through an epitaxial process, and the drift base layers are distributed in a stacked manner on the first conductive type substrate; After a drift base layer is grown in an epitaxial manner, the grown drift base layer is etched to obtain a drift base layer groove, and the drift base layer groove is filled with second conductive type impurities to form a second conductive type drift base column after filling; The drift base columns in each drift base layer correspond to each other, and the drift base columns in adjacent drift base layers are in contact with each other, so that the second conductive type column is formed through the drift base columns in contact with each other when all the drift base layers are used to form the required first conductive type drift region, and the super-junction structure is obtained in the formed first conductive type drift region, and the first conductive type column and the second conductive type column in the super-junction structure are alternately distributed in the first conductive type drift region; During voltage resistance, the first conductive type column and the second conductive type column of the drift base column have the same amount of charge after mutual depletion; During forward voltage resistance, the space charge region starts to expand outward from the PN junction formed by the second conductive type base region on the front surface and the first conductive type epitaxial layer, the first conductive type impurities in the first conductive type column and the second conductive type impurities in the second conductive type column are mutually compensated, and then exhibit electrically neutral characteristics, so that the longitudinal electric field is in a trapezoidal distribution, thereby improving the breakdown voltage; during reverse voltage resistance, the second conductive type column is isolated from the second conductive type collector region through the first conductive type substrate and the first conductive type drift region, the space charge region starts to expand outward from the PN junction formed by the first conductive type substrate and the second conductive type collector region, the first conductive type impurities in the first conductive type column can be depleted with the second conductive type column to form a voltage resistance layer, thereby enabling the formed power semiconductor device to have bidirectional voltage resistance capability.

2. The super junction structure based high voltage cascode power semiconductor device of claim 1, wherein: In the cross section of the power semiconductor device, the cells in the cell region comprise a second conductive type base region arranged in the first conductive type epitaxial layer and a cell trench arranged in the first conductive type epitaxial layer, the cell trench penetrates the second conductive type base region, the bottom of the cell trench is located below the second conductive type base region, the second conductive type base region is in contact with the outer sidewall of the cell trench, and the depth of the cell trench is less than the thickness of the first conductive type epitaxial layer. An insulating oxide layer is arranged on the side wall and bottom wall of the cell trench, and a gate conductive polysilicon is filled in the cell trench with the insulating oxide layer; A first conductive type source region is arranged in the second conductive type base region, the first conductive type source region is in contact with the outer side wall of the cell trench, and the second conductive type base region and the first conductive type source region are in ohmic contact with the emitter metal above the first conductive type epitaxial layer.

3. The super junction structure based high voltage cascode power semiconductor device of claim 2, wherein: A second conductive type injection region is also arranged in the second conductive type base region, the doping concentration of the second conductive type injection region is greater than that of the second conductive type base region, and the second conductive type injection region is in ohmic contact with the emitter metal.

4. The super junction based high voltage cascode power semiconductor device of claim 1, wherein: The back electrode structure includes a collector metal layer arranged on the second conductive type collector region, and the collector metal layer is in ohmic contact with the second conductive type collector region.

5. A method for manufacturing a high-voltage reverse blocking power semiconductor device based on a super junction structure, characterized by the steps of: The high-voltage reverse blocking power semiconductor device of claim 1 is prepared by the following steps: ​ Step 1, providing a first conductive type substrate; Step 2, preparing a first conductive type drift region and a super junction structure in the first conductive type drift region on the front surface of the substrate by epitaxial process, wherein the corresponding heights of the first conductive type columns and the second conductive type columns in the super junction structure are less than the thickness of the first conductive type drift region, and the first conductive type drift region includes a plurality of drift base layers sequentially grown by epitaxial process, and the drift base layers are stacked on the first conductive type substrate; After a drift base layer is epitaxially grown, a photolithography and trench etching process is performed on the grown drift base layer to obtain a drift base layer groove, and the drift base layer groove is filled with second conductive type impurities to form a second conductive type drift base column after filling; The drift base columns in each drift base layer correspond to each other, and the drift base columns in adjacent drift base layers contact each other, so that the second conductive type columns are formed by the mutually contacting drift base columns when all the drift base layers are used to form the required first conductive type drift region, and the super junction structure is obtained in the formed first conductive type drift region, and the first conductive type columns and the second conductive type columns in the super junction structure are alternately distributed in the first conductive type drift region; Step 3, preparing a first conductive type epitaxial layer on the above-mentioned first conductive type drift region by epitaxial growth process, the first conductive type epitaxial layer is supported on the first conductive type drift region, and the second conductive type columns in the super junction structure are in contact with the first conductive type epitaxial layer; Step 4, preparing a cell region corresponding to the first conductive type epitaxial layer, the cell region includes a plurality of cells, and the cell region includes a second conductive type base region, and the second conductive type base region is isolated from the second conductive type columns in the super junction structure by the first conductive type epitaxial layer; Step 5, preparing a required back electrode structure on the back surface of the first conductive type substrate, and the second conductive type collector region in the back electrode structure is isolated from the second conductive type columns in the super junction structure by the first conductive type substrate.

6. The method of claim 5, wherein the method further comprises: On a cross section of the power semiconductor device, the cells in the cell region include a second-conductivity-type base region disposed in the first-conductivity-type epitaxial layer and a cell trench disposed in the first-conductivity-type epitaxial layer, the cell trench penetrating through the second-conductivity-type base region, a bottom of the cell trench being below the second-conductivity-type base region, the second-conductivity-type base region being in contact with an outer sidewall of the cell trench, and a depth of the cell trench being less than a thickness of the first-conductivity-type epitaxial layer; An insulating oxide layer is disposed on the sidewall and the bottom wall of the cell trench, and a gate conductive polysilicon is filled in the cell trench with the insulating oxide layer; A first-conductivity-type source region is disposed in the second-conductivity-type base region, the first-conductivity-type source region being in contact with the outer sidewall of the cell trench, and the second-conductivity-type base region and the first-conductivity-type source region being in ohmic contact with an emitter metal on the first-conductivity-type epitaxial layer.

7. The method of claim 5 or 6, wherein the method further comprises: The back electrode structure includes a second-conductivity-type collector region disposed on a back surface of the first-conductivity-type substrate and a collector metal layer disposed on the second-conductivity-type collector region, the collector metal layer being in ohmic contact with the second-conductivity-type collector region.

8. The method of claim 6, wherein the method further comprises: The material of the substrate includes silicon, and the depth of the cell trench is 5-6 μm.

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