Improved backside contact structure for semiconductor devices and corresponding manufacturing process

Abstract

Embodiments of the present disclosure relate to improved backside contact structures for semiconductor devices and corresponding manufacturing processes. Various embodiments provide a vertical conduction semiconductor device comprising: a silicon substrate having a front side and a back side; a front side structure disposed on the front side of the substrate having at least one current conduction region at the front side; and a backside metal structure disposed on the back side of the substrate in electrical contact with the substrate and comprised of a stack of metal layers. The backside metal structure is formed from: a first metal layer; a silicide region between the back side of the substrate and the first metal layer in electrical contact with the back side; and a second metal layer disposed on the first metal layer.

Description

Technical Field

[0001] This solution relates to an improved back-side contact structure for semiconductor devices and the corresponding manufacturing process. Background Technology

[0002] Several vertically conductive semiconductor devices, particularly silicon-based devices for power applications, have contacts or metallization on the back side or rear side; for example, MOSFET (metal-oxide-semiconductor field-effect transistor) devices of the VDMOS (vertical double-diffused metal-oxide-semiconductor) type or IGBT (insulated-gate bipolar transistor) type transistor devices are known, wherein current flows vertically in the device to electrical contacts on the back side.

[0003] In this respect, as an example only, Figure 1 A cross-sectional view shows an IGBT (Insulated Gate Bipolar Transistor) transistor device 1 with a planar structure, comprising a wafer 1', the wafer 1' including, for example, having a P + The substrate 2 is a doped silicon substrate and has a front side 2a and a back side 2b.

[0004] N + A buffer layer 4 of type silicon is formed on the front side 2a of substrate 2, N － A p-type doped silicon drift layer 6 is formed on and in contact with the buffer layer 4. The drift layer 6 houses a body region 8 at its top surface 6a, which extends in depth from the top surface 6a and is formed by implanting p-type dopant. Within the body region 8, an N-type dopant material is implanted to form a source region 10, thereby forming an N-type dopant extending from the top surface 6a within the body region 8. + Doped regions.

[0005] The IGBT transistor device 1 also includes a front metal layer 12 formed on the top surface 6a of the drift layer 6, which is in direct contact with the body region 8 and partially in direct contact with the source region 10. The front metal layer 12, which functions as the emitter contact of the IGBT transistor device 1, is separated from the outer portion (outer in the top view) of the body region 8 by a superposition of insulating material 14 and conductive material 16, such that the conductive layer 16, for example, of polysilicon, is electrically insulated from the top surface 6a and the front metal layer 12 by a corresponding insulating material layer 14, thereby forming the gate structure 18 of the IGBT transistor device 1.

[0006] Specifically, a rear metal structure 19 is formed on the rear side 2b of the substrate 2, which is in direct electrical contact with the substrate 2, thus constituting the collector contact of the IGBT transistor device 1.

[0007] A common solution for providing the back metal structure of a vertically conductive semiconductor device envisions a stack of three or four metal layers, typically obtained sequentially via PVD (physical vapor deposition) techniques, such as sputtering, without vacuum interruption.

[0008] Specifically: a first metal layer, such as aluminum (Al), arranged to be in direct contact with the silicon substrate, ensures electrical contact with the same substrate; a second metal layer, such as titanium (Ti), overlapping the first layer, constitutes a barrier layer to prevent diffusion; a third metal layer, such as nickel-vanadium (NiV), overlapping the second layer, constitutes an active bonding layer for coupling, for example, to a support (e.g., a so-called lead frame) of the package in which the semiconductor device is packaged; and a fourth metal layer, such as silver (Ag), overlapping the third layer, serves to prevent oxidation.

[0009] Recent applications of silicon-based semiconductor devices for power use, particularly in the automotive and other industrial sectors, have enabled wafers to be thinner, for example, down to 40 μm, and increased the total thickness of the metal stack on the back side of the same wafer.

[0010] The problem with backside metal stacking is the high bending caused on the wafer, especially in the case of thin wafers (<100μm), which leads to handling problems in the final manufacturing steps and reliability issues of the resulting devices, as well as possible failures or reduced yield.

[0011] Furthermore, for some devices, establishing good electrical contact involves expensive and unproductive methods to limit the temperature reached by the wafer in each deposition step involved in the formation of the back-side metal stack.

[0012] For example, if electrical contact with the substrate is achieved through an aluminum layer, the so-called spike process caused by the diffusion of silicon in aluminum plays an important role, thereby creating voids in the silicon surface that are rapidly filled by aluminum, and specifically through the distribution and density of “spikes” generated on the back surface of the wafer; this process utilizes high temperatures, which are subsequently caused by back-side metallization to induce high stress on the wafer, for example, with a value of about 180 MPa.

[0013] The solution to reduce the aforementioned prominent problems to date has been to limit the thermal stress caused by the deposition (e.g., sputtering) process by employing a multi-step deposition technique with repeated and alternating deposition and cooling steps until the desired total stack thickness (e.g., depending on packaging requirements) is achieved.

[0014] However, the applicant has found that the currently used solution has some limitations and drawbacks, particularly due to the reduction (even to a considerable extent) in production efficiency and the inadequate management of stress caused by metal stacking. Summary of the Invention

[0015] The various embodiments disclosed herein overcome the shortcomings of previous solutions by providing an improved solution that represents a good trade-off between stress management caused by back-side metal stacking and the electrical characteristics of the semiconductor device, especially considering the need to reduce wafer thickness and increase the total thickness of back-side metallization while ensuring good electrical contact with the substrate.

[0016] According to this solution, a semiconductor device and a corresponding manufacturing process are provided. Attached Figure Description

[0017] To better understand this solution, embodiments thereof will now be described only by way of non-limiting examples and with reference to the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic cross-sectional view of an IGBT transistor;

[0019] Figure 2A -2B is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present solution in successive steps of the corresponding manufacturing process;

[0020] Figure 3 yes Figure 2A and 2B An enlarged cross-sectional view of a portion of a semiconductor device; and

[0021] Figure 4A , Figure 4B , Figure 4C and Figure 4D It is about Figure 3 The diagram illustrates a portion of the contents of a semiconductor device, with each element shown in the diagram. Detailed Implementation

[0022] As will be described in detail below, one aspect of this solution envisions alternative embodiments of a back-side metal structure (or stack) on the back side of a substrate or wafer of a semiconductor device, particularly a silicon-based semiconductor device, such as a device for power applications.

[0023] This alternative embodiment envisions only two metal layers overlapping on the aforementioned rear side of the substrate.

[0024] Specifically, in this case, the first metal layer in contact with the substrate itself constitutes an active bonding layer and is formed through deposition techniques and processes (especially PVD) to ensure the simultaneous formation of a silicide region, which is a binary compound formed from metal and silicon atoms, in direct contact with the substrate. This silicide region ensures good electrical contact with the substrate and also ensures good mechanical strength.

[0025] Therefore, in this solution, only one second metal layer on the first metal layer is sufficient. This second metal layer has the function of preventing oxidation and, together with the first metal layer, forms the required thickness for packaging semiconductor devices (the thickness of the first and second metal layers is selected according to the application of the semiconductor device).

[0026] First refer to Figure 2A The process for manufacturing a rear metal structure according to an embodiment of the present solution is now disclosed.

[0027] In Figure 2A In this context, silicon-based semiconductor devices, such as power devices (e.g., IGBTs or VDMOS devices), are represented by 20.

[0028] The aforementioned semiconductor device 20 includes a silicon wafer 21 having a substrate 22 having a front side 22a and a rear side 22b (it should be noted that the wafer 21 has been flipped to perform appropriate machining operations on the rear side).

[0029] In a manner not described in detail herein, the front structure of semiconductor device 20 (represented by 24 in general) has been pre-formed on the front side 22a of substrate 22 using known techniques.

[0030] Obviously, the front structure 24 can have a wide range of configurations, and in any case includes at least one current-conducting region at the corresponding front surface 24a.

[0031] For example, in the case of an IGBT-type semiconductor device 20, the front structure 24 includes, starting from the same substrate 22, a portion in the vertical direction (see also [reference]). Figure 1 The structure consists of a buffer layer, a drift layer (within which the body region and source region are formed, defining the aforementioned current conduction region), a gate structure, and a front metal layer.

[0032] The process then envisions machining the back side of the wafer 21 using, for example, PVD technology, particularly forming a first metal layer 26 on the back side 22b of the substrate 22.

[0033] In one embodiment, the aforementioned first metal layer 26 is a nickel-vanadium (NiV) layer, with a variable concentration of vanadium ranging from 5 wt% to 8 wt%.

[0034] In a possible embodiment, the first metal layer 26 may have a thickness, for example, between 300 nm and 700 nm, formed by sputtering techniques, for example using argon (Ar) and nitrogen (N2) as processing gases in the deposition chamber.

[0035] According to one aspect of this scheme, the deposition is appropriately adjusted to achieve an in-situ temperature, thereby triggering a silicide formation reaction process on the substrate 22, during the same deposition step of the first metal layer 26, forming a silicide region 27, particularly nickel silicide, between the back side 22b of the substrate 22 and the aforementioned first metal layer 26. For example, the temperature of the deposition chamber is controlled to be above 400°C, for example, to be maintained in the range between 400°C and 500°C during deposition.

[0036] Therefore, the silicide region 27 that is in contact with the first metal layer 26 is configured to be in electrical contact with the rear side 22b of the substrate 22.

[0037] Furthermore, the thickness of the silicide region 27 is less than the thickness of the first metal layer 26 and the second metal layer 28.

[0038] Next, as Figure 2B As shown, for example, a second metal layer 28 is formed again using PVD technology, which overlaps with the first metal layer 26.

[0039] The second metal layer 28 may have a thickness between 150 nm and 500 nm, for example, a silver (Ag) layer.

[0040] The first metal layer 26 (with a corresponding silicide region 27) and the second metal layer 28 stacked on top of each other form the rear metal structure of the semiconductor device 20 in this case, which is generally indicated by 30. The rear metal structure 30 is in electrical contact with the substrate 22, and in particular with at least one current-conducting region disposed at the rear side 22b of the substrate 22 (the current conduction path is defined as a current conduction path through the substrate 22 in the vertical direction between the current-conducting region disposed at the front side 24a of the front structure 24 and the current-conducting region disposed at the rear side 22b of the substrate 22).

[0041] In other words, in this case, the rear metal structure 30 is formed only by the first metal layer 26 and the second metal layer 28, wherein the silicide region 27 is placed between the substrate 22 and the first metal layer 26.

[0042] For more details, please refer to Figure 3 (It shows an enlarged image of a cross-sectional view of a portion of wafer 21) and Figure 4A - A diagram of the elements shown in 4D (nitrogen, nickel, vanadium, and silicon, respectively), referencing the same... Figure 3 The region 33, which is the transition between the substrate 22 and the first metal layer 26, is highlighted in the image and has a thickness of, for example, tens of nanometers.

[0043] Moving toward the silicon substrate in this enlarged cross-sectional view, the region (indicated by 40) is in direct contact with a uniform and polycrystalline NiV layer (the aforementioned first metal layer 26), which has a thickness of, for example, tens of angstroms and, in some embodiments, contains only nitrogen and vanadium atoms; followed by a silicide region 27, characterized by the simultaneous presence of Ni and Si, having a thickness of, for example, tens of nanometers, as shown in the chemical diagram, in direct contact with the rear side 22b of the substrate 22.

[0044] Basically, the above Figure 3 and Figure 4A - Figure 4D The process of forming silicide region 27 simultaneously with the sputtering deposition of the first metal layer 26 is highlighted. This silicide region 27 "kicks out" nitrogen and vanadium atoms at the interface with the substrate 22.

[0045] One aspect of this solution is the simultaneous formation of nickel silicide with the deposition of the first metal layer 26.

[0046] To more accurately control the deposition temperature (and simultaneously control the siliconization process) and to reduce thermal stress, a multi-step deposition process can be advantageously implemented.

[0047] In one possible implementation, the sputtering deposition step is performed with the following process characteristics: electrical power between 1 kW and 10 kW; Ar flow rate between 20 sccm and 90 sccm; and N2 flow rate between 0 sccm and 40 sccm. As described above, the deposition is advantageously carried out through multiple steps of deposition and stabilization (or cooling) of appropriate duration, wherein the process parameters are assumed to be values ​​included in the aforementioned ranges.

[0048] For example, a possible multi-step process for providing a first metal layer 26 with a thickness of 500 nm could be envisioned as a evacuation and stabilization step in a process gas chamber, followed by successive steps of deposition and cooling, iterated multiple times to achieve the desired NiV thickness, with the possible first step in the deposition and cooling steps being implemented, for example, at a higher sputtering power than the subsequent steps.

[0049] Similarly, the deposition step of the second metal layer 28 with a variable thickness between 150 nm and 500 nm can also be performed by a corresponding multi-step process with a corresponding number of deposition and stabilization steps of appropriate length, wherein the process parameters take values ​​included in the previously mentioned range.

[0050] Experimental tests conducted by the applicant have demonstrated that, using substantially the same warpage value of the wafer 21 of the semiconductor device 20, a thickness value significantly greater than that of the back metal structure 30 of the conventional structure can be obtained (e.g., a thickness value of 800 nm compared to the thickness value of 500 nm of the conventional structure with three metal layers).

[0051] Similarly, conversely, given the same thickness of the back metal stack, it has been shown that the final deformation of the wafer 21 of the semiconductor device 20 can be significantly reduced.

[0052] Advantageously, the applicant has demonstrated through experimental testing that the electrical performance of the semiconductor device 20 has not undergone substantial modification, particularly the reference threshold voltage and breakdown voltage values, which remain essentially unchanged (again compared to conventional structures with three metal layers).

[0053] Furthermore, the applicant has discovered that the manufacturing process increases yield by up to 30% compared to conventional processes.

[0054] The advantages achieved through this solution are clearly evident from the preceding description.

[0055] In any case, it should be emphasized that the solution offers manufacturing cost savings, with the rear metal structure 30 consisting of a small number of layers, namely only two metal layers (instead of three or four as in known solutions), and a higher yield (so-called process production rate) (even up to 30%).

[0056] In particular, since the silicide process implies mixing between the atoms of the substrate and the silicide (in this case, between nickel and silicon atoms), it ensures fewer problems associated with stripping, thus improving the strength of the semiconductor device 20.

[0057] Furthermore, as described above, compared to conventional structures, given the same thickness of the same back metal structure 30, the stress exerted by the back metal structure 30 on the wafer 21 can be reduced (or, alternatively, given the same stress exerted on the wafer 21, the thickness of the back metal structure 30 can be increased).

[0058] Essentially, even with a thick back metal stack and a small thickness of the same wafer 21, this solution is able to better manage the deformation of the wafer 21.

[0059] Finally, modifications and variations can be made to this invention.

[0060] In particular, it is emphasized that different materials or combinations of materials can be envisioned for the back metal structure 30, especially for forming the silicide region 27; for example, the first metal layer 26 may be made of nickel without any percentage of vanadium, and / or the second metal layer 28 may be made of materials other than silver, such as gold (Au).

[0061] Furthermore, the reactive gases present in the deposition chamber during the sputtering process can be different; for example, only argon may be present (instead of a mixture of argon and nitrogen).

[0062] Furthermore, it should be emphasized that this solution can find advantageous applications in various semiconductor silicon devices, such as signal or power VDMOS devices, IP (intelligent power) MOSFET devices, and devices like VIPower. TM MOSFET devices typically have vertical conductivity and use the same electrical contacts or active terminals on the back side of the wafer in all devices.

[0063] In one or more embodiments, a vertically conductive semiconductor device (20) includes: a silicon substrate (22) having a front side (22a) and a rear side (22b); a front side structure (24) disposed on the front side (22a) of the substrate (22) having at least one current-conducting region at the respective front side (24a); and a rear side metal structure (30) disposed on the rear side (22b) of the substrate (22), electrically contacting the substrate (22) and formed by overlapping stacks of metal layers, characterized in that the rear side metal structure (30) may include: a first metal layer (26); a silicide region (27) inserted between the rear side (22b) of the substrate (22) and the first metal layer (26) and electrically contacting the rear side (22b); and a second metal layer (28) disposed on the first metal layer (26).

[0064] The rear metal structure (30) may consist only of a first metal layer (26) and a second metal layer (28) stacked on the silicide region (27).

[0065] The first metal layer (26) can be mainly composed of nickel, and the silicide can be nickel silicide.

[0066] The first metal layer (26) may be composed of nickel and vanadium, with a vanadium concentration between 5 wt% and 8 wt%.

[0067] The second metal layer (28) can be made of silver or gold.

[0068] The thickness of the first metal layer (26) can be between 300 nm and 700 nm, the thickness of the second metal layer (28) can be between 150 nm and 500 nm, and the thickness of the silicide region (27) can be less than the thickness of the first metal layer (26) and the second metal layer (28).

[0069] Vertically conductive semiconductor devices for power applications may include at least one IGBT transistor.

[0070] In one or more embodiments, a process for manufacturing a vertically conductive semiconductor device (20) includes: providing a silicon substrate (22) having a front side (22a) and a rear side (22b); forming a front side structure (24) on the front side (22a) of the substrate (22), the front side structure (24) having at least one current-conducting region at a respective front side (24a); and forming a rear side metal structure (30) on the rear side (22b) of the substrate (22), the rear side metal structure (30) being electrically contacted with the substrate (22), the rear side metal structure (30) being composed of stacked overlapping metal layers, characterized in that the step of forming the rear side metal structure (30) may include: forming a first metal layer (26) on the rear side (22b) of the substrate (22), the forming step including simultaneously forming a silicide region (27) electrically contacting the rear side (22b) of the substrate (22); and forming a second metal layer (28) on the first metal layer (26).

[0071] The rear metal structure (30) may consist only of the first metal layer (26) and the second metal layer, with the silicide region (27) inserted between the rear side (22b) of the substrate (22) and the first metal layer (26).

[0072] The first metal layer (26) may be primarily composed of nickel, and the silicide may be nickel silicide.

[0073] The first metal layer (26) may be composed of nickel and vanadium, with a vanadium concentration between 5 wt% and 8 wt%.

[0074] The second metal layer (28) can be made of silver or gold.

[0075] The step of forming the first metal layer (26) can be performed by PVD (physical vapor deposition), controlling the PVD to achieve a temperature that triggers the formation of a silicide region (27) between the back side (22b) of the substrate (22) and the first metal layer (26) during deposition. The temperature can be controlled to be maintained in the range of 400°C to 500°C. The step of forming the first metal layer (26) can also be performed by sputter deposition. Sputter deposition can be envisioned using argon (Ar) and nitrogen (N2) as process gases in the deposition chamber. Sputter deposition can be performed with the following process characteristics: electrical power between 1 and 10 kW; argon flow rate between 20 sccm and 90 sccm; and nitrogen flow rate between 0 sccm and 40 sccm.

[0076] The step of forming the first metal layer (26) can be performed by multi-step deposition, which includes repeated and alternating deposition and cooling or stabilization steps until the desired total thickness is achieved.

[0077] The step of forming the second metal layer (28) can be performed by the corresponding PVD (physical vapor deposition).

[0078] The various embodiments described above can be combined to provide other embodiments.

[0079] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A vertically conductive semiconductor device, comprising: A silicon substrate having a front side and a back side; A front-side structure, on the front side of the silicon substrate, the front-side structure having at least one current-conducting region at a respective front side; as well as A rear-side metal structure, located on the rear side of the silicon substrate, is in electrical contact with the silicon substrate and comprises overlapping stacks of metal layers. The rear metal structure includes: The first metal layer comprises nickel and vanadium; A silicide region is located between the rear side of the silicon substrate and the first metal layer, and is electrically contacted with the rear side of the silicon substrate; the silicide region includes nickel silicide. The boundary region between the first metal layer and the silicide region, the boundary region comprising nitrogen and vanadium; and A second metal layer is applied over the first metal layer.

2. The device of claim 1, wherein the rear metal structure consists only of the first metal layer and the second metal layer stacked on the silicide region and the junction region.

3. The device according to claim 1, wherein the first metal layer comprises nickel and vanadium, the concentration of vanadium being between 5 wt% and 8 wt%.

4. The device of claim 1, wherein the second metal layer comprises silver or gold.

5. The device of claim 1, wherein the first metal layer has a thickness between 300 nm and 700 nm, the second metal layer has a thickness between 150 nm and 500 nm, and the silicide region has a thickness less than the thickness of the first metal layer and the thickness of the second metal layer.

6. The device of claim 1, wherein the device is configured for power applications, and the front-side structure includes at least one IGBT transistor.

7. A process for manufacturing a vertically conductive semiconductor device, the process comprising: Provides a silicon substrate with a front side and a back side; A front-side structure is formed on the front side of the silicon substrate, the front-side structure having at least one current-conducting region at the respective front side; as well as A rear-side metal structure is formed on the rear side of the silicon substrate, the rear-side metal structure being in electrical contact with the silicon substrate, the rear-side metal structure comprising overlapping stacks of metal layers. The formation of the rear metal structure includes: A first metal layer is formed on the rear side of the silicon substrate, the formation of the first metal layer including the simultaneous formation of a silicide region electrically in contact with the rear side of the silicon substrate, wherein the formation of the first metal layer is performed by physical vapor deposition (PVD), the PVD being controlled to reach a temperature that triggers the formation of the silicide region during the PVD. as well as A second metal layer is formed on the first metal layer.

8. The process according to claim 7, wherein the rear metal structure is composed only of the first metal layer and the second metal layer.

9. The process of claim 7, wherein the first metal layer comprises nickel, and the silicide region is a nickel silicide region.

10. The process of claim 7, wherein the first metal layer comprises nickel and vanadium, the concentration of vanadium being between 5 wt% and 8 wt%.

11. The process of claim 7, wherein the second metal layer comprises silver or gold.

12. The process of claim 7, wherein the temperature is controlled to be maintained in the range between 400°C and 500°C during PVD.

13. The process of claim 7, wherein the formation of the first metal layer is performed by sputter deposition.

14. The process of claim 13, wherein the sputtering deposition uses argon (Ar) and nitrogen (N2) as process gases in the deposition chamber.

15. The process of claim 14, wherein the sputtering deposition is performed using the following process features: an electrical power between 1 kW and 10 kW; an argon flow rate between 20 sccm and 90 sccm; and a nitrogen flow rate between 0 sccm and 40 sccm.

16. The process of claim 7, wherein the formation of the first metal layer is performed by multi-step deposition until a predetermined total thickness is reached, the multi-step deposition comprising repeated and alternating deposition steps and cooling or stabilization steps.

17. The process of claim 7, wherein the formation of the second metal layer is performed by a corresponding PVD.

18. A method for manufacturing a vertically conductive semiconductor device, comprising: A first structure is formed on a first side of a substrate, the first structure including a transistor; as well as A second structure is formed on a second side of the substrate opposite to the first side, the second structure being electrically coupled to the substrate, the formation of the second structure comprising: A first conductive layer is formed on the second side of the substrate; During the formation of the first conductive layer, a silicide region is formed between the second side of the substrate and the first conductive layer, the silicide region being electrically coupled to the substrate, wherein the formation of the first conductive layer is performed at a temperature that triggers the formation of the silicide region; and A second conductive layer is formed on the first conductive layer.

19. The method of claim 18, wherein the second structure is a contact structure.

20. The method of claim 18, wherein the first conductive layer comprises nickel, the silicide region comprises nickel silicide, and the second conductive layer comprises silver or gold.

Images