Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: providing a substrate, the substrate having a gate structure and active source / drain doped regions in the substrate on both sides of the gate structure, and an interlayer dielectric layer on the substrate on the sides of the gate structure and covering the top of the gate structure; forming source / drain plugs penetrating through the interlayer dielectric layer above the top of the source / drain doped regions and gate plugs penetrating through the interlayer dielectric layer above the top of the gate structure, the gate plugs being arranged opposite to the sidewalls of the source / drain plugs; etching the interlayer dielectric layer between the source / drain plugs and the gate plugs to form a trench surrounded by the sidewalls of the source / drain plugs and the gate plugs and the substrate; and forming a sealing dielectric layer in the trench to seal the top of the trench, the sealing dielectric layer in the trench having an air gap formed therein. The air gap is formed after the source / drain plugs and the gate plugs are formed, which reduces the probability of short circuit between the source / drain doped regions and the gate structure, and reduces the capacitance between the gate structure and the source / drain plugs, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source / drain doped regions located within the substrate on both sides of the gate structure; a source / drain plug located at the top of the source / drain doped regions and connected to them; a gate plug located at the top of the gate structure and connected to it, wherein the sidewalls of the gate plug and the source / drain plug are disposed opposite to each other, and the opposite sidewalls of the source / drain plug and the gate plug, together with the substrate, form a trench; and a sealing dielectric layer located in the trench and sealing the top of the trench, wherein the sealing dielectric layer in the trench has an air gap.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped regions are formed in the substrate on both sides of the gate structure, an interlayer dielectric layer is formed on the substrate on the side of the gate structure, the interlayer dielectric layer covering the top of the gate structure; forming a source and drain plug penetrating the interlayer dielectric layer above the top of the source and drain doped regions and connected to the source and drain doped regions, and a gate plug penetrating the interlayer dielectric layer above the top of the gate structure and connected to the gate structure, wherein the sidewalls of the gate plug and the source and drain plug are disposed opposite to each other; etching the interlayer dielectric layer between the source and drain plug and the gate plug, such that the opposite sidewalls of the source and drain plug and the gate plug form a trench with the substrate; forming a sealing dielectric layer in the trench, the sealing dielectric layer sealing the top of the trench, and an air gap being formed in the sealing dielectric layer in the trench.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the formation method provided by this embodiment of the invention, a source / drain plug is first formed that penetrates the interlayer dielectric layer above the top of the source / drain doped region and is connected to the source / drain doped region, and a gate plug is formed that penetrates the interlayer dielectric layer above the top of the gate structure and is connected to the gate structure. Then, the interlayer dielectric layer between the source / drain plug and the gate plug is etched, so that the opposing sidewalls of the source / drain plug and the gate plug, together with the substrate, form a trench. A sealing dielectric layer is formed in the trench, sealing the top of the trench, and an air gap is formed in the sealing dielectric layer within the trench. By forming the trench and using the sealing dielectric layer to seal the top of the trench to form an air gap, an air gap is formed between the source / drain plug and the gate plug, thereby reducing the capacitance between the gate structure and the source / drain plug. Correspondingly, in this embodiment of the invention, no air sidewalls are formed between the sidewalls of the gate structure and the interlayer dielectric layer before forming the source / drain plug and the gate plug. Therefore, the probability of material filling the source / drain plug or gate plug to the sidewall of the gate structure is reduced, thereby reducing the probability of short circuit between the source / drain doped region and the gate structure. In summary, after forming the source / drain plug and the gate plug, the embodiment of the present invention forms an air gap between the source / drain plug and the gate plug, which not only reduces the probability of short circuit between the source / drain doped region and the gate structure, but also reduces the capacitance between the gate structure and the source / drain plug, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a semiconductor structure.

[0010] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a particular semiconductor structure needs further improvement.

[0013] refer to Figure 1 The diagram shows a schematic of a semiconductor structure.

[0014] The semiconductor structure includes: a substrate 10; a gate structure 20 located on the substrate 10; source / drain doped regions 30 located within the substrate 10 on both sides of the gate structure 20; an interlayer dielectric layer 40 covering the gate structure 20 and the substrate 10; an air sidewall 25 located between the sidewall of the gate structure 20 and the interlayer dielectric layer 40; a source / drain plug 50 penetrating the interlayer dielectric layer 40 at the top of the source / drain doped regions 30 and connected to the source / drain doped regions 30; and a gate plug 60 penetrating the interlayer dielectric layer 40 at the top of the gate structure 20 and connected to the gate structure 20.

[0015] An air sidewall 25 is provided between the sidewall of the gate structure 20 and the interlayer dielectric layer 40 to reduce the capacitance between the gate structure 20 and the source / drain plug 50. The steps of forming the source / drain plug 50 and the gate plug 60 include: etching the interlayer dielectric layer 40 on top of the source / drain doped region 30 to form a source / drain contact hole (not shown); etching the interlayer dielectric layer 40 on top of the gate structure 20 to form a gate contact hole (not shown); and filling the source / drain contact hole and the gate contact hole with conductive material to form the source / drain plug 50 located in the source / drain contact hole and the gate plug 60 located in the gate contact hole. However, during the etching of the interlayer dielectric layer 40, when overlay shift or over-etch (OE) occurs, the air sidewall 25 is easily etched through, causing the air sidewall 25 to connect with the source / drain contact hole or the gate contact hole. This increases the probability that the sidewall of the gate structure 20 or the source / drain doped region 30 is exposed. Consequently, the material of the source / drain plug 50 or the gate plug 60 fills the air sidewall 25, which in turn increases the probability that a short circuit occurs between the drain doped region 30 and the gate structure 20, thereby reducing the performance of the semiconductor structure.

[0016] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source / drain doped regions located within the substrate on both sides of the gate structure; a source / drain plug located at the top of and connected to the source / drain doped regions; a gate plug located at the top of and connected to the gate structure, wherein the sidewalls of the gate plug and the sidewalls of the source / drain plug are disposed opposite to each other, and the opposing sidewalls of the source / drain plug and the gate plug, together with the substrate, form a trench; and a sealing dielectric layer located in the trench and sealing the top of the trench, wherein the sealing dielectric layer in the trench has an air gap.

[0017] This invention reduces the capacitance between the gate structure and the source / drain plugs by providing an air gap between the source / drain plugs and the gate plugs. Furthermore, this invention does not provide air sidewalls at the sidewalls of the gate structure, thus reducing the probability of material from the source / drain plugs or gate plugs filling the sidewalls of the gate structure, thereby reducing the probability of short circuits between the source / drain doped regions and the gate structure. In summary, this invention not only reduces the probability of short circuits between the source / drain doped regions and the gate structure but also reduces the capacitance between the gate structure and the source / drain plugs, thereby improving the performance of the semiconductor structure, for example, improving the AC performance of the semiconductor structure.

[0018] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0020] The semiconductor structure includes: a substrate 100; a gate structure 110 located on the substrate 100; source / drain doped regions 120 located within the substrate 100 on both sides of the gate structure 110; a source / drain plug 130 located on top of and connected to the source / drain doped regions 120; a gate plug 140 located on top of and connected to the gate structure 110, the sidewalls of the gate plug 140 being opposite to the sidewalls of the source / drain plug 130, and the opposing sidewalls of the source / drain plug 130 and the gate plug 140 forming a trench (not shown) with the substrate 100; and a sealing dielectric layer 160 located in the trench and sealing the top of the trench, the sealing dielectric layer 160 in the trench having an air gap 165.

[0021] By providing an air gap 165 between the source / drain plug 130 and the gate plug 140, the capacitance between the gate structure 110 and the source / drain plug 130 is reduced. Furthermore, since no air sidewalls are provided at the sidewall positions of the gate structure 110, during the formation of the semiconductor structure, the probability of material from the source / drain plug 130 or the gate plug 140 filling the sidewall positions of the gate structure 110 is reduced, thereby reducing the probability of a short circuit occurring between the source / drain doped region 120 and the gate structure 110. In summary, this embodiment, by providing an air gap 165 between the source / drain plug 130 and the gate plug 140, not only reduces the probability of a short circuit occurring between the source / drain doped region 120 and the gate structure 110, but also reduces the capacitance between the gate structure 110 and the source / drain plug 130, thereby improving the performance of the semiconductor structure (e.g., improving the AC performance of the semiconductor structure).

[0022] The substrate 100 provides a process platform for the formation of the semiconductor structure. In this embodiment, taking a FinFET as an example, the substrate 100 includes a substrate 101 and a fin 102 protruding from the substrate 101. In other embodiments, the semiconductor structure is a planar field-effect transistor, and the substrate is correspondingly a planar substrate. In this embodiment, the substrate 101 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the substrate material can be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In this embodiment, the fin 102 and the substrate 101 are an integral structure, and the material of the fin 102 is silicon. In this embodiment, the substrate 100 includes an active area (AA), and the transistor is located on the active area of ​​the substrate 100. It should be noted that... Figure 2 It is a cross-sectional view along the extension direction of the fin 102 and at a position on one side of the fin 102.

[0023] The gate structure 110 is used to control the switching on or off of the transistor's channel. In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. The high-k gate dielectric layer is made of a high-k dielectric material, wherein a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2. The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. The gate electrode layer is used to bring out the electrical properties of the gate structure 110. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In other embodiments, depending on process requirements, the gate structure can also be a polysilicon gate structure.

[0024] The source / drain doped regions 120 are located within the substrate 100 of the active region. As an example, the source / drain doped regions 120 are located in the fins 102 on both sides of the gate structure 110. The source / drain doped regions 120 include an epitaxial layer doped with ions. When the semiconductor structure is an NMOS transistor, the material of the epitaxial layer is Si or SiC, and the doping ions in the epitaxial layer are N-type ions, including P ions, As ions, or Sb ions; when the semiconductor structure is a PMOS transistor, the material of the epitaxial layer is Si or SiGe, and the doping ions in the epitaxial layer are P-type ions, including B ions, Ga ions, or In ions.

[0025] The source / drain plug 130 is used to establish an electrical connection between the source / drain doped region 120 and external circuitry or other interconnect structures. In this embodiment, the source / drain plug 130 is made of tungsten. In other embodiments, the source / drain plug may also be made of conductive materials such as ruthenium or cobalt. The gate plug 140 is used to establish an electrical connection between the gate structure 110 and external circuitry or other interconnect structures. In this embodiment, the gate plug 140 is made of tungsten. In other embodiments, the gate plug may also be made of conductive materials such as ruthenium or cobalt.

[0026] In this embodiment, the sidewall of the gate plug 140 is disposed opposite to the sidewall of the source / drain plug 130, and the opposing sidewalls of the source / drain plug 130 and the gate plug 140, together with the substrate 100, form a trench. The trench provides space for the formation of the sealing dielectric layer 160, thereby enabling the sealing dielectric layer 160 to form an air gap 165 between the source / drain plug 130 and the gate plug 140. The trench is formed by disposing the sidewalls of the source / drain plug 130 and the gate plug 140 opposite to each other. Correspondingly, the gate plug 140 is located above the gate structure 110 in the active region. The gate plug 140 is an active gate contact plug (COAG). Compared to the scheme where the gate plug contacts the gate structure located in the isolation region, this embodiment eliminates the portion of the gate structure 110 located in the isolation region, which helps save chip area and thus achieves further reduction in chip size.

[0027] In this embodiment, the top linewidth of the source / drain plug 13 is greater than its bottom linewidth, and the top linewidth of the gate plug 140 is greater than its bottom linewidth. That is, the longitudinal cross-sectional shape of either the source / drain plug 130 or the gate plug 140 is an inverted trapezoid. This results in a smaller top opening and a larger bottom opening of the trench, allowing the material of the sealing dielectric layer 160 to easily accumulate at the opening. This allows for sealing at the trench opening even before the trench is fully filled, thus facilitating the sealing dielectric layer 160's sealing of the top of the trench and the formation of an air gap 165. The angle α between the sidewall of either the source / drain plug 130 or the gate plug 140 and the surface of the substrate 100 should not be too small or too large. If the angle α is too large, the sealing dielectric layer 160 may fail to seal the top of the trench and form an air gap 165; if the angle α is too small, the source / drain plug 130 and the gate plug 140 may easily come into contact. Therefore, in this embodiment, the angle α between the sidewall of either the source / drain plug 130 or the gate plug 140 and the surface of the substrate 100 is 85 to 88 degrees. In this embodiment, the surface of the substrate 100 refers to the surface of the substrate 101, which is a horizontal plane.

[0028] A sealing dielectric layer 160 is used to seal the top of the trench, thereby forming an air gap 165 between the source / drain plug 130 and the gate plug 140. The sealing dielectric layer 160 also serves to isolate the source / drain plug 130 and the gate plug 140. The material of the sealing dielectric layer 160 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the sealing dielectric layer 160 is silicon oxide. Silicon oxide has appropriate hardness, which helps to reduce the probability of damage to the sealing dielectric layer 160 in subsequent processes, and its dielectric constant is appropriate, resulting in a smaller capacitance between the source / drain plug 130 and the gate structure 110. In other embodiments, to further reduce the capacitance between the source / drain plug and the gate structure, the material of the sealing dielectric layer may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6).

[0029] In this embodiment, the sealing dielectric layer 160 is also located on the substrate 100 on the sides of the source / drain plug 130 and the gate plug 140. During the formation of the semiconductor structure, the source / drain plug 130 and the gate plug 140 are formed in the interlayer dielectric layer. By placing the sealing dielectric layer 160 on the substrate 100 on the sides of the source / drain plug 130 and the gate plug 140, the interlayer dielectric layer can be globally etched using a maskless etching method, so that the opposite sidewalls of the source / drain plug 130 and the gate plug 140 form a trench with the substrate 100, and then the sealing dielectric layer 160 sealing the trench is formed. Therefore, by placing the sealing dielectric layer 160 on the substrate 100 on the sides of the source / drain plug 130 and the gate plug 140, the process complexity is reduced while saving photomasks.

[0030] In this embodiment, during the formation of the semiconductor structure, when the interlayer dielectric layer is globally etched, only a portion of its thickness is removed. Therefore, the semiconductor structure further includes an interlayer dielectric layer (not shown), located between the bottom of the sealing dielectric layer 160 and the substrate 100. As described above, after etching the interlayer dielectric layer to form trenches, the sealing dielectric layer is then formed. By placing the interlayer dielectric layer between the bottom of the sealing dielectric layer and the substrate, the amount of re-etching of the interlayer dielectric layer is reduced, thereby helping to reduce process time and lower process costs. As an example, the top of the interlayer dielectric layer is lower than the top of the fin 102. It should be noted that... Figure 2 It is a cross-sectional view along the extending direction of the fin 102 and at a position on one side of the fin 102. Therefore, Figure 2 The interlayer dielectric layer is not shown in the diagram.

[0031] It should also be noted that the distance from the top of the interlayer dielectric layer to the top of either the source / drain plug or the gate plug is at least 15 nanometers, thus providing sufficient space for the formation of the air gap, which in turn significantly reduces the capacitance between the gate structure and the source / drain plug. Specifically, to reduce the amount of back etching of the interlayer dielectric layer and to significantly reduce the capacitance between the gate structure and the source / drain plug, the distance from the top of the interlayer dielectric layer to the top of either the source / drain plug or the gate plug is between 15 nanometers and 95 nanometers.

[0032] In this embodiment, the sealing dielectric layer 160 exposes the tops of the gate plug 140 and the source / drain plug 130. By exposing the sealing dielectric layer 160 to the tops of the gate plug 140 and the source / drain plug 130, preparation is made for the subsequent formation of metal interconnects that electrically connect to the gate plug 140 and the source / drain plug 130. Accordingly, the material of the inter-metal dielectric (IMD) layer can be flexibly selected to meet the performance requirements of the semiconductor structure. In other embodiments, the sealing dielectric layer may also cover the tops of the gate plug and the source / drain plug, so that the sealing dielectric layer above the tops of the gate plug and the source / drain plug serves as the inter-metal dielectric layer, thereby simplifying the back-end (BEOL) process steps.

[0033] In this embodiment, the semiconductor structure further includes a gate cap layer 170, located on top of the gate structure 110 exposed by the gate plug 140. As described above, during the formation of the semiconductor structure, after etching the interlayer dielectric layer to form a trench, a sealing dielectric layer is formed. During the etching of the interlayer dielectric layer, the gate cap layer 170 protects the top of the gate structure 110, thereby reducing damage to the gate structure 110. The material of the gate cap layer 170 includes one or both of titanium nitride and tantalum nitride. The gate cap layer 170 has high etching resistance, and the interlayer dielectric layer and the gate cap layer 170 have a high etching selectivity ratio. Therefore, during the etching of the interlayer dielectric layer to form a trench, the probability of damage to the gate cap layer 170 is low, resulting in better protection of the top of the gate structure 110. As an example, the material of the gate cap layer 170 is titanium nitride.

[0034] The thickness of the gate capping layer 170 should not be too small or too large. If the thickness of the gate capping layer 170 is too small, the protective effect of the gate capping layer 170 on the top of the gate structure 110 will be reduced accordingly. During the formation of the semiconductor structure, the gate capping layer 170 is usually formed on top of the remaining gate structure 110 after removing part of the height of the gate structure 110. If the thickness of the gate capping layer 170 is too large, the height of the gate structure 110 in the semiconductor structure will be too small, thereby reducing the control capability of the gate structure 110 over the channel and thus reducing the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the gate capping layer 170 is 3 nanometers to 20 nanometers. For example, it is 5 nanometers, 7 nanometers, 10 nanometers, 15 nanometers, or 17 nanometers.

[0035] In this embodiment, the semiconductor structure further includes a barrier layer 190 covering the sidewalls of the gate plug 140 and the source / drain plug 130. Specifically, the barrier layer 190 is located between the sidewall of the gate plug 140 and the sealing dielectric layer 160, and between the sidewall of the gate plug 140 and the gate cap layer 170. The barrier layer 190 is also located between the sidewall of the source / drain plug 130 and the sealing dielectric layer 160. The barrier layer 190 is used to reduce the diffusion of easily diffusing ions from the materials of the source / drain plug 130 and the gate plug 140 into the sealing dielectric layer 160. In this embodiment, the material of the barrier layer 190 includes one or both of titanium nitride and tantalum nitride.

[0036] In this embodiment, the barrier layer 190 only covers the sidewalls of the gate plug 140 and the source / drain plug 130, thereby allowing the source / drain plug 130 to directly contact the source / drain doped region 120 and the gate plug 140 to directly contact the gate structure 110, thus reducing contact resistance. It should be noted that during the formation of the semiconductor structure, when etching back the interlayer dielectric layer, the barrier layer 190 also protects the sidewalls of the source / drain plug 130 and the gate plug 140, thereby reducing the probability of damage to the source / drain plug 130 and the gate plug 140. The barrier layer 190 is made of one or both of titanium nitride and tantalum nitride. The material of the interlayer dielectric layer and the barrier layer 190 have a high etch selectivity ratio; therefore, the probability of damage to the barrier layer 190 during the etching back of the interlayer dielectric layer is low, resulting in better protection of the sidewalls of the source / drain plug 130 and the gate plug 140.

[0037] In this embodiment, the semiconductor structure further includes a sidewall structure 180 that covers a portion of the sidewall of the gate structure 110, with the top of the sidewall structure 180 lower than the top of the gate structure 110. The material of the sidewall structure 180 typically has a high dielectric constant. Therefore, compared to a scheme where the sidewall structure completely covers the sidewall of the gate structure, this embodiment, by making the top of the sidewall structure 180 lower than the top of the gate structure 110, helps to further reduce the capacitance between the gate structure 110 and the source / drain plug 130. Specifically, the sidewall structure 180 includes a sidewall layer 181 covering the sidewall of the gate structure 110, and a contact etch stop layer (CESL) 182 covering the sidewall of the sidewall layer 181.

[0038] The sidewall layer 181 is used to protect the sidewalls of the gate structure 110 and also to define the formation region of the source / drain doped region 120. In this embodiment, the material of the sidewall layer 181 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. As an example, the material of the sidewall layer 181 is silicon nitride. Silicon nitride has high density and etching resistance, which ensures the protective effect of the sidewall layer 181. During the formation of the semiconductor structure, before the formation of the source / drain plug 130, the contact hole etch stop layer 182 also covers the source / drain doped region 120; when the source / drain plug 130 is formed, the source / drain plug 130 is formed in the source / drain contact hole above the source / drain doped region 120, and the source / drain contact hole penetrates the interlayer dielectric layer and the contact hole etch stop layer 182. In the step of etching the interlayer dielectric layer, the contact hole etch stop layer 182 is used to define the etch stop position, thereby reducing the probability of over-etching the source / drain doped region 120. After the etching of the interlayer dielectric layer is completed, the contact hole etch stop layer 182 above the source / drain doped region 120 is etched to form the source / drain contact hole. In this embodiment, the material of the contact hole etch stop layer 182 is silicon nitride.

[0039] Both the sidewall layer 181 and the contact hole etch stop layer 182 have high dielectric constants. By making the tops of both the sidewall layer 181 and the contact hole etch stop layer 182 lower than the top of the gate structure 110, the effect of reducing the capacitance between the gate structure 110 and the source / drain plug 130 is significant. In this embodiment, in order to significantly reduce the capacitance between the gate structure 110 and the source / drain plug 130, the distance from the top of the sidewall structure 180 to the top of the gate structure 110 is at least 5 nanometers. However, during the formation of the semiconductor structure, the height of the sidewall structure 180 is reduced by etching it. Therefore, increasing the distance from the top of the sidewall structure 180 to the top of the gate structure 110 will correspondingly increase the time and cost required to etch the sidewall structure 180. Therefore, in this embodiment, in order to reduce the time and cost required to etch the sidewall structure 180, and to significantly reduce the capacitance between the gate structure 110 and the source / drain plug 130, the distance from the top of the sidewall structure 180 to the top of the gate structure 110 is 5 nanometers to 20 nanometers. As an example, the top of the sidewall structure 180 is flush with the top of the fin 102. It should be noted that in other embodiments, the semiconductor structure may not contain a sidewall structure. For example, during the formation of the semiconductor structure, the sidewall structure may be completely removed based on its initial height and the amount of etching.

[0040] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0041] refer to Figures 3 to 6 A substrate 200 is provided, on which a gate structure 210 is formed. Active and drain doped regions 220 are formed in the substrate 200 on both sides of the gate structure 210. An interlayer dielectric layer 300 is formed on the substrate 200 on the side of the gate structure 210, and the interlayer dielectric layer 300 covers the top of the gate structure 210.

[0042] The substrate 200 provides a process platform for the formation of semiconductor structures. In this embodiment, taking the formation of a fin field-effect transistor as an example, the substrate 200 includes a substrate 201 and fins 202 protruding from the substrate 201. In other embodiments, the substrate is used to form a planar field-effect transistor, and the substrate is correspondingly a planar substrate. In this embodiment, the substrate 201 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the substrate material can be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In this embodiment, the fins 202 and the substrate 201 are an integral structure, and the material of the fins 202 is silicon. In this embodiment, the substrate 200 includes an active region, which is used to form the transistor. It should be noted that... Figures 3 to 6 All are cross-sectional views along the extension direction of the fin 202 and at a position on one side of the fin 202.

[0043] The gate structure 210 is used to control the opening or closing of the transistor channel. In this embodiment, the gate structure 210 is a metal gate structure, including a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer. The high-k gate dielectric layer is made of a high-k dielectric material, wherein a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. As an example, the high-k gate dielectric layer is made of HfO2. The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer; when forming an NMOS transistor, the work function layer is an N-type work function layer. The gate electrode layer is used to bring out the electrical properties of the gate structure 110. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In other embodiments, depending on process requirements, the gate structure may also be a polysilicon gate structure.

[0044] The source / drain doped regions 220 are formed in the substrate 200 of the active region. As an example, the source / drain doped regions 220 are formed in the fins 202 on both sides of the gate structure 210. In this embodiment, the source / drain doped regions 220 are formed by an epitaxial process and include an epitaxial layer doped with ions. When forming an NMOS transistor, the material of the epitaxial layer is Si or SiC, and the dopant ions in the epitaxial layer are N-type ions. When forming a PMOS transistor, the material of the epitaxial layer is Si or SiGe, and the dopant ions in the epitaxial layer are P-type ions.

[0045] The interlayer dielectric layer 300 is used to isolate adjacent devices. The material of the interlayer dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 300 is silicon oxide.

[0046] In this embodiment, the gate structure 210 is formed using a process of forming a high-k gate dielectric layer followed by a gate electrode layer (high-klast metal gate last). Therefore, in conjunction with the reference... Figure 3 Before the interlayer dielectric layer 300 is formed, a bottom dielectric layer 310 is formed on the substrate 200 on the side of the gate structure 210, and the bottom dielectric layer 310 covers the sidewall of the gate structure 210.

[0047] Specifically, before forming the gate structure 210, the formation method further includes: forming a dummy gate structure on the substrate 100. The dummy gate structure is used to occupy space for the formation of the gate structure 210. Correspondingly, source and drain doped regions 220 are formed in the substrate 200 on both sides of the dummy gate structure. After forming the drain doped region 220, the bottom dielectric layer 310 is formed on the substrate 200 on the side of the dummy gate structure. The dummy gate structure is then removed, and a gate opening is formed in the bottom dielectric layer 310.

[0048] A gate structure 210 is formed in the gate opening, and the top and bottom dielectric layers 310 of the gate structure 210 are flush. Specifically, a high-k gate dielectric layer conformally covers the bottom and sidewalls of the gate opening, a work function layer conformally covers the high-k gate dielectric layer, and a gate electrode layer fills the gate opening and covers the work function layer.

[0049] Reference Figure 3 In this embodiment, the sidewall of the gate structure 210 is formed with a sidewall structure 280.

[0050] Specifically, the sidewall structure 280 includes a sidewall layer 281 covering the sidewalls of the gate structure 210, and a contact hole etch stop layer 282 covering the sidewalls of the sidewall layer 281. The sidewall layer 281 is used to protect the sidewalls of the gate structure 210 and also to define the formation regions of the source / drain doped regions 220. In this embodiment, the material of the sidewall layer 281 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. As an example, the material of the sidewall layer 281 is silicon nitride.

[0051] The contact hole etch stop layer 281 covers not only the sidewalls of the sidewall layer 281, but also the source / drain doped regions 220 and the substrate 200. During the subsequent formation of the interlayer dielectric layer 300, which penetrates the top of the source / drain doped regions 220 and connects to them, the contact hole etch stop layer 282 defines the etch stop position when etching the interlayer dielectric layer 300, thereby reducing the probability of over-etching the source / drain doped regions 220. In this embodiment, the material of the contact hole etch stop layer 282 is silicon nitride.

[0052] Reference Figure 4 and Figure 5 In this embodiment, a gate cap layer 330 is formed on the top of the gate structure 210 (e.g., Figure 5 (As shown).

[0053] After the formation of the interlayer dielectric layer 300 that penetrates the top of the source / drain doped region 220 and is connected to the source / drain doped region 220, and the interlayer dielectric layer 300 that penetrates the top of the gate structure 210 and is connected to the gate structure 210, the process further includes etching the interlayer dielectric layer 300 between the source / drain plug and the gate plug, so that the opposite sidewalls of the source / drain plug and the gate plug form a trench with the substrate 200. During the subsequent etching of the interlayer dielectric layer 300, the gate cap layer 330 is used to protect the top of the gate structure 210, thereby reducing damage to the gate structure 210.

[0054] The gate cap layer 330 is made of one or both of titanium nitride and tantalum nitride. The gate cap layer 330 has high etch resistance, and the interlayer dielectric layer 320 has a high etch selectivity with the gate cap layer 330. Therefore, during the subsequent etching of the interlayer dielectric layer 300 to form a trench, the probability of damage to the gate cap layer 330 is low, resulting in better protection of the top of the gate structure 210. As an example, the gate cap layer 330 is made of titanium nitride.

[0055] Reference Figure 4 Before forming the interlayer dielectric layer 300, the forming method further includes: removing a portion of the height of the gate structure 200 and forming a first groove 315 in the bottom dielectric layer 310.

[0056] The first groove 315 provides space for the formation of the gate cap layer 330. In this embodiment, a portion of the gate structure 200 is removed by etching. The etching options for the gate structure 200 and other layers (e.g., the bottom dielectric layer 310) are relatively flexible; a maskless etching method can be used to form the first groove 315. Consequently, by forming the gate cap layer 330 in the first groove 315, a photomask can be saved, thereby reducing process costs. Furthermore, the top of the gate cap layer 330 is flush with the top of the bottom dielectric layer 310, which helps improve the flatness of the top surface of the interlayer dielectric layer. In addition, the gate cap layer 330 is formed in the first groove 315, ensuring that the top and sidewalls of the gate structure 200 are completely covered, further reducing the probability of damage to the gate structure 210 during subsequent etching of the interlayer dielectric layer 300. In this embodiment, an anisotropic etching process is used to etch a portion of the gate structure 200 to form the first groove 315. The longitudinal etching rate of the anisotropic etching process is greater than its lateral etching rate, which is beneficial to improving the sidewall morphology quality of the first groove 315 and to precisely controlling the etching amount of the gate structure 200.

[0057] It should be noted that the depth of the first groove 315 should not be too small or too large. If the depth of the first groove 315 is too small, the protective effect of the gate cap layer on the top of the gate structure 210 will be reduced accordingly; if the depth of the first groove 315 is too large, the remaining height of the gate structure 210 will be too small, thereby reducing the control capability of the gate structure 210 over the channel and thus reducing the performance of the semiconductor structure. Therefore, in this embodiment, the depth of the first groove 315 is 3 nanometers to 20 nanometers. For example, the depth of the first groove 315 is 5 nanometers, 7 nanometers, 10 nanometers, 15 nanometers, or 17 nanometers.

[0058] Accordingly, in conjunction with references Figure 5 A gate cap layer 330 is formed in the first groove 315. Specifically, the step of forming the gate cap layer 330 includes: filling the first groove 315 with a gate cap material layer, the gate cap material layer also covering the top of the bottom dielectric layer 310; using the top of the bottom dielectric layer 310 as a stop position, planarizing the gate cap material layer, and retaining the remaining gate cap material layer in the first groove 315 as the gate cap layer 330. As an example, a chemical mechanical polishing process is used to planarize the gate cap material layer.

[0059] Reference Figure 6 The step of forming the interlayer dielectric layer 200 includes forming a top dielectric layer 320 covering the gate structure 210 and the bottom dielectric layer 310, wherein the top dielectric layer 320 and the bottom dielectric layer 310 are used to constitute the interlayer dielectric layer 300.

[0060] Reference Figure 7 and Figure 8 A source / drain plug 230 is formed, which extends through the interlayer dielectric layer 300 above the top of the source / drain doped region 220 and is connected to the source / drain doped region 220. Figure 8 (as shown), and the gate plug 240 (as shown) that penetrates the interlayer dielectric layer 300 above the top of the gate structure 210 and is connected to the gate structure 210. Figure 8 As shown, the sidewall of the gate plug 240 is disposed opposite to the sidewall of the source / drain plug 230.

[0061] The source / drain plug 230 is used to realize the electrical connection between the source / drain doped region 220 and external circuits or other interconnect structures, and the gate plug 240 is used to realize the electrical connection between the gate structure 210 and external circuits or other interconnect structures. Before forming the source / drain plug 230 and the gate plug 240, no air sidewall is formed between the sidewall of the gate structure 210 and the interlayer dielectric layer 300. Therefore, during the formation of the source / drain plug 230 or the gate plug 240, the probability that the material of the source / drain plug 230 or the gate plug 240 fills to the sidewall position of the gate structure 210 is reduced, thereby reducing the probability of a short circuit between the source / drain doped region 220 and the gate structure 210.

[0062] In this embodiment, the sidewalls of the gate plug 240 and the source / drain plug 230 are disposed opposite to each other. Therefore, the gate plug 240 is formed above the gate structure 110 in the active region. The gate plug 240 is the active gate contact plug. Compared with the scheme where the gate plug is in contact with the gate structure located in the isolation region, this embodiment eliminates the part of the gate structure 210 located in the isolation region, which is beneficial to save the chip area and thus achieve further reduction in chip size.

[0063] In this embodiment, the top linewidth of the source / drain plug 230 is larger than its bottom linewidth, and the top linewidth of the gate plug 240 is larger than its bottom linewidth; that is, the longitudinal cross-sectional shape of both the source / drain plug 230 and the gate plug 240 is an inverted trapezoid. Correspondingly, after the trench is formed, the top opening size of the trench is smaller and the bottom opening size is larger, making it easier for the sealing medium layer material to accumulate at the opening. This allows for sealing at the trench opening even before the trench is completely filled, thus facilitating the sealing medium layer's ability to seal the top of the trench. The angle α between the sidewall of either the source / drain plug 230 or the gate plug 240 and the surface of the substrate 200 should not be too small or too large. If the angle α is too large, the subsequent sealing medium layer may fail to seal the top of the trench and create an air gap; if the angle α is too small, the source / drain plug 230 and the gate plug 240 may easily come into contact. Therefore, in this embodiment, the angle α between the sidewall of either the source / drain plug 230 or the gate plug 240 and the surface of the substrate 100 is 85 to 88 degrees. In this embodiment, the surface of the substrate 200 refers to the surface of the substrate 201, which is a horizontal plane.

[0064] Specifically, the steps for forming the source / drain plug 230 include: Figure 7 As shown, the interlayer dielectric layer 300 and the contact hole etching stop layer 282 on both sides of the gate structure 210 are etched sequentially to form source / drain contact holes 235 that expose the source / drain doped regions 220; as Figure 8 As shown, the source / drain contact hole 235 is filled to form a source / drain plug 230 located in the source / drain contact hole 235. In this embodiment, the material of the source / drain plug 230 is tungsten. In other embodiments, the material of the source / drain plug can also be a conductive material such as ruthenium or cobalt. Specifically, the step of forming the gate plug 240 includes: as shown in the figure. Figure 7 As shown, the interlayer dielectric layer 300 and the gate cap layer 330 above the top of the gate structure 210 are etched sequentially to form a gate contact hole 245 exposing the top of the gate structure 210; as Figure 8 As shown, the gate contact hole 245 is filled to form a gate plug 240 located within the gate contact hole 245. In this embodiment, the gate plug 240 is made of tungsten. In other embodiments, the gate plug can also be made of conductive materials such as ruthenium or cobalt. The top linewidth of the source / drain plug 230 is larger than the bottom linewidth, and the top linewidth of the gate plug 240 is larger than the bottom linewidth. Therefore, the top linewidth of the source / drain contact hole 235 is larger than the bottom linewidth, and the top linewidth of the gate contact hole 245 is larger than the bottom linewidth. Furthermore, through etching processes, the linewidths of the source / drain contact hole 235 and the gate contact hole 245 can easily meet the above conditions.

[0065] In this embodiment, after forming the source / drain contact hole 235 and the gate contact hole 245, the source / drain plug 230 and the gate plug 240 are formed in the same step.

[0066] It should be noted that, after forming the source / drain contact hole 235 and the gate contact hole 245, and before forming the source / drain plug 230 and the gate plug 240, the forming method further includes: forming a barrier layer 340 on the sidewall of the source / drain contact hole 235 and the gate contact hole 245.

[0067] The barrier layer 340 reduces the diffusion of easily diffusing ions from the materials of the source / drain plugs 230 and the gate plug 240 into the interlayer dielectric layer 300. During subsequent etching of the interlayer dielectric layer 300 between the source / drain plugs 230 and the gate plug 240 to form a trench, the barrier layer 340 also protects the sidewalls of the source / drain plugs 230 and the gate plug 240, thereby reducing the probability of damage to the source / drain plugs 230 and the gate plug 240. In this embodiment, the material of the barrier layer 340 includes one or both of titanium nitride and tantalum nitride. The material of the interlayer dielectric layer and the material of the barrier layer 340 have a high etching selectivity, resulting in a lower probability of damage to the barrier layer 340 during the re-etching of the interlayer dielectric layer.

[0068] Specifically, the step of forming the barrier layer 340 includes: forming a barrier material layer conformally covering the bottom and sidewalls of the source / drain contact hole 235, the bottom and sidewalls of the gate contact hole 245, and the top of the interlayer dielectric layer 300; removing the barrier material layers located at the top of the interlayer dielectric layer 300, the bottom of the source / drain contact hole 235, and the bottom of the gate contact hole 245, and retaining the remaining barrier material layers located at the sidewalls of the source / drain contact hole 235 and the sidewalls of the gate contact hole 245 as the barrier layer 340. By removing the barrier material layers located at the bottom of the source / drain contact hole 235 and the bottom of the gate contact hole 245, the source / drain plug 230 and the source / drain doped region 220 are in direct contact, and the gate plug 240 is in direct contact with the gate structure 210, thereby reducing the contact resistance.

[0069] Reference Figure 9 and Figure 10 After forming the source / drain plug 230 and the gate plug 240, the method further includes: forming a plug cap layer 350 on top of the source / drain plug 230 and the gate plug 240 (e.g., Figure 10 (As shown).

[0070] During the subsequent etching of the interlayer dielectric layer 300 to form a trench, the plug cap layer 350 serves to protect the tops of the source / drain plug 230 and the gate plug 240, reducing the probability of damage to the source / drain plug 230 and the gate plug 240. Specifically, the steps for forming the plug cap layer 350 include: Figure 9 As shown, by removing a portion of the source / drain plugs 230 and gate plugs 240, a second recess 355 is formed in the interlayer dielectric layer 300; as Figure 10As shown, a plug cap layer 350 is formed in the second groove 325. The second groove 355 provides space for the formation of the plug cap layer 350.

[0071] A portion of the source / drain plugs 230 and 240 is removed by etching. The etching options for the source / drain plugs 230 and 240 and the interlayer dielectric layer 300 are relatively flexible; therefore, a maskless etching method can be used to etch the source / drain plugs 230 and 240, forming a second groove 355. Correspondingly, by forming a plug cap layer 350 in the second groove 355, a photomask can be saved, reducing process costs. Furthermore, this completely covers the top and sidewalls of the source / drain plugs 230 and 240, further reducing the probability of damage to the source / drain plugs 230 and 240. In this embodiment, an anisotropic etching process is used to etch a portion of the source / drain plugs 230 and 240 to form the second groove 355. The longitudinal etching rate of the anisotropic etching process is greater than its lateral etching rate, which is beneficial to improving the sidewall morphology quality of the second groove 355 and to precisely controlling the etching amount of the source / drain plug 230 and the gate plug 240.

[0072] It should be noted that the depth of the second groove 355 should not be too small or too large. If the depth of the second groove 355 is too small, the thickness of the plug cap layer 350 will be too small, which will easily reduce the protective effect of the plug cap layer 350 on the source / drain plug 230 and the gate plug 240. If the depth of the second groove 355 is too large, the remaining height of the source / drain plug 230 and the gate plug 240 will be too small, which will affect the resistance of the source / drain plug 230 and the gate plug 240, and thus affect the performance of the semiconductor structure. Therefore, in this embodiment, the depth of the second groove 355 is 5 nanometers to 20 nanometers.

[0073] In this embodiment, the step of forming the plug cap layer 350 in the second groove 355 includes: forming a plug cap material layer in the second groove 355, the plug cap material layer also covering the top of the interlayer dielectric layer 300; using the top of the interlayer dielectric layer 300 as the stop position, planarizing the plug cap material layer, and retaining the plug cap material layer in the second groove 355 as the plug cap layer 350. As an example, a chemical mechanical polishing process is used to planarize the plug cap material layer. In this embodiment, the material of the plug cap layer 350 includes one or both of titanium nitride and tantalum nitride. The interlayer dielectric layer 300 and the plug cap layer 350 have a high etching selectivity ratio. Therefore, during the subsequent etching of the interlayer dielectric layer 300 to form a trench, the probability of damage to the plug cap layer 350 is low, thereby making the plug cap layer 350 provide better protection for the tops of the source / drain plugs 230 and the gate plug 240.

[0074] refer to Figure 11 The interlayer dielectric layer 300 between the source / drain plug 230 and the gate plug 240 is etched, so that the opposite sidewalls of the source / drain plug 230 and the gate plug 240 form a trench 290 with the substrate 200.

[0075] The trench 290 provides space for the subsequent formation of a sealing medium layer. Specifically, the top of the trench 290 is subsequently sealed with a sealing layer to form an air gap. That is, the trench 290 prepares for the subsequent formation of an air gap between the source / drain plug 230 and the gate plug 240.

[0076] Specifically, the step of etching the interlayer dielectric layer 300 between the source / drain plug 230 and the gate plug 240 includes: thinning the interlayer dielectric layer 300 using an etching process to remove a portion of the thickness of the interlayer dielectric layer 300. The interlayer dielectric layer 300 has a high etching selectivity compared to other film layers. By thinning the interlayer dielectric layer 300 using an etching process, a maskless etching method can be used to etch the interlayer dielectric layer 300. Therefore, the process of forming the trench 290 does not require a photomask, thus reducing process costs. Furthermore, by performing global etching on the interlayer dielectric layer 300, the process feasibility is higher. In this embodiment, the spacing between the source / drain plug 230 and the gate plug 240 is typically small. Therefore, an isotropic etching process is used to etch the interlayer dielectric layer 300, which facilitates the complete removal of the interlayer dielectric layer 300 between the source / drain plug 230 and the gate plug 240. Simultaneously, it is easier to improve the etching selectivity between the interlayer dielectric layer 300 and other film layers. Specifically, a remote plasma etching process is employed to etch the interlayer dielectric layer 300. Remote plasma etching exhibits isotropic etching characteristics and good etching selectivity, thereby reducing damage to other film layers during the etching process. The principle of remote plasma etching involves generating plasma outside the etching chamber (e.g., through a remote plasma generator), then introducing it into the etching chamber and utilizing the chemical reaction between the plasma and the layer to be etched for etching. This achieves an isotropic etching effect, and because there is no ion bombardment, damage to other film layers is minimized.

[0077] In the step of etching the interlayer dielectric layer 300 with the surface normal direction of the substrate 200 as the longitudinal direction, the longitudinal etching depth of the interlayer dielectric layer 300 should not be too small. If the longitudinal etching depth of the interlayer dielectric layer 300 is too small, it will be difficult to provide sufficient space for the formation of air gaps, that is, it will be difficult to form air gaps between the source / drain plugs 230 and the gate plugs 240, which will make it difficult to reduce the capacitance between the gate structure 210 and the source / drain plugs 230. Therefore, in this embodiment, the longitudinal etching depth of the interlayer dielectric layer 300 is at least 20 nanometers. The larger the longitudinal etching depth of the interlayer dielectric layer 300, the greater the required process time and cost. Therefore, in order to reduce process time and cost, and at the same time make the effect of reducing the capacitance between the gate structure 210 and the source / drain plugs 230 more significant, the longitudinal etching depth of the interlayer dielectric layer 300 is 20 nanometers to 100 nanometers. In other embodiments, the interlayer dielectric layer is completely removed after etching, depending on the initial thickness of the interlayer dielectric layer and the longitudinal etching amount. In this embodiment, after etching the interlayer dielectric layer 300, the bottom of the trench 290 is exposed above the top of the sidewall structure 280.

[0078] Reference Figure 12 The forming method further includes: etching the sidewall structure 280 exposed by the trench 290 to reduce the height of the sidewall structure 280.

[0079] The sidewall structure 280 is made of a material with a high dielectric constant. Therefore, by reducing the height of the sidewall structure 280, it is beneficial to further reduce the capacitance between the gate structure 210 and the source / drain plug 230. In this embodiment, the materials of the sidewall layer 281 and the contact hole etch stop layer 282 both have high dielectric constants. By making the tops of the sidewall layer 281 and the contact hole etch stop layer 282 lower than the top of the gate structure 210, the effect of reducing the capacitance between the gate structure 210 and the source / drain plug 230 is more significant.

[0080] In this embodiment, the space of the trench 290 is typically small. Therefore, an isotropic etching process is used to etch the sidewall structure 280 exposed by the trench 290, thereby facilitating the etching of the sidewall structure 280 through the trench 290 and improving the etching selectivity between the sidewall structure 280 and other film layers. In this embodiment, a remote plasma etching process is used to etch the sidewall structure 280, thereby reducing damage to other film layers during the etching process.

[0081] It should be noted that in the step of etching the sidewall structure 280 exposed by the trench 290, the reduction in height of the sidewall structure 280 should not be too small, otherwise it will be difficult to further reduce the capacitance between the gate structure 110 and the source / drain plug 130. Therefore, the reduction in height of the sidewall structure 280 is at least 5 nanometers. However, increasing the etching amount of the sidewall structure 280 will correspondingly increase the time and cost required to etch the sidewall structure 280, and may easily lead to damage to the source / drain doped region 220. Therefore, considering the above aspects, the reduction in height of the sidewall structure 280 is 5 nanometers to 40 nanometers. For example, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, or 35 nanometers. As an example, after removing part of the height of the sidewall structure 280, the top of the remaining sidewall structure 280 is flush with the top of the fin 202. It should be noted that in other embodiments, depending on the initial height and etching amount of the sidewall structure, the entire height of the sidewall structure can also be removed.

[0082] Reference Figure 13 and Figure 14 In trench 290 (e.g.) Figure 12 A sealing medium layer 260 is formed in the (as shown) Figure 14 As shown, the sealing dielectric layer 260 seals the top of the trench 290, and an air gap 265 is formed in the sealing dielectric layer 260 within the trench 290. The sealing dielectric layer 260 is used to seal the top of the trench 290, thereby forming an air gap 265 located between the source / drain plug 230 and the gate plug 240. The sealing dielectric layer 260 also serves to isolate the source / drain plug 230 and the gate plug 240.

[0083] In this embodiment, by forming a trench 290 and sealing the top of the trench 290 with a sealing dielectric layer 260 to form an air gap 265, an air gap 265 is formed between the source / drain plug 230 and the gate plug 240, thereby reducing the capacitance between the gate structure 210 and the source / drain plug 230. Furthermore, before forming the source / drain plug 230 and the gate plug 240, no air sidewalls are formed between the sidewall of the gate structure 210 and the interlayer dielectric layer 300. Therefore, during the formation of the source / drain plug 230 or the gate plug 240, the probability of the material of the source / drain plug 230 or the gate plug 240 filling to the sidewall position of the gate structure 210 is reduced, thereby reducing the probability of a short circuit occurring between the source / drain doped region 220 and the gate structure 210. In summary, after forming the source / drain plug 230 and the gate plug 240, this embodiment forms an air gap 265 between the source / drain plug 230 and the gate plug 240. This not only reduces the probability of short circuits occurring between the source / drain doped region 220 and the gate structure 210, but also reduces the capacitance between the gate structure 210 and the source / drain plug 230, thereby improving the performance of the semiconductor structure, for example, improving the AC performance of the semiconductor structure.

[0084] In this embodiment, the interlayer dielectric layer 300 is thinned using an etching process to form a trench 290. Therefore, in the step of forming a sealing dielectric layer 260 in the trench 290, the sealing dielectric layer 260 is also formed on the remaining interlayer dielectric layer 300 on the sides of the source / drain plug 230 and the gate plug 240. Specifically, the step of forming the sealing dielectric layer 260 includes: as follows Figure 13 As shown, a sealing dielectric material layer 261 is formed covering the gate plug 240 and the source / drain plug 230. The sealing dielectric material layer 261 is also formed in the trench 290 and seals the top of the trench 290, forming an air gap 265. The top of the air gap 265 is lower than the top of the gate plug 240 and the source / drain plug 230. Figure 14 As shown, the sealing medium material layer 261 is planarized to form a sealing medium layer 260 that exposes the top surface of the gate plug 240 and the top surface of the source / drain plug 230.

[0085] In this embodiment, a chemical vapor deposition (CVD) process is used to form the sealing dielectric material layer 261. By employing CVD, it is easy to pre-seal the top of the trench 290 before it completely fills the trench, forming an air gap 265. Furthermore, the CVD process has a lower deposition temperature, which helps reduce the impact on transistor performance. In other embodiments, to ensure the sealing dielectric layer seals the top of the trench and forms an air gap, a furnace tube process can also be used to form the sealing dielectric material layer. In this embodiment, a chemical mechanical polishing (CMP) process is used to planarize the sealing dielectric material layer 261. The sealing dielectric layer 260 exposes the top surfaces of the source / drain plugs 230 and the gate plug 240; therefore, during the planarization process of the sealing dielectric material layer 261, the plug cap layer 350 (e.g., ...) is also removed. Figure 13 (As shown). By exposing the top surfaces of the gate plug 240 and the source / drain plug 230 with the sealing dielectric layer 260, preparation is made for the subsequent formation of metal interconnects that electrically connect to the gate plug 240 and the source / drain plug 230; correspondingly, the material of the intermetallic dielectric layer can be flexibly selected to meet the performance requirements of the semiconductor structure. In other embodiments, the sealing dielectric layer may also cover the top of the gate plug and the source / drain plug, so that the sealing dielectric layer above the top of the gate plug and the source / drain plug serves as the intermetallic dielectric layer, simplifying the process steps of the subsequent fabrication. Correspondingly, the plug cap layer may also be retained.

[0086] The sealing dielectric layer 260 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the sealing dielectric layer 260 is made of silicon oxide. Silicon oxide has appropriate hardness, which helps reduce the probability of damage to the sealing dielectric layer 260 in subsequent processes. The appropriate dielectric constant of silicon oxide results in a smaller capacitance between the source / drain plug 230 and the gate structure 210. In other embodiments, to further reduce the capacitance between the source / drain plug and the gate structure, the sealing dielectric layer can also be made of a low-k dielectric material or an ultra-low-k dielectric material.

[0087] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and fins protruding from the substrate; A gate structure is located on the substrate; A sidewall structure, comprising a sidewall covering a portion of the height of the gate structure, wherein the top of the sidewall structure is lower than the top of the gate structure; The source / drain doped regions are located in the substrate on both sides of the gate structure. The top of the sidewall structure and the top of the fin are flush, and the sidewall structure is located between the source / drain doped regions and the gate structure. A source / drain plug is located at the top of and connected to the source / drain doped region, and the bottom of the source / drain plug is lower than the top of the gate structure. A gate plug is located on top of the gate structure and connected to the gate structure. The gate plug is disposed opposite to the sidewall of the source / drain plug. The opposite sidewall of the source / drain plug and the gate plug, the top of the source / drain doped region exposed by the source / drain plug, the top of the sidewall structure, and the opposite sidewall of the source / drain plug and the gate structure exposed in the sidewall structure form a trench with the substrate. A sealing medium layer is located in the trench and seals the top of the trench, and the sealing medium layer in the trench has an air gap.

2. The semiconductor structure as described in claim 1, characterized in that, The sealing medium layer is also located on the substrate on the side of the source / drain plug and the gate plug.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes an interlayer dielectric layer located between the bottom of the sealing dielectric layer and the substrate.

4. The semiconductor structure as described in claim 3, characterized in that, The distance from the top of the interlayer dielectric layer to the top of either the source / drain plug or the gate plug is 15 nanometers to 95 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a gate cap layer located on top of the exposed gate structure of the gate plug.

6. The semiconductor structure as described in claim 5, characterized in that, The thickness of the gate cap layer is 3 nanometers to 20 nanometers.

7. The semiconductor structure as described in claim 5, characterized in that, The material of the gate cap layer includes one or both of titanium nitride and tantalum nitride.

8. The semiconductor structure as described in claim 1, characterized in that, The sidewall structure includes a sidewall layer covering the sidewall of the gate structure and a contact hole etch stop layer covering the sidewall of the sidewall layer.

9. The semiconductor structure as described in claim 1, characterized in that, The distance from the top of the sidewall structure to the top of the gate structure is 5 nanometers to 20 nanometers.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the sealing medium layer includes silicon oxide, low-k medium material, or ultra-low-k medium material.

11. The semiconductor structure as claimed in claim 1, characterized in that, The top linewidth of the source / drain plug is greater than the bottom linewidth, and the top linewidth of the gate plug is greater than the bottom linewidth.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate structure is formed, a sidewall structure is formed on the sidewall of the gate structure, source and drain doped regions are formed in the substrate on both sides of the gate structure, an interlayer dielectric layer is formed on the substrate on the side of the gate structure, the interlayer dielectric layer covers the top of the gate structure, and the substrate includes a substrate and fins protruding from the substrate. An interlayer dielectric layer is formed that penetrates above the top of the source / drain doped region and is connected to the source / drain doped region, and a gate plug is formed that penetrates above the top of the gate structure and is connected to the gate structure. The gate plug and the sidewall of the source / drain plug are disposed opposite to each other, and the sidewall structure is located between the source / drain doped region and the gate structure. The interlayer dielectric layer between the source / drain plug and the gate plug is etched to form a trench between the opposite sidewalls of the source / drain plug and the gate plug and the substrate, with the bottom of the trench exposed above the top of the sidewall structure. The sidewall structure exposed by the trench is etched to reduce the height of the sidewall structure, and the top of the sidewall structure is flush with the top of the fin; in the step of etching the sidewall structure exposed by the trench, the trench is formed by at least the opposing sidewalls of the source / drain plug and the gate plug, the top of the source / drain doped region exposed by the source / drain plug, the top of the sidewall structure, and the opposing sidewalls of the source / drain plug and the gate structure exposed in the sidewall structure, together with the substrate; After etching the sidewall structure exposed by the trench, a sealing medium layer is formed in the trench, the sealing medium layer seals the top of the trench, and an air gap is formed in the sealing medium layer in the trench.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, a gate cap layer is formed on top of the gate structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, Before the interlayer dielectric layer is formed, a bottom dielectric layer is formed on the substrate of the side of the gate structure, and the bottom dielectric layer covers the sidewall of the gate structure; Before forming the interlayer dielectric layer, the forming method further includes: removing a portion of the height of the gate structure to form a first groove in the bottom dielectric layer; forming the gate cap layer in the first groove; the step of forming the interlayer dielectric layer includes: forming a top dielectric layer covering the gate cap layer and the bottom dielectric layer, the top dielectric layer and the bottom dielectric layer constituting the interlayer dielectric layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the first groove, the depth of the first groove is 3 nanometers to 20 nanometers.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the source / drain plug and the gate plug, and before forming the trench, the forming method further includes: forming a plug cap layer on top of the source / drain plug and the gate plug.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the plug cap layer includes: removing a portion of the height of the source / drain plug and gate plug, forming a second groove in the interlayer dielectric layer; and forming the plug cap layer in the second groove.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the step of forming the second groove, the depth of the second groove is 5 nanometers to 20 nanometers.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the plug cap layer includes one or both of titanium nitride and tantalum nitride.

20. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of etching the interlayer dielectric layer between the source / drain plug and the gate plug includes: thinning the interlayer dielectric layer using an etching process to remove a portion of the thickness of the interlayer dielectric layer; in the step of forming a sealing dielectric layer in the trench, the sealing dielectric layer is also formed on the remaining interlayer dielectric layer on the sides of the source / drain plug and the gate plug.

21. The method for forming a semiconductor structure as described in claim 12 or 20, characterized in that, In the step of etching the interlayer dielectric layer, the longitudinal etching depth of the interlayer dielectric layer is 20 nanometers to 100 nanometers.

22. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, the sidewall structure includes a sidewall layer covering the sidewall of the gate structure and a contact hole etch stop layer covering the sidewall of the sidewall layer.

23. The method for forming a semiconductor structure as described in claim 12, characterized in that, An isotropic etching process is used to etch the sidewall structure exposed by the trench.

24. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of etching the sidewall structure, the height of the sidewall structure is reduced by 5 nanometers to 40 nanometers.

25. The method for forming a semiconductor structure as described in claim 12, characterized in that, The interlayer dielectric layer is etched using an isotropic etching process.

26. The method for forming a semiconductor structure as described in claim 23 or 25, characterized in that, The isotropic etching process includes remote plasma etching.

27. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of forming the source / drain plug and the gate plug, the top linewidth dimension of the source / drain plug is larger than the bottom linewidth dimension, and the top linewidth dimension of the gate plug is larger than the bottom linewidth dimension.

28. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the sealing dielectric layer includes: forming a sealing dielectric material layer covering the gate plug and the source / drain plug, the sealing dielectric material layer also being formed in the trench and sealing the top of the trench to form an air gap, the top of the air gap being lower than the top of the gate plug and the source / drain plug; and planarizing the sealing dielectric material layer to form a sealing dielectric layer exposing the top surface of the gate plug and the top surface of the source / drain plug.

29. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the sealing medium layer includes chemical vapor deposition or furnace tube process.

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