Power semiconductor device and applications thereof

Abstract

This invention discloses a power semiconductor device and its application. The power semiconductor device includes: a substrate, within which a first metal region, a source region, a gate oxide dielectric layer, and a gate electrode region are disposed. The gate oxide dielectric layer surrounds the gate electrode region. The source region is located between the first metal region and the gate oxide dielectric layer, and its sidewalls are in contact with both the first metal region and the gate oxide dielectric layer. The surfaces of the first metal region, the source region, the gate oxide dielectric layer, and the gate electrode region are flush with one side surface of the substrate. The substrate and the source region have the same conductivity type, and the work function of the substrate material is less than that of the first metal region material. An insulating dielectric layer is disposed on the gate oxide dielectric layer, the gate electrode region, and the source region. In the above power semiconductor device structure, a Schottky diode is formed between the first metal region and the substrate, avoiding bipolar degradation and depleting the drift region of the gate electrode region, making the semiconductor device a normally closed device and reducing leakage current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a power semiconductor device and its applications. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are a new generation of power electronic switching devices developed based on the integrated circuit technology of metal-oxide-semiconductor field-effect transistors. They meet the requirements of high power and high current of power equipment based on microelectronic technology.

[0003] like Figure 1 As shown, a conventional trench MOSFET device 10 includes a substrate 110 and a drift region 111 of a first conductivity type, a base region 120 of a second conductivity type, a source region 112 of a first conductivity type, a drain electrode 130, a source electrode 131, a gate electrode 113, a gate oxide dielectric 132, and an insulating dielectric 133. The operating mode of the above-mentioned trench MOSFET device can be described as follows: When a voltage below a threshold voltage is applied to the gate electrode 113, the drain electrode 130 can withstand a relatively large positive voltage relative to the source electrode 131, and the current through the source electrode 131 and the drain electrode 130 is very small. When the voltage applied to the gate electrode 113 is greater than the threshold voltage, an inversion layer is formed near the interface between the base region 120 and the gate oxide dielectric 132, allowing a relatively large current to pass between the source electrode and the drain electrode. However, due to the high interface state density at the interface between the base region 120 and the gate oxide dielectric 132, the trench MOSFET device has a relatively large on-resistance. Figure 2 As shown, a structure that can reduce the on-resistance of a device is called an accumulation-type metal-oxide-semiconductor field-effect transistor device 20, and... Figure 1 Compared to the illustrated structure, this structure lacks a base region of the second conductivity type. The operating mode of the aforementioned accumulation-type metal-oxide-semiconductor field-effect transistor device can be described as follows: When the voltage applied to the gate electrode 213 relative to the source electrode 231 is lower than the threshold voltage, the work function difference between the gate electrode 213 and the drift region 211 can completely deplete the drift region 211 between the two gate electrodes 213, allowing the drain electrode 230 to withstand a relatively large voltage relative to the source electrode 231 while the current flowing through them is very small. When the voltage applied to the gate electrode 213 is greater than the threshold voltage, an accumulated electron layer 220a appears near the gate dielectric 232, enabling the device to obtain a larger on-state current. Typically... Figure 2 The on-resistance of the device shown in the example is lower than Figure 1 The example device, but to make Figure 2 If the device in the middle becomes a normally closed device commonly used in practice, then the distance between the gate electrodes 213 must be very small (e.g., 0.2μm), and such a small distance is difficult to achieve in terms of manufacturing process. Summary of the Invention

[0004] Therefore, it is necessary to provide a power semiconductor device that is simple to manufacture and is normally closed, and its application.

[0005] This invention provides a power semiconductor device, comprising:

[0006] A substrate is provided with a first metal region, a source region, a gate oxide dielectric layer, and a gate electrode region. The gate oxide dielectric layer surrounds the gate electrode region. The source region is located between the first metal region and the gate oxide dielectric layer, and the sidewalls of the source region are in contact with the first metal region and the gate oxide dielectric layer, respectively. The surfaces of the first metal region, the source region, the gate oxide dielectric layer, and the gate electrode region are flush with one side surface of the substrate. The substrate and the source region have the same conductivity type. The work function of the material of the substrate is less than the work function of the material of the first metal region.

[0007] An insulating dielectric layer is disposed on the gate oxide dielectric layer, the gate electrode region, and the source region.

[0008] In one embodiment, a second metal region is further included, which is disposed on the side of the first metal region away from the substrate. The work function of the material in the second metal region is greater than the work function of the material in the substrate, and the work function of the material in the second metal region is less than the work function of the material in the first metal region.

[0009] In one embodiment, the substrate includes a substrate and a drift region disposed on the substrate, wherein the first metal region, the source region, the gate oxide dielectric layer and the gate electrode region are disposed in the drift region and their surfaces are flush with the surface of the drift region on the side away from the substrate.

[0010] In one embodiment, the material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride, and gallium oxide.

[0011] In one embodiment, the substrate has a doping concentration of 10. 18 cm -3 ~10 20 cm -3 The doping concentration of the drift region is 10. 14 cm -3 ~1×10 18 cm -3 .

[0012] In one embodiment, the gate electrode region material is selected from at least one of polycrystalline silicon, silicon carbide, and metallic materials.

[0013] In one embodiment, the depth of the source region is shallower than that of the first metal region.

[0014] In one embodiment, the depth of the first metal region is shallower than that of the gate electrode region.

[0015] In one embodiment, a source electrode region and a drain electrode region are further included, wherein the source electrode region is formed on the insulating dielectric layer, and the drain electrode region is formed on the side of the substrate away from the insulating dielectric layer.

[0016] Furthermore, the present invention also provides an electronic product comprising the power semiconductor device as described above.

[0017] In the aforementioned power semiconductor device structure, a Schottky diode is formed between the first metal region and the substrate, eliminating the parasitic PN junction diode found in traditional devices and avoiding bipolar degradation. Furthermore, the formed Schottky diode can deplete the drift region near the gate electrode region, making the semiconductor device a normally closed device and reducing leakage current. The device fabrication process is simple, directly utilizing the formed drift region as an accumulation channel. The Schottky diode can also function as a freewheeling diode in applications, and it does not occupy additional area, reducing device cost. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a traditional trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device.

[0019] Figure 2 This is a schematic diagram of a traditional accumulation-type metal-oxide-semiconductor field-effect transistor (MOSFET) device.

[0020] Figure 3 A schematic diagram of the structure of the power semiconductor device provided by the present invention;

[0021] The symbols in the attached image are explained as follows:

[0022] 10: Traditional trench metal-oxide-semiconductor field-effect transistor device; 110: Substrate; 111: Drift region; 112: Source region of the first conductivity type; 113: Gate electrode; 120: Base region of the second conductivity type; 130: Drain electrode; 131: Source electrode; 132: Gate oxide dielectric; 133: Insulating dielectric.

[0023] 20: Accumulation type metal-oxide-semiconductor field-effect transistor device; 210: Substrate; 211: Drift region; 212: Source region of first conductivity type; 213: Gate electrode; 220a: Accumulation electron layer; 230: Drain electrode; 231: Source electrode; 232: Gate oxide dielectric; 233: Insulating dielectric.

[0024] 30: Power semiconductor device; 301: Source electrode region; 302: Insulating dielectric layer; 303: Source region; 304: First metal region; 305: Second metal region; 306: Gate electrode region; 307: Gate oxide dielectric layer; 308: Drift region; 309: Substrate; 310: Drain electrode region. Detailed Implementation

[0025] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of the present invention, "a number" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0027] The terms "preferred," "more preferably," etc., used in this invention refer to embodiments of the invention that provide certain beneficial effects under certain circumstances. However, other embodiments may also be preferred under the same or other circumstances. Furthermore, the description of one or more preferred embodiments does not imply that other embodiments are unavailable, nor is it intended to exclude other embodiments from the scope of this invention.

[0028] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.

[0029] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0030] When using “including,” “having,” and “contains” as described herein, the intention is to cover non-exclusive inclusion, unless an explicit qualifying term such as “only,” “consisting of,” etc., is used, in which case another component may be added.

[0031] Unless otherwise stated, a singular term may include a plural term and should not be understood as having a quantity of one.

[0032] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the elements are shown in the drawings only as examples to facilitate understanding of the invention, but are not necessarily drawn to actual scale. The scale in the drawings does not constitute a limitation on the invention. It should be noted that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an inserting component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no inserting component. Similarly, when the first component is referred to as "electrically contacting" or "electrically coupling" to the second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between the conductive components.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] like Figure 1 As shown, the present invention provides a power semiconductor device 30, comprising: a substrate, wherein a first metal region 304, a source region 303, a gate oxide dielectric layer 307 and a gate electrode region 306 are disposed within the substrate, the gate oxide dielectric layer 307 surrounds the gate electrode region 306, the source region 303 is located between the first metal region 304 and the gate oxide dielectric layer 307 and the sidewalls of the source region 303 are respectively in contact with the first metal region 304 and the gate oxide dielectric layer 307, the surfaces of the first metal region 304, the source region 303, the gate oxide dielectric layer 307 and the gate electrode region 306 are flush with the same side surface of the substrate, the substrate and the source region 303 have the same conductivity type, wherein the work function of the material of the substrate is less than the work function of the material of the first metal region;

[0035] An insulating dielectric layer 302 is disposed on the gate oxide dielectric layer 307, the gate electrode region 306, and the source region 303.

[0036] Understandably, when the first metal region material and the substrate semiconductor material come into contact, depletion occurs, forming a depletion region on the semiconductor surface. Within a certain width, there are almost no mobile electrons. Therefore, electrons do not easily travel between the semiconductor and the metal, thus forming a Schottky contact.

[0037] In a specific example, a second metal region 305 is also included. The second metal region 305 is disposed on the side of the first metal region 304 away from the substrate. The work function of the material of the second metal region 305 is greater than the work function of the material of the substrate, and the work function of the material of the second metal region 305 is less than the work function of the material of the first metal region 304.

[0038] In a specific example, the substrate includes a substrate 309 and a drift region 308 disposed on the substrate. A first metal region 304, a source region 303, a gate oxide dielectric layer 307 and a gate electrode region 306 are disposed in the drift region 308, and their surfaces are flush with the surface of the drift region 308 on the side away from the substrate 309.

[0039] In one specific example, the material of the substrate 309 and the material of the drift region 308 are selected from at least one of silicon carbide, gallium nitride, and gallium oxide.

[0040] In one specific example, the doping concentration of substrate 309 is 10. 18 cm -3 ~10 20 cm -3 The doping concentration of drift region 308 is 10. 14 cm -3 ~1×10 18 cm -3 .

[0041] In one specific example, the gate electrode region 306 material is selected from at least one of polycrystalline silicon, silicon carbide, and metallic materials.

[0042] In a specific example, the source region 303 is shallower than the first metal region 304.

[0043] In one specific example, the depth of the first metal region 304 is shallower than that of the gate electrode region 306.

[0044] In one specific example, a source electrode region 301 and a drain electrode region 310 are also included, wherein the source electrode region 301 is formed on the insulating dielectric layer 302, and the drain electrode region 310 is formed on the side of the substrate away from the insulating dielectric layer 302.

[0045] In the aforementioned power semiconductor device structure, a Schottky diode is formed between the first metal region 304 and the substrate, eliminating the parasitic PN junction diode found in traditional devices and avoiding bipolar degradation. Furthermore, the formed Schottky diode can deplete the drift region near the gate electrode region, making the semiconductor device normally closed and reducing leakage current. Moreover, the device fabrication process provided by this invention is simple, directly utilizing the formed drift region as an accumulation channel. The Schottky diode can act as a freewheeling diode in applications, and it does not occupy additional area, reducing device cost.

[0046] Understandably, metal-oxide-semiconductor field-effect transistors (MOSFETs) are generally controlled to be in a conducting or blocking state by the gate voltage. When no voltage is applied to the gate, if the device can be in a blocking state (withstand high voltage), then the device is a normally closed device. Conversely, if the device cannot be in a blocking state when no voltage is applied to the gate (i.e., the device cannot withstand high voltage), but a large current flows through it, then the device is a normally open device. Therefore, normally closed devices are usually used in practical applications. The Schottky diode formed in the power semiconductor device provided by this invention can also deplete the drift region of the gate electrode, making the semiconductor device a normally closed device.

[0047] In metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the drift and source regions are typically composed of n-type doped materials with high electron concentrations. These regions are separated by a channel. When the device is in the blocking state, the channel contains almost no electrons, preventing electron flow from the source to the drift region. Since the channel is usually p-type doped, it is electron-free in the blocking state. When a voltage greater than a threshold voltage is applied to the gate, the energy band of the p-type semiconductor material bends downwards, forming a layer with a high electron concentration in the channel (this can be considered as the positive charge of the gate attracting electrons). The semiconductor appears to have "reversed" from p-type to n-type doping, forming an inverted channel layer. With a high electron concentration in the channel, the source and drift regions are connected, allowing current to flow. Of course, the channel can also be n-type doped, in which case electrons are present in the drift, channel, and source regions, resulting in a normally-on device. Therefore, semiconductor devices require special design to ensure the channel is completely depleted (i.e., devoid of electrons) even without a gate voltage, thus achieving a normally-closed device. Figure 2 In traditional semiconductor devices, the channel is depleted through a shielding region beneath it. In this invention, the drift region near the depleted gate electrode region in the semiconductor device can be directly utilized as an accumulation channel. When a voltage greater than a threshold is applied to the gate, electrons in the channel recover and their concentration increases beyond that before depletion, effectively "accumulating" electrons to form an accumulation channel.

[0048] The semiconductor device operation mode provided by this invention can be described as follows: When the semiconductor device is under zero bias, since the work function of the gate electrode region 306 and the first metal region 304 is greater than the work function of the drift region 308, this work function difference can deplete the drift region near the gate electrode region 306 and the first metal region 304, specifically as follows... Figure 3 The depletion region is formed within the area enclosed by the dashed line. The presence of the depletion region makes the semiconductor device of this invention a normally closed device. When a voltage of 0V is applied to the source electrode region 301 and a voltage of 0V is applied to the gate electrode region 306, the drain electrode region 310 can withstand a relatively large voltage with almost no current flowing through the device, and the semiconductor device is in a high-voltage blocking state. When a voltage of 0V is applied to the source electrode region 301 and a voltage greater than the threshold voltage is applied to the gate electrode region 306, if a voltage greater than 0V is applied to the drain electrode region 310, electrons can flow from the source electrode region 301 to the drain electrode region 310, putting the semiconductor device in a conducting state. By controlling the voltage applied to the gate electrode region 306, the semiconductor device can switch between the high-voltage blocking state and the conducting state.

[0049] Compared to traditional semiconductor device structures, the semiconductor device structure provided by this invention integrates a Schottky diode between the gate and the semiconductor device, eliminating the parasitic PN junction diode found in traditional devices and avoiding bipolar degradation. The Schottky diode can also deplete the drift region 308 near the gate, making the device normally closed and reducing leakage current. The device fabrication process is simple, and the Schottky diode does not occupy additional area, reducing device cost.

[0050] Furthermore, the present invention also includes a second metal region 305, and the semiconductor device 30 includes a first Schottky contact metal of the first metal region 304 and a second Schottky contact metal of the second metal region 305. The work functions of the first Schottky contact metal and the second Schottky contact metal are different; the work function of the first Schottky contact metal of the first metal region 304 is greater than the work function of the second Schottky contact metal of the second metal region 305. A larger work function of the first Schottky contact metal results in a larger depletion region in the drift region, allowing the semiconductor device to achieve lower leakage current. The work function of the second Schottky contact metal determines the turn-on voltage of the Schottky body diode; the smaller the work function of the second Schottky contact metal, the smaller the turn-on voltage of the Schottky body diode. The arrangement of the first and second Schottky contact metals increases the design flexibility of the semiconductor device of the present invention.

[0051] Furthermore, the present invention also provides an electronic product comprising the power semiconductor device as described above.

[0052] Understandably, the aforementioned electronic products include, but are not limited to, electronic components such as integrated circuits, resistors, and capacitors.

[0053] The following specific embodiments provide a more detailed description of the semiconductor power device of the present invention. It will be understood that, unless otherwise specified, all materials involved in the following specific embodiments are commercially available.

[0054] Example 1

[0055] This embodiment provides a method such as Figure 3 The power semiconductor device shown is fabricated as follows:

[0056] S110, having a first conductivity type, is doped with nitrogen or phosphorus as the impurity, and the doping concentration is 10. 18 cm -3 ~10 20 cm -3 On the Si surface of a silicon carbide substrate 309 with a thickness of 320μm to 380μm, a material with a first conductivity type is grown via homoepitaxial growth, and the doping impurities are nitrogen or phosphorus with a doping concentration of 10. 14 ~10 18 cm -3 308, a silicon carbide drift region with a thickness of 5μm to 200μm;

[0057] S120 is formed on the side of the silicon carbide drift region 308 away from the substrate 100 by homoepitaxial growth of silicon carbide or high-temperature ion implantation, having a first conductivity type, and the doped impurities are nitrogen or phosphorus, with a doping concentration of 10. 18 cm -3 ~10 20 cm -3 The source region 303 has a thickness of 0.1–1 μm.

[0058] In step S130, on the side of the silicon carbide drift region 308 away from the substrate 100, trenches for accommodating the gate oxide dielectric layer 307 are etched downwards using photolithography and plasma etching. The trench depth is 0.5–10 μm. A dense silicon oxide layer with a thickness of 10–100 nm is formed on the surface of the trenches in the gate electrode region 306 as the gate oxide dielectric layer 307 using a high-temperature thermal oxidation combined with oxidation and annealing process or a low-pressure chemical vapor deposition (LPCVD) method. Then, using chemical vapor deposition, doped impurities of a second conductivity type, either aluminum or boron, are deposited and filled on the surface of the gate oxide dielectric layer 307 within the trenches of the gate electrode region 306, with a doping concentration of 10⁻⁶. 18 cm -3 ~10 22 cm -3 After filling is completed, excess silicon oxide on the source region 303 and drift region 308 is removed by photolithography and etching / etching.

[0059] S140, at the positions corresponding to the first metal region 304 and the second metal region 305 on the drift region 308, trenches for the first metal region 304 and the second metal region 305 are etched downwards by photolithography and plasma etching; the metals of the first metal region 304 and the second metal region 305 are deposited and filled into the etched trenches by processes such as electron beam evaporation or ion sputtering; the work function of the material of the second metal region 305 is greater than the work function of the material of the first metal region 304. Typically, the material of the first metal region 304 can be metals such as Ta (work function 4.25 eV), Ti (work function 4.33 eV), Cr (work function 4.5 eV), or W (work function 4.55 eV), and its thickness is 1 / 2 to 3 / 4 of the thickness of the gate electrode region 306. Typically, the material of the second metal region 305 can be, but is not limited to, Au (work function 5.1 eV), Ni (work function 5.15 eV), or Pt (work function 5.65 eV), and its thickness is 100 to 2000 nm. Then, excess metal formed on the surface of the source region 303, the gate electrode region 306, and the gate oxide dielectric layer 307 is removed by photolithography and plasma etching. In a nitrogen or argon atmosphere in a furnace tube annealing furnace, annealing is carried out at a temperature of 300 to 600°C for 10 to 60 minutes to form the first metal-silicon carbide Schottky contact and the second metal-silicon carbide Schottky contact with the drift region 308, respectively.

[0060] S150, on the surface of the drift region 308 away from the substrate 309, a silicon oxide layer of 0.5 to 2 μm thickness is deposited on it by plasma chemical vapor deposition. The excess silicon oxide is removed by photolithography and plasma etching to form an insulating dielectric layer 302.

[0061] S160, a drain electrode region 310 metal is deposited on the surface (C-plane) of the substrate 309 away from the drift region 308 by processes such as electron beam evaporation or ion sputtering. Ni or Ti metal can be selected, and the thickness is 50-200 nm. A source electrode metal is deposited on the surface of the insulating dielectric layer 302309 by processes such as electron beam evaporation or ion sputtering to form a source electrode 301. Ni or Ti metal can be selected, and the thickness is 50-200 nm. The source metal region 301 is formed by photolithography and etching / etching. By rapidly annealing in a rapid thermal annealing furnace at a temperature of 900-1200°C for 1-5 min in a nitrogen or argon atmosphere, an ohmic contact with low specific contact resistance is formed between the drain metal 310 and the substrate 309 and between the source metal 301 and the source region 303.

[0062] Compared to traditional device structures, the device structure in this embodiment integrates a Schottky diode between the gate and the device, eliminating the parasitic PN diode found in traditional devices and avoiding bipolar degradation. The Schottky diode can also deplete the drift region near the gate, making the device normally closed and reducing leakage current. The device fabrication process provided by this invention is simple, and the formed Schottky diode does not occupy additional area, reducing device cost. Furthermore, the arrangement of the first and second Schottky contact metals in the device structure provided in this embodiment increases the flexibility of device design.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The embodiments described above are merely illustrative of several implementations of the present invention, designed to facilitate a detailed understanding of the technical solutions of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided by the present invention through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this invention patent should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises: a substrate, a first metal region, a source region, a gate oxide dielectric layer and a gate electrode region are arranged in the substrate, the gate oxide dielectric layer surrounds the gate electrode region, the source region is located between the first metal region and the gate oxide dielectric layer, and the sidewall of the source region is in contact with the first metal region and the gate oxide dielectric layer respectively, the surface of the first metal region, the source region, the gate oxide dielectric layer and the gate electrode region is flush with the side surface of the substrate, the substrate and the source region have the same conductive type, the work function of the material of the substrate is less than the work function of the material of the first metal region; an insulating dielectric layer is arranged on the gate oxide dielectric layer, the gate electrode region and the source region; a second metal region is further arranged on the side of the first metal region away from the side flush with the substrate, the work function of the material of the second metal region is greater than the work function of the material of the substrate, and the work function of the material of the second metal region is less than the work function of the material of the first metal region.

2. The power semiconductor device of claim 1, wherein, The substrate comprises a substrate and a drift region arranged on the substrate, the first metal region, the source region, the gate oxide dielectric layer and the gate electrode region are arranged in the drift region, and the surface is flush with the side surface of the drift region away from the substrate.

3. The power semiconductor device of claim 2, wherein, The material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride and gallium oxide.

4. The power semiconductor device of claim 3, wherein, The substrate has a doping concentration of 10 18 cm -3 ~10 20 cm -3 , and the drift region has a doping concentration of 10 14 cm -3 ~1x10 18 cm -3 .

5. The power semiconductor device of claim 1, wherein, The material of the gate electrode region is selected from at least one of polysilicon, silicon carbide and metal material.

6. The power semiconductor device of claim 1, wherein, The depth of the source region is shallower than the first metal region.

7. The power semiconductor device of claim 1, wherein, The depth of the first metal region is shallower than the gate electrode region.

8. The power semiconductor device according to any one of claims 1 to 7, wherein A source electrode region and a drain electrode region are further included, the source electrode region is formed on the insulating dielectric layer, and the drain electrode region is formed on the side of the substrate away from the insulating dielectric layer.

9. An electronic product, characterized by comprising: The power semiconductor device comprises: a substrate, a first metal region, a source region, a gate oxide dielectric layer and a gate electrode region are arranged in the substrate, the gate oxide dielectric layer surrounds the gate electrode region, the source region is located between the first metal region and the gate oxide dielectric layer, and the sidewall of the source region is in contact with the first metal region and the gate oxide dielectric layer respectively, the surface of the first metal region, the source region, the gate oxide dielectric layer and the gate electrode region is flush with the side surface of the substrate, the substrate and the source region have the same conductive type, the work function of the material of the substrate is less than the work function of the material of the first metal region; an insulating dielectric layer is arranged on the gate oxide dielectric layer, the gate electrode region and the source region; a second metal region is further arranged on the side of the first metal region away from the side flush with the substrate, the work function of the material of the second metal region is greater than the work function of the material of the substrate, and the work function of the material of the second metal region is less than the work function of the material of the first metal region. The substrate comprises a substrate and a drift region arranged on the substrate, the first metal region, the source region, the gate oxide dielectric layer and the gate electrode region are arranged in the drift region, and the surface is flush with the side surface of the drift region away from the substrate. The material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride and gallium oxide. The material of the gate electrode region is selected from at least one of polysilicon, silicon carbide and metal material. The depth of the source region is shallower than the first metal region. The depth of the first metal region is shallower than the gate electrode region. A source electrode region and a drain electrode region are further included, the source electrode region is formed on the insulating dielectric layer, and the drain electrode region is formed on the side of the substrate away from the insulating dielectric layer.

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