Power semiconductor device and applications thereof

Abstract

The application discloses a power semiconductor device and application thereof, wherein the device comprises a substrate with opposite first and second surfaces, a contact region, a source region, a shield region and a first floating region are arranged in the substrate, the side surface of the source region and the contact region on one side is flush with the first surface of the substrate, the side surface of the source region and the contact region on the other side is in contact with the shield region, the sidewall of the source region is in contact with the sidewall of the contact region, the source region, the shield region and the substrate wrap the contact region, and the first floating region is closer to the second surface of the substrate than the shield region. The power semiconductor device is designed with the first floating region in the substrate, which can protect the gate dielectric layer and further cooperate with the drift region directly used as the accumulation channel without ion implantation, the shield region and the source region can be formed by using the same ion implantation process, and since the accumulation channel is not subjected to ion implantation, the lattice defects are less, the electron mobility is high, and the on-resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a power semiconductor device and its applications. Background Technology

[0002] Third-generation semiconductors, silicon carbide (SiC) and gallium nitride (GaN), are wide-bandgap semiconductor materials with advantages such as high breakdown electric field strength, good thermal stability, and high carrier saturation drift velocity, making them advantageous for high-power devices. Power semiconductor devices are commonly used in high-voltage, high-current, and high-temperature operating environments, gradually replacing traditional silicon (Si) materials in the field of power electronics. Vertical metal-oxide-semiconductor field-effect transistor (MOSFET) power devices typically refer to a vertical structure device formed on a substrate. It usually includes a substrate and a drift region formed on the substrate, which acts as a drift layer during forward bias and bears the blocking voltage during forward blocking. Vertical MOSFET power devices can be divided into planar devices and trench devices. Planar power devices are simpler to fabricate and therefore have more mature commercial applications. The application of planar power devices is mainly limited by three factors. The first factor is that in the blocking state, the gate dielectric layer of the device is subjected to a very high electric field, which can easily damage the gate dielectric layer and cause device failure. The second factor is the high defect state density of the device channel, resulting in a large on-resistance. The third factor is the presence of a junction field-effect transistor (JFET) region in the device, where the current path is smaller, resulting in a larger on-resistance.

[0003] To reduce on-resistance, such as Figure 1 As shown, a conventional accumulation-type metal-oxide-semiconductor field-effect transistor (MOSFET) device 10 includes a substrate 110 of a first conductivity type, a drift region 109 of a first conductivity type, a shielding region 108 of a second conductivity type, a contact region 105 of a second conductivity type, a source region 106 of a first conductivity type, a base region 107 of a first conductivity type, a gate 103 of a first conductivity type, an insulating dielectric layer 102, and a gate dielectric layer 104. In this structure, the base region 107 uses a material of the first conductivity type. In the blocking state, the base region 107 of the first conductivity type is completely depleted by the shielding region 108 and the gate 103 under zero bias, thereby achieving a normally closed state. When a voltage greater than a threshold voltage is applied to the gate 103, electrons accumulate in the base region 107, turning on the device 10. When the device is in the blocking state, the shielding region 108 of the second conductivity type can shield the electric field at the gate dielectric layer 104, thereby enabling the device to obtain a higher breakdown voltage. However, the source region 106 and the shielding region 108 need to be formed through two different ion implantation processes, and the base region 107 also needs to be formed through a separate ion implantation process. Furthermore, the concentration and depth need to be precisely controlled, making the device manufacturing process quite complex. Summary of the Invention

[0004] Therefore, it is necessary to provide a power semiconductor device and its application that can reduce the fabrication process.

[0005] This invention provides a power semiconductor device, comprising:

[0006] The substrate has a first surface and a second surface facing each other. The substrate contains a contact area, a source area, a shielding area, and a first floating area. One side surface of the source area and the contact area is flush with the first surface of the substrate. The other side surface of the source area and the contact area contacts the shielding area. The sidewall of the source area contacts the sidewall of the contact area. The source area, the shielding area, and the substrate surround the contact area. The first floating area is closer to the second surface of the substrate than the shielding area.

[0007] A gate dielectric layer is disposed on the first surface of the source region and the substrate, and the first floating region is located directly below the gate dielectric layer;

[0008] A gate, wherein the gate is disposed on the gate dielectric layer;

[0009] The source region has a first conductivity type, and the contact region, the first floating region, and the shielding region have a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

[0010] In one embodiment, a leakage current limiting region is further included, the leakage current limiting region being disposed in the substrate, the sidewalls of the shielding region and the source region being in contact with the sidewalls of the leakage current limiting region, one side surface of the contact region, the source region and the leakage current limiting region being flush with a first surface of the substrate, the leakage current limiting region being in contact with the gate dielectric layer, and the leakage current limiting region having a first conductivity type.

[0011] In one embodiment, the doping concentration of the leakage current limiting region is less than the doping concentration of the substrate.

[0012] In one embodiment, a second floating region is further included, which is disposed within the substrate. The second floating region has the same depth as the first floating region and is located directly below the shielding region.

[0013] In one embodiment, the substrate includes a substrate and a drift region disposed on the substrate, wherein the contact region, the source region, the shielding region, the first floating region, the leakage current limiting region and the second floating region are disposed within the drift region, the first surface is the surface of the drift region away from the substrate, and the second surface is the surface of the substrate away from the drift region.

[0014] In one embodiment, the material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride, and gallium oxide.

[0015] In one embodiment, the resistivity of the substrate is 0.01 Ω·cm to 0.03 Ω·cm, and the doping concentration of the drift region is 5 × 10⁻⁶. 15 / cm 3 ~5×10 17 / cm 3 The doping concentration of the leakage current limiting region is 1×10⁻⁶. 15 / cm 3 ~1×10 17 / cm 3 .

[0016] In one embodiment, the thickness of the substrate is 100 μm to 500 μm, and the thickness of the drift region is 5 μm to 100 μm.

[0017] In one embodiment, the system further includes a source electrode region, a drain electrode region, and an isolation layer, the isolation layer surrounding the gate and the gate dielectric layer, the source electrode region being disposed on the source region and the contact region, and the drain electrode region being disposed on the second surface of the substrate.

[0018] Furthermore, the present invention also provides an electronic product comprising the power semiconductor device as described above.

[0019] The aforementioned power semiconductor device structure incorporates a first floating region within the substrate, which protects the gate dielectric layer and facilitates the use of an accumulation channel. Unlike traditional accumulation channel devices, the power semiconductor device of this invention directly utilizes a portion of the drift region / leakage current confinement layer within the substrate as the accumulation channel, eliminating the need for ion implantation. This further shortens the fabrication process compared to conventional devices. Furthermore, since the accumulation channel does not undergo ion implantation, it exhibits fewer lattice defects and higher electron mobility, resulting in reduced on-resistance. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a traditional accumulation-type metal-oxide-semiconductor field-effect transistor (MOSFET) device.

[0021] Figure 2 A schematic diagram of the structure of a power semiconductor device according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of a power semiconductor device according to another embodiment of the present invention;

[0023] Figure 4This is a schematic diagram of the structure of a power semiconductor device according to another embodiment of the present invention;

[0024] The symbols in the attached image are explained as follows:

[0025] 10: Accumulation type metal-oxide-semiconductor field-effect transistor device; 101: Source electrode region; 102: Insulating dielectric layer; 103: Gate; 104: Gate dielectric layer; 105: Contact region; 106: Source region; 107: Base region; 108: Shielding region; 109: Drift region; 110: Substrate; 111: Drain electrode region.

[0026] 20: Power semiconductor device; 201: Source electrode region; 202: Isolation layer; 203: Gate; 204: Gate dielectric layer; 205: Contact region; 206: Shielding region; 207: Source region; 208: First floating region; 209: Drift region; 210: Substrate; 211: Drain electrode region; 212: Drain current limiting region; 213: Second floating region. Detailed Implementation

[0027] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of the present invention, "a number" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0029] The terms "preferred," "more preferably," etc., used in this invention refer to embodiments of the invention that provide certain beneficial effects under certain circumstances. However, other embodiments may also be preferred under the same or other circumstances. Furthermore, the description of one or more preferred embodiments does not imply that other embodiments are unavailable, nor is it intended to exclude other embodiments from the scope of this invention.

[0030] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.

[0031] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] When using “including,” “having,” and “contains” as described herein, the intention is to cover non-exclusive inclusion, unless an explicit qualifying term such as “only,” “consisting of,” etc., is used, in which case another component may be added.

[0036] Unless otherwise stated, a singular term may include a plural term and should not be understood as having a quantity of one.

[0037] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the elements are shown in the drawings only as examples to facilitate understanding of the invention, but are not necessarily drawn to actual scale. The scale in the drawings does not constitute a limitation on the invention. It should be noted that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an inserting component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no inserting component. Similarly, when the first component is referred to as "electrically contacting" or "electrically coupling" to the second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between the conductive components.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] like Figure 2As shown, the present invention provides a power semiconductor device 20, comprising: a substrate having a first surface and a second surface opposite to each other; a contact region 205, a source region 207, a shielding region 206 and a first floating region 208 disposed within the substrate; one side surface of the source region 207 and the contact region 205 being flush with the first surface of the substrate; the other side surface of the source region 207 and the contact region 205 contacting the shielding region 206; the sidewall of the source region 207 contacting the sidewall of the contact region 205; the source region 207, the shielding region 206 and the substrate surrounding the contact region 205; and the first floating region 208 being closer to the second surface of the substrate than the shielding region 206.

[0040] In a specific example, the power semiconductor device 20 further includes a gate dielectric layer 204 disposed on the first surface of the source region 207 and the substrate, and a first floating region 208 located directly below the gate dielectric layer 204.

[0041] Specifically, the thickness of the gate dielectric layer 204 is 30nm to 150nm, and the gate dielectric layer 204 can be formed by thermal oxidation or thermal deposition, but is not limited to being made of silicon dioxide.

[0042] Furthermore, the thickness of the gate dielectric layer 204 can be, but is not limited to, 30nm, 50nm, 80nm, 100nm or 150nm.

[0043] In one specific example, the power semiconductor device 20 described above also includes a gate 203 disposed on the gate dielectric layer 204.

[0044] It should be noted that the source region 207 has a first conductivity type, while the contact region 205, the first floating region 208, and the shielding region 206 have a second conductivity type. The first conductivity type is the opposite of the second conductivity type.

[0045] Understandably, the shielding region 206 and the first floating region 208 work together. The shielding region 206 primarily shields the electric field at the gate dielectric layer 204, and works in conjunction with the first floating region 208 and the zero-bias gate 203 to form a depletion region at and near the sidewall contact point of the drift region 209 with the shielding region 206 and the source region 207. This allows the power semiconductor device 20 to remain in a blocking state even without an applied gate voltage. The first floating region 208 primarily shields the gate dielectric layer 204 to improve the breakdown voltage of the power semiconductor device 20. This interaction allows the device to achieve better blocking voltage and on-resistance performance.

[0046] In a specific example, the power semiconductor device 20 further includes a leakage current limiting region 212 disposed in the substrate. The sidewalls of the shielding region 206 and the source region 207 are in contact with the sidewalls of the leakage current limiting region 212. One side surface of the contact region 205, the source region 207, and the leakage current limiting region 212 is flush with the first surface of the substrate. The leakage current limiting region 212 is in contact with the gate dielectric layer 204. The leakage current limiting region 212 has a first conductivity type.

[0047] If the first conductivity type is N-type, then the second conductivity type is P-type; if the first conductivity type is P-type, then the second conductivity type is N-type.

[0048] Understandably, the doping concentration of the leakage current limiting region 212 is less than that of the drift region 209.

[0049] In a specific example, the power semiconductor device 20 further includes a second floating region 213 disposed in the substrate. The second floating region 213 has the same depth as the first floating region 208 and is located directly below the shielding region 206.

[0050] Understandably, the depth is the distance from the surface of any floating zone that is closer to the first surface of the substrate to the first surface of the substrate.

[0051] Specifically, such as Figure 2 As shown, the fact that the second floating region 213 and the first floating region 208 have the same depth indicates that the upper surface of the second floating region 213 and the first floating region 208 are at the same distance from the first surface of the substrate.

[0052] Furthermore, the substrate includes a substrate 210 and a drift region 209 disposed on the substrate 210. A contact region 205, a source region 207, a shielding region 206, a first floating region 208, a leakage current limiting region 212, and a second floating region 213 are disposed within the drift region 209. The first surface is the surface of the drift region 209 that is away from the substrate 210, and the second surface is the surface of the substrate 210 that is away from the drift region 209.

[0053] Specifically, the material of the substrate 210 and the material of the drift region 209 are selected from at least one of silicon carbide, gallium nitride and gallium oxide.

[0054] In a specific example, the resistivity of substrate 210 is 0.01 Ω·cm to 0.03 Ω·cm, and the doping concentration of drift region 209 is 5 × 10⁻⁶. 15 / cm 3 ~5×10 17 / cm 3 The doping concentration of the leakage current limiting region 212 is 1×10⁻⁶. 15 / cm 3 ~1×1017 / cm 3 .

[0055] In a specific example, the thickness of the substrate 210 is 100 μm to 500 μm, and the thickness of the drift region 209 is 5 μm to 100 μm.

[0056] Furthermore, the thickness of the substrate 210 may be, but is not limited to, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm or 500μm.

[0057] Furthermore, the thickness of the aforementioned drift region 209 may be, but is not limited to, 5μm, 20μm, 35μm, 50μm, 65μm, 80μm, 95μm or 100μm.

[0058] In a specific example, the power semiconductor device 20 further includes a source electrode region 201, a drain electrode region 211, and an isolation layer 202. The isolation layer 202 surrounds the gate 203 and the gate dielectric layer 204. The source electrode region 201 is disposed on the source region 207 and the contact region 205, and the drain electrode region 211 is disposed on the second surface of the substrate.

[0059] Understandably, when no voltage is applied to the gate 203 of the power semiconductor device 20, a depletion region is formed in and near the contact area between the drift region 209 and the sidewalls of the shield region 206 and the source region 207 of the power semiconductor device 20, such as... Figure 2 As shown by the dashed lines, the depletion region electrically isolates the source region 207 and the drift region 209, making the device normally closed. When no voltage is applied to the gate 203, but a positive voltage is applied to the drain region 211, the area of ​​the depletion region expands, preventing electrons from flowing from the source region 207 to the drift region 209, so the power semiconductor device 20 is in a blocking state. When a positive voltage greater than the threshold voltage is applied to the gate 203, an electron accumulation layer forms in the drift region 209 near the gate dielectric layer 204. This electron accumulation layer electrically connects the source region 207 and the drift region 209. If a high voltage from the source region 201 is applied to the drain region 211, electrons can flow from the source region 207 to the drift region through the electron accumulation layer, and the power semiconductor device 20 is in a conducting state. By controlling the voltage of the gate 203, the power semiconductor device 20 can be switched between blocking and conducting states.

[0060] When the power semiconductor device 20 also includes a leakage current limiting region 212, such as Figure 3As shown, the leakage current limiting region 212 is of the first conductivity type, and its doping concentration is lower than that of the drift region 209 of the first conductivity type. The presence of the leakage current limiting region 212 increases the area of ​​the depletion region, thereby reducing the leakage current of the power semiconductor device 20 in the blocking state.

[0061] When the power semiconductor device 20 also includes a second floating region 213, such as Figure 4 The second floating region 213 shown is of a second conductivity type, and its doping concentration is equal to that of the first floating region 208. By setting the second floating region 213, the electric field at the first floating region 208 can be shared, enabling the power semiconductor device 20 to obtain a higher breakdown voltage and further improving device performance.

[0062] The aforementioned power semiconductor device 20 structure incorporates a first floating region 208 within the substrate, which protects the gate dielectric layer 204 and facilitates the use of an accumulation channel. Unlike conventional accumulation channel devices, the power semiconductor device 20 of this invention directly utilizes a portion of the drift region 209 / leakage current limiting region 212 within the substrate as an accumulation channel, eliminating the need for ion implantation. This significantly shortens the fabrication process compared to conventional devices. Furthermore, since no ion implantation is performed in the accumulation channel, there are fewer lattice defects and higher electron mobility, resulting in reduced on-resistance of the power semiconductor device 20.

[0063] Furthermore, the present invention also provides an electronic product comprising the power semiconductor device 20 as described above.

[0064] Understandably, the aforementioned electronic products include, but are not limited to, electronic components such as integrated circuits, resistors, and capacitors.

[0065] The following specific embodiments provide a more detailed description of the power semiconductor device 20 of the present invention. It will be understood that, unless otherwise specified, all materials involved in the following specific embodiments are commercially available.

[0066] Example 1

[0067] This embodiment provides a power semiconductor device, the fabrication process of which is as follows:

[0068] Step S1: On the Si surface of the silicon carbide substrate 210 having a first conductivity type, a partial silicon carbide drift region 209 having a first conductivity type is grown by homoepitaxial growth.

[0069] The silicon carbide substrate 210 is heavily doped with nitrogen or phosphorus as the dopant, and has a resistivity of 0.01 Ω·cm to 0.03 Ω·cm with a thickness of 100 μm to 500 μm. The silicon carbide drift region 209 is doped with nitrogen or phosphorus as the dopant, and the doping concentration is 5 × 10⁻⁶. 15 / cm3 ~5×10 17 / cm 3 The thickness ranges from 5μm to 100μm.

[0070] Step S2: A floating region is formed on the surface of the silicon carbide drift region 209 away from the silicon carbide substrate 210.

[0071] In a specific example ( Figure 2 or Figure 3 In one example, the floating area is the first floating area 208; in another specific example ( Figure 4 In the above, the floating areas are the first floating area 208 and the second floating area 213.

[0072] The first floating region 208 and the second floating region 213 are located on the same plane, with the same thickness and width, the thickness being 0.1 μm to 1.0 μm and the width being 1.0 μm to 10 μm; both the first floating region 208 and the second floating region 213 are of the second conductivity type, and the doped impurities are aluminum or boron, with a doping concentration of 10. 18 cm -3 -10 20 cm -3 .

[0073] The air-floating areas (including the first air-floating area 208 and the second air-floating area 213) can be completed in one step using the following process:

[0074] The floating region is formed by selective high-temperature ion implantation on the surface of the silicon carbide drift region 209 away from the silicon carbide substrate 210.

[0075] Alternatively, the floating region can be obtained by performing plasma dry etching on the surface of the silicon carbide drift region 209 away from the silicon carbide substrate 210 to remove the area where the floating region is located, and then growing silicon carbide with the same doping impurities and doping concentration as the floating region on it through homoepitaxial growth process, and removing the excess silicon carbide drift layer 209 by mechanical polishing or plasma dry etching processes.

[0076] Step S3: On the surface of the silicon carbide drift region 209, which has completed the fabrication of the floating region, a silicon carbide epitaxial layer with the same doping impurities and doping concentration as the silicon carbide drift region 209 is continuously grown homogeneously on the surface away from the silicon carbide substrate 210, to complete the growth of the complete silicon carbide drift region 209.

[0077] In a specific example ( Figure 2 In one example, the thickness of the silicon carbide epitaxial layer grown by homoepitaxial process is 0.6 μm to 1.5 μm; in another specific example ( Figure 3 In option 4), the thickness of the silicon carbide epitaxial layer grown by homoepitaxial process is 0.1 μm to 0.5 μm.

[0078] Step S4: A leakage current limiting region 212 is formed on the surface of the silicon carbide drift region 209 that has been epitaxially grown in step S3. Figure 3 and Figure 4 ), contact area 205, source area 207, and shielding area 206.

[0079] Among them, Figure 3 and Figure 4 In the example shown, the leakage current limiting region 212 has a first conductivity type, and the doped impurity is nitrogen or phosphorus with a doping concentration of 10. 15 / cm 3 ~10 17 cm -3 The thickness is 0.5μm to 1.0μm; the leakage current restriction region 212 is formed by homoepitaxial growth on the surface of the drift layer 209 away from the substrate 210.

[0080] The contact region 205 has a thickness of 0.1 μm, exhibits a second conductivity type, and is doped with boron or aluminum at a doping concentration of 10. 19 cm -3 ~10 20 cm -3 The source region 207 has a thickness of 0.1 μm, exhibits the first conductivity type, and is doped with nitrogen or phosphorus at a doping concentration of 10. 19 / cm 3 ~10 20 cm -3 The thickness of the shielding region 206 is 0.4μm to 0.9μm, it has a second conductivity type, and the doped impurities are boron or aluminum with a doping concentration of 10. 18 cm -3 ~10 19 cm -3 The above components are fabricated in the drift region 209 using photolithography and localized ion implantation processes. Figure 2 ) and leakage current limiting region 212 ( Figure 3 and Figure 4 The surface away from the substrate 210 is realized.

[0081] Step S5: Prepare gate dielectric 204 and gate 203.

[0082] Through high-temperature thermal oxidation and post-oxidation annealing processes, in the drift zone 209 ( Figure 2 ) and leakage current limiting region 212 ( Figure 3 and Figure 4 A dense, high-quality, low-defect, low-interface-state-density, low-silicon dioxide gate dielectric layer 204 is formed on the surface away from the substrate 210, with a thickness of 30nm to 150nm.

[0083] A polysilicon gate 203 is deposited on the upper surface of the gate dielectric layer 204 using a chemical vapor deposition process, with a thickness ranging from 100 nm to 500 nm. The polysilicon gate 203 is of the first conductivity type and is doped with boron, with a doping concentration greater than 10%. 20 cm -3 The doping of polysilicon gate 203 can be achieved through in-situ doping during chemical vapor deposition or ion implantation after growth.

[0084] After completing the growth process of the gate dielectric layer 204 and the polysilicon gate 203, the patterning of the gate dielectric layer 204 and the polysilicon gate 203 is completed through photolithography and etching processes.

[0085] Step S6: Prepare isolation layer 202 and source electrode region 201 to achieve ohmic contact between source electrode region 201 and drain electrode region 211 and silicon carbide.

[0086] A low-temperature silicon oxide layer is deposited on the surface of the polysilicon gate 203 using plasma chemical vapor deposition (PCVDC) and then patterned using photolithography and etching processes to form an isolation layer 202.

[0087] A metal layer is deposited on the surfaces of the contact region 205, source region 207, and source electrode region using ion sputtering or electron beam evaporation. This layer is then patterned using photolithography and etching / etching processes to form the source electrode region 201. The material of the source electrode region 201 can be metals such as Ni, Ti, and Al, or combinations thereof. The ohmic contact between the source electrode region 201, the drain electrode region 211, and the silicon carbide is formed by annealing in a tube annealing furnace under nitrogen or argon atmosphere at 500°C–600°C for 30–60 minutes, or by annealing in a rapid thermal annealing apparatus under nitrogen or argon atmosphere at 1000–1200°C for 1–5 minutes.

[0088] By selecting steps S1 to S6 and their specific methods, the SiC MOSFET devices with floating shielding regions and accumulation channels in the above embodiments can be fabricated.

[0089] Specifically, the power device includes the power semiconductor device with a floating shielding region and an accumulation channel in any of the above embodiments, or the power semiconductor device prepared by the preparation method of the power semiconductor device with a floating shielding region and an accumulation channel in any of the above embodiments.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementations of the present invention, designed to facilitate a detailed understanding of the technical solutions of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided by the present invention through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this invention patent should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises: a substrate having opposite first and second surfaces, the substrate having a contact region, a source region, a shield region and a first floating region therein, the source region being flush with the first surface of the substrate on one side thereof, the other side of the source region being in contact with the shield region, the sidewall of the source region being in contact with the sidewall of the contact region, the source region, the shield region and the substrate surrounding the contact region, the first floating region being closer to the second surface of the substrate than the shield region; a gate dielectric layer disposed on the source region and the first surface of the substrate, the first floating region being directly below the gate dielectric layer; a gate electrode disposed on the gate dielectric layer; wherein the source region has a first conductivity type, the contact region, the first floating region and the shield region have a second conductivity type, the first conductivity type being opposite to the second conductivity type; a drain current limiting region disposed in the substrate, the sidewall of the shield region and the sidewall of the source region being in contact with the sidewall of the drain current limiting region, the contact region, the source region and one side of the drain current limiting region being flush with the first surface of the substrate, the drain current limiting region being in contact with the gate dielectric layer, the drain current limiting region having the first conductivity type, the drain current limiting region having a doping concentration less than that of the substrate.

2. The power semiconductor device of claim 1, wherein, a second floating region disposed in the substrate, the second floating region having the same depth as the first floating region and being directly below the shield region.

3. The power semiconductor device of claim 2, wherein, The substrate comprises a substrate and a drift region disposed on the substrate, the contact region, the source region, the shield region, the first floating region, the drain current limiting region and the second floating region being disposed in the drift region, the first surface being the surface of the drift region away from the substrate, the second surface being the surface of the substrate away from the drift region.

4. The power semiconductor device of claim 3, wherein, The material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride and gallium oxide.

5. The power semiconductor device of claim 3, wherein, The resistivity of the substrate is 0.01 Ω-cm ~ 0.03 Ω-cm, the doping concentration of the drift region is 5x10 15 / cm 3 ~5x10 17 / cm 3 , and the doping concentration of the leakage current limiting region is 1x10 15 / cm 3 ~1x10 17 / cm 3 .

6. The power semiconductor device of claim 3, wherein, The thickness of the substrate is 100 μm ~ 500 μm, and the thickness of the drift region is 5 μm ~ 100 μm.

7. The power semiconductor device according to any one of claims 1 to 2 and 4 to 6, characterized in that, The power semiconductor device further comprises a source electrode region, a drain electrode region and an isolation layer, the isolation layer surrounding the gate electrode and the gate dielectric layer, the source electrode region being disposed on the source region and the contact region, the drain electrode region being disposed on the second surface of the substrate.

8. An electronic product, characterized by comprising: The power semiconductor device comprises: a substrate having opposite first and second surfaces, the substrate having a contact region, a source region, a shield region and a first floating region therein, the source region being flush with the first surface of the substrate on one side thereof, the other side of the source region being in contact with the shield region, the sidewall of the source region being in contact with the sidewall of the contact region, the source region, the shield region and the substrate surrounding the contact region, the first floating region being closer to the second surface of the substrate than the shield region; a gate dielectric layer disposed on the source region and the first surface of the substrate, the first floating region being directly below the gate dielectric layer; a gate electrode disposed on the gate dielectric layer; wherein the source region has a first conductivity type, the contact region, the first floating region and the shield region have a second conductivity type, the first conductivity type being opposite to the second conductivity type; a drain current limiting region disposed in the substrate, the sidewall of the shield region and the sidewall of the source region being in contact with the sidewall of the drain current limiting region, the contact region, the source region and one side of the drain current limiting region being flush with the first surface of the substrate, the drain current limiting region being in contact with the gate dielectric layer, the drain current limiting region having the first conductivity type, the drain current limiting region having a doping concentration less than that of the substrate. a second floating region disposed in the substrate, the second floating region having the same depth as the first floating region and being directly below the shield region. The substrate comprises a substrate and a drift region disposed on the substrate, the contact region, the source region, the shield region, the first floating region, the drain current limiting region and the second floating region being disposed in the drift region, the first surface being the surface of the drift region away from the substrate, the second surface being the surface of the substrate away from the drift region. The material of the substrate and the material of the drift region are selected from at least one of silicon carbide, gallium nitride and gallium oxide. The thickness of the substrate is 100 μm ~ 500 μm, and the thickness of the drift region is 5 μm ~ 100 μm. The power semiconductor device further comprises a source electrode region, a drain electrode region and an isolation layer, the isolation layer surrounding the gate electrode and the gate dielectric layer, the source electrode region being disposed on the source region and the contact region, the drain electrode region being disposed on the second surface of the substrate. The power semiconductor device comprises:

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