A Compact Doherty Power Amplifier

Abstract

The present invention relates to a compact Doherty power amplifier, belonging to the technical field of radio frequency power amplifiers, and solves the problems of low working efficiency and small circuit gain of existing Doherty power amplifiers. The Doherty power amplifier includes: a drive power amplification circuit connected to the input end of a power divider; a carrier power amplification circuit connected to one output end of the power divider, and the carrier power amplification circuit includes a carrier output matching network; a peak power amplification circuit connected to the other output end of the power divider, and the peak power amplification circuit includes a peak output matching network and a π-type microstrip compensation line. The double impedance point matching of the carrier power amplifier is realized, and the working efficiency of the carrier power amplifier when operating at the back-off power point and the saturation operating point is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency power amplifiers, and in particular, to a compact Doherty power amplifier. Background Art

[0002] At present, 5G technology has become a hot topic for numerous scientific research workers. However, the implementation of 5G technology requires excellent hardware infrastructure. Small base stations are one of the hardware infrastructures for implementing 5G technology. Radio frequency power amplifiers are the core components in 5G small base stations and play an important role in small base stations. In order to find a radio frequency power amplifier architecture that can meet the current requirements of 5G small base stations, radio frequency power amplifiers based on the Doherty architecture have gradually emerged in people's vision. This type of power amplifier has high efficiency and good linearity at the power back-off operating point, so Doherty power amplifiers have become a hot topic in current research.

[0003] Traditional Doherty power amplifiers have low operating efficiency and small circuit gain, and cannot meet the requirements of current 5G communication systems for radio frequency power amplifiers. Therefore, there is a lack of a compact, high-efficiency, and high-gain Doherty power amplifier suitable for 5G communication base stations in the future. Summary of the Invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a compact Doherty power amplifier to solve the problems of low operating efficiency and small circuit gain of existing Doherty power amplifiers.

[0005] On the one hand, an embodiment of the present invention provides a compact Doherty power amplifier, including:

[0006] A drive power amplification circuit connected to the input end of a power splitter;

[0007] A carrier power amplification circuit connected to an output end of the power splitter, and the carrier power amplification circuit includes a carrier output matching network;

[0008] A peak power amplification circuit connected to the other output end of the power splitter, and the peak power amplification circuit includes a peak output matching network and a π-shaped microstrip compensation line.

[0009] Further, when a first power signal is input to the drive power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to the impedance at the combining point, and the π-shaped microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the carrier power amplification circuit amplifies the first power signal;

[0010] When a second power signal is input to the drive power amplifier circuit, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, and the peak output matching network matches the load impedance of the peak power transistor to 75 ohms. The second power signal is amplified by the carrier power amplifier circuit and the peak power amplifier circuit together.

[0011] Further, the carrier power amplifier circuit further includes a carrier input matching network connected between an input terminal of the power splitter and the carrier power transistor;

[0012] The carrier input matching network includes a first inductor, a first capacitor, and a second capacitor; one end of the first inductor is simultaneously connected to one end of the first capacitor and one end of the second capacitor, the other end of the first inductor is connected to the gate of the carrier power transistor, the other end of the first capacitor is the input terminal of the carrier input matching network, and the other end of the second capacitor is grounded.

[0013] Further, the carrier output matching network is connected between the carrier power transistor and the combining point, and includes a first microstrip line, a third capacitor, and a fourth capacitor. One end of the first microstrip line is connected to one end of the third capacitor, the other end of the first microstrip line is the output terminal of the carrier output matching network, the output terminal of the carrier output matching network is further connected to one end of the fourth capacitor, one end of the third capacitor is connected to the drain of the carrier power transistor, and the other end of the fourth capacitor is grounded.

[0014] Further, the carrier power amplifier circuit further includes a π-type phase compensation network connected between an output terminal of the power splitter and the carrier input matching network;

[0015] The π-type phase compensation network includes a second inductor, a fifth capacitor, and a sixth capacitor. The fifth capacitor and the sixth capacitor are respectively connected to both ends of the second inductor; one end of the second inductor is the input terminal of the π-type phase compensation network, and the other end is the output terminal of the π-type phase compensation network.

[0016] Further, the peak power amplifier circuit further includes a peak input matching network;

[0017] The peak input matching network includes a second microstrip line, a seventh capacitor, and an eighth capacitor. One end of the second microstrip line is simultaneously connected to one end of the seventh capacitor and one end of the eighth capacitor, the other end of the seventh capacitor is the input terminal of the peak input matching network, the other end of the eighth capacitor is grounded, and the other end of the second microstrip line is the output terminal of the peak input matching network.

[0018] Further, the peak output matching network includes a third microstrip line, a ninth capacitor, and a tenth capacitor. The third microstrip line is connected to one end of the ninth capacitor and one end of the tenth capacitor at the same time. The other end of the ninth capacitor is the input end of the peak output matching network, and the other end of the tenth capacitor is grounded.

[0019] Further, the π-shaped microstrip compensation line includes a fourth microstrip line and an eleventh capacitor, and shares the tenth capacitor with the peak output matching network; the tenth capacitor and the eleventh capacitor are respectively connected to both ends of the fourth microstrip line, and both ends of the fourth microstrip line are respectively the input end and the output end of the π-shaped microstrip compensation line.

[0020] Further, the drive power amplifier circuit includes a drive input matching network, a drive power transistor, and a drive output matching network;

[0021] The drive input matching network includes a first resistor, a third inductor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor; the first resistor is connected in parallel with the twelfth capacitor, and one end of the parallel connection is the output end of the drive input matching network, and the other end of the parallel connection is connected to one end of the third inductor. The other end of the third inductor is connected to one end of the thirteenth capacitor and one end of the fourteenth capacitor at the same time. The other end of the thirteenth capacitor is the input end of the drive input matching network, and the other end of the fourteenth capacitor is grounded;

[0022] The drive output matching network includes a fifth microstrip line, a fifteenth capacitor, and a sixteenth capacitor; one end of the fifth microstrip line is connected to one end of the fifteenth capacitor, and the other end is the output end of the drive output matching network. The other end of the fifteenth capacitor is the input end of the drive output matching network, and the sixteenth capacitor is connected between the output end of the drive output matching network and the ground.

[0023] Further, it also includes an input bias circuit connected to the gates of the carrier power transistor, the peak power transistor, and the drive power transistor; the input bias network includes a fourth inductor, a second resistor, and a first DC voltage source; one end of the fourth inductor is the input end of the input bias network, and the other end is connected to one end of the second resistor. The other end of the second resistor is connected to the positive terminal of the DC voltage source, and the negative terminal of the DC voltage source is grounded;

[0024] It also includes an output bias circuit connected to the drains of the carrier power transistor, the peak power transistor, and the drive power transistor; the output bias network includes a fifth inductor and a second DC voltage source; one end of the fifth inductor is the input end of the output bias network, and the other end of the fifth inductor is connected to the positive terminal of the second DC voltage source, and the negative terminal of the second DC voltage source is grounded.

[0025] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0026] 1. A compact Doherty power amplifier provides driving power for a power divider, a carrier power amplifier circuit, and a peak power amplifier circuit through a driving power amplifier circuit, enhancing the gain of the overall circuit. Meanwhile, through the mutual cooperation of a carrier output matching network, a peak output matching network, and a π-shaped microstrip compensation line, dual-impedance point matching of the carrier power amplifier is achieved, improving the operating efficiency of the carrier power amplifier when operating at the back-off power point and the saturation operating point. When a low-power signal is input, the carrier output matching network matches the load impedance of the carrier power amplifier to the combining point impedance. When a high-power signal is input, the carrier output matching network and the peak output matching network cooperate with each other to achieve the effect of matching the parallel load impedance of the carrier power amplifier circuit and the peak power amplifier circuit to the combining point impedance. Therefore, there is no need to set a post-matching network at the combining point, reducing the size of the entire amplifier and achieving a compact layout.

[0027] 2. The Π-shaped phase compensation network in the carrier power amplifier circuit is used to compensate the phase difference between the carrier power amplifier circuit and the peak power amplifier circuit, improving the gain of the overall circuit.

[0028] 3. Through the π-shaped microstrip compensation line, it is ensured that the output power of the carrier power amplifier circuit does not leak when the peak power amplifier is not turned on, that is, when the carrier power amplifier operates at the back-off point, the load impedance of the peak power transistor is in a high-impedance state. At the same time, the π-shaped microstrip compensation line shares the capacitor C17 with the peak output matching network, which can reduce the circuit size and save costs.

[0029] 4. By setting an input bias circuit connected to the gates of the carrier power transistor, the peak power transistor, and the driving power transistor and an output bias circuit connected to the drains, stable DC voltages are provided for the gates and drains of the transistors, preventing interference of the RF signal to the DC power supply and improving the stability of the entire circuit.

[0030] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combination schemes. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can be made obvious from the description or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings are only for the purpose of showing specific embodiments and are not considered as a limitation to the present invention. Throughout the drawings, the same reference signs represent the same components.

[0032] Figure 1 It is a schematic diagram of the overall structure of a compact Doherty power amplifier in an embodiment;

[0033] Figure 2 It is a schematic diagram of the internal structure of a compact Doherty power amplifier in an embodiment. Specific embodiments

[0034] The preferred embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0035] Traditional Doherty power amplifiers have low operating efficiency and small circuit gain, and cannot meet the requirements of current 5G communication systems for RF power amplifiers. Therefore, this application provides a compact Doherty power amplifier. By the cooperation of the drive power amplification circuit, the carrier power amplification circuit and the peak power amplification circuit, the amplification of the input signal is realized, and the operating efficiency and circuit gain of the Doherty power amplifier are improved.

[0036] A specific embodiment of the present invention discloses a compact Doherty power amplifier, as Figure 1 shown, including: a drive power amplification circuit connected to the input end of the power divider;

[0037] a carrier power amplification circuit connected to an output end of the power divider, and the carrier power amplification circuit includes a carrier output matching network;

[0038] a peak power amplification circuit connected to the other output end of the power divider, and the peak power amplification circuit includes a peak output matching network and a π-type microstrip compensation line;

[0039] When a first power signal is input to the drive power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to the combining point impedance, and the π-type microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the first power signal is amplified by the carrier power amplification circuit;

[0040] When a second power signal is input to the drive power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, and the peak output matching network matches the load impedance of the peak power transistor to 75 ohms, and the second power signal is amplified jointly by the carrier power amplification circuit and the peak power amplification circuit.

[0041] Specifically, the power of the first power signal is lower than that of the second power signal. The first power signal is a low-power signal, such that the signal when the carrier power transistor is turned on is a low-power signal. The second power signal is a high-power signal, such that the signal when the peak power transistor is turned on is a high-power signal. When a low-power signal is input to the drive power amplifier circuit, the carrier power amplifier circuit operates at the power back-off point. At this time, the carrier output matching network matches the load impedance of the carrier power transistor to 50 ohms, and the π-shaped microstrip compensation line matches the load impedance of the peak power transistor to infinity. The first power signal is amplified by the carrier power amplifier circuit. When a high-power signal is input to the drive power amplifier circuit, the carrier power amplifier circuit operates at the power saturation point. The carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, and the peak output matching network matches the load impedance of the peak power transistor to 75 ohms. The parallel load impedance of the carrier power amplifier circuit and the peak power amplifier circuit is 50 ohms. The second power signal is amplified jointly by the carrier power amplifier circuit and the peak power amplifier circuit.

[0042] In implementation, both the carrier power transistor and the peak power transistor are GaN HEMT transistors.

[0043] Compared with the prior art, the compact Doherty power amplifier provided in this embodiment provides drive power for the power divider, the carrier power amplifier circuit, and the peak power amplifier circuit through the drive power amplifier circuit, improving the gain of the overall circuit. At the same time, through the mutual cooperation of the carrier output matching network, the peak output matching network, and the π-shaped microstrip compensation line, dual-impedance point matching of the carrier power amplifier is achieved, improving the operating efficiency of the carrier power amplifier at the back-off power point and its high operating efficiency at the saturation operating point. When a low-power signal is input, the carrier output matching network matches the load impedance of the carrier power amplifier to the combining point impedance. When a high-power signal is input, the carrier output matching network and the peak output matching network cooperate with each other to achieve the effect of matching the parallel load impedance of the carrier power amplifier circuit and the peak power amplifier circuit to the combining point impedance. Therefore, there is no need to set a post-matching network at the combining point, reducing the size of the entire amplifier and achieving a compact layout.

[0044] Preferably, as Figure 2As shown, the carrier power amplification circuit further includes a carrier input matching network IMN2 connected between an input terminal of the power divider and the carrier power transistor. The carrier input matching network IMN2 includes a first inductor L5, a first capacitor C10, and a second capacitor C11; one end of the first inductor L5 is connected to one end of the first capacitor C10 and one end of the second capacitor C11 at the same time, the other end of the first inductor L5 is connected to the gate of the carrier power transistor, the other end of the first capacitor C10 is the input terminal of the carrier input matching network, and the other end of the second capacitor C11 is grounded.

[0045] The carrier output matching network OMN2 is connected between the carrier power transistor and the combining point, and includes a first microstrip line Z2, a third capacitor C12, and a fourth capacitor C13. One end of the first microstrip line Z2 is connected to one end of the third capacitor C12, the other end of the first microstrip line Z2 is the output terminal of the carrier output matching network, the output terminal of the carrier output matching network is further connected to one end of the fourth capacitor C13, one end of the third capacitor C12 is connected to the drain of the carrier power transistor, and the other end of the fourth capacitor C13 is grounded.

[0046] Specifically, to improve the working efficiency, the carrier power transistor in the carrier power amplification circuit operates in class AB. The capacitor C12 in the carrier output matching network is a DC blocking capacitor, which has the function of blocking DC signals and allowing RF signals to pass through. The load impedance corresponding to the carrier power transistor at the back-off operating point and the saturation operating point is different. When the carrier power transistor operates at the back-off operating point, the load impedance of the carrier power transistor can be matched to 50 ohms by adjusting the values of the microstrip line Z2 and the capacitor C13 in the carrier output matching network; when the carrier power transistor operates at the saturation operating point, the load impedance of the carrier power transistor can be matched to 150 ohms by adjusting the values of the microstrip line Z2 and the capacitor C13 in the carrier output matching network, so as to improve the working efficiency of the carrier power transistor at different operating points without affecting the saturation output power of the Doherty power amplifier.

[0047] Preferably, the carrier power amplification circuit further includes a π-type phase compensation network connected between an output terminal of the power divider and the carrier input matching network; the π-type phase compensation network includes a second inductor L4, a fifth capacitor C8, and a sixth capacitor C9, and the fifth capacitor C8 and the sixth capacitor C9 are respectively connected to both ends of the second inductor L4; one end of the second inductor L4 is the input terminal of the π-type phase compensation network, and the other end is the output terminal of the π-type phase compensation network.

[0048] Specifically, the π-type phase compensation network is composed of an inductor and two grounded capacitors connected together, where the values of the two grounded capacitors are the same. The π-type phase compensation network in the carrier power amplifier circuit is used to compensate for the phase difference between the carrier power amplifier circuit and the peak power amplifier circuit, making the entire amplifier circuit more stable and increasing the gain of the overall circuit.

[0049] Preferably, the peak power amplifier circuit further includes a peak input matching network IMN3; the peak input matching network includes a second microstrip line Z3, a seventh capacitor C14, and an eighth capacitor C15. One end of the second microstrip line Z2 is connected to one end of the seventh capacitor C14 and one end of the eighth capacitor C15 at the same time. The other end of the seventh capacitor C14 is the input end of the peak input matching network, the other end of the eighth capacitor C15 is grounded, and the other end of the second microstrip line Z3 is the output end of the peak input matching network.

[0050] The peak output matching network OMN3 includes a third microstrip line Z4, a ninth capacitor C16, and a tenth capacitor C17. The third microstrip line Z4 is connected to one end of the ninth capacitor C16 and one end of the tenth capacitor C17 at the same time. The other end of the ninth capacitor C16 is the input end of the peak output matching network, and the other end of the tenth capacitor C17 is grounded.

[0051] Specifically, to ensure the working efficiency, the peak power transistor is biased in class C. The capacitor C16 in the peak output matching network is a DC-blocking capacitor, which has the function of blocking DC signals and allowing RF signals to pass through. When the drive power amplifier circuit inputs a high-power signal, by adjusting the values of the microstrip line Z2 and the capacitor C13 in the carrier output matching network, the load impedance of the carrier power transistor can be matched to 150 ohms, and by adjusting the values of the microstrip line Z4 and the capacitor C17 in the peak output matching network, the load impedance matching value of the peak power transistor can be 75 ohms, so that the parallel load impedance of the carrier power amplifier circuit and the peak power amplifier circuit is 50 ohms, and it can be directly connected to the combined load, and the input high-power signal is amplified jointly by the carrier power amplifier circuit and the peak power amplifier circuit.

[0052] Preferably, the π-type microstrip compensation line includes a fourth microstrip line Z5 and an eleventh capacitor C18, and shares the tenth capacitor C17 with the peak output matching network; the tenth capacitor C17 and the eleventh capacitor C18 are respectively connected to both ends of the fourth microstrip line Z5, and both ends of the fourth microstrip line Z5 are the input end and the output end of the π-type microstrip compensation line respectively.

[0053] Specifically, the output end of the peak output matching network is connected to a π-shaped microstrip compensation line, which ensures that the output power of the carrier power amplification circuit does not leak when the peak power amplifier is not turned on, that is, when the carrier power amplifier operates at the back-off point, the load impedance of the peak power transistor is in a high-impedance state. The π-shaped microstrip compensation line is composed of a section of microstrip line and two grounded capacitors with the same capacitance. In addition, the grounded capacitors in the π-shaped microstrip compensation line can be combined with the grounded capacitors near the peak output matching network. That is, as shown in the appendix Figure 2 the π-shaped microstrip compensation line and the peak output matching network share the capacitor C17, which can reduce the circuit size and save costs.

[0054] Preferably, the drive power amplification circuit includes a drive input matching network IMN1, a drive power transistor, and a drive output matching network OMN1. The drive input matching network includes a first resistor R1, a third inductor L1, a twelfth capacitor C3, a thirteenth capacitor C1, and a fourteenth capacitor C2; the first resistor R1 is connected in parallel with the twelfth capacitor C3, and one end of the parallel connection is the output end of the drive input matching network, and the other end of the parallel connection is connected to one end of the third inductor. The other end of the third inductor is simultaneously connected to one end of the thirteenth capacitor C1 and one end of the fourteenth capacitor C2. The other end of the thirteenth capacitor C1 is the input end of the drive input matching network, and the other end of the fourteenth capacitor C2 is grounded.

[0055] The drive output matching network includes a fifth microstrip line Z1, a fifteenth capacitor C4, and a sixteenth capacitor C5; one end of the fifth microstrip line Z1 is connected to one end of the fifteenth capacitor C4, and the other end is the output end of the drive output matching network. The other end of the fifteenth capacitor C4 is the input end of the drive output matching network, and the sixteenth capacitor C5 is connected between the output end of the drive output matching network and the ground.

[0056] Specifically, to ensure the working efficiency, the drive power transistor operates in class AB. The drive input matching network includes an RC stabilization network. Adjusting this network can keep the overall circuit stable without oscillation, which is beneficial to improving the stability performance of the overall circuit.

[0057] Preferably, it further includes an input bias circuit connected to the gates of the carrier power transistor, the peak power transistor, and the drive power transistor; the input bias network includes a fourth inductor, a second resistor, and a first DC voltage source; one end of the fourth inductor is the input end of the input bias network, and the other end is connected to one end of the second resistor. The other end of the second resistor is connected to the positive terminal of the DC voltage source, and the negative terminal of the DC voltage source is grounded. At the same time, the input bias circuit further includes three capacitors, and each capacitor is connected in series between the positive terminal of the first DC voltage source and the ground.

[0058] Specifically, the input bias circuits connected to the gates of the carrier power transistor, the peak power transistor, and the drive power transistor have the same structure. However, the voltage VG of the first DC voltage source in the input bias circuit connected to the gate of the carrier power transistor is -4.8V, the voltage VG of the first DC voltage source in the input bias circuit connected to the gate of the peak power transistor is -1.8V, and the voltage VG of the first DC voltage source in the input bias circuit connected to the gate of the drive power transistor is -1.7V.

[0059] By setting the input bias circuits connected to the gates of the carrier power transistor, the peak power transistor, and the drive power transistor, a stable DC voltage is provided for the gates of the transistors, preventing interference from the RF input signal to the DC power supply and improving the stability of the entire circuit.

[0060] Preferably, it further includes an output bias circuit connected to the drains of the carrier power transistor, the peak power transistor, and the drive power transistor; the output bias network includes a fifth inductor and a second DC voltage source; one end of the fifth inductor is the input end of the output bias network, the other end of the fifth inductor is connected to the positive terminal of the second DC voltage source, and the negative terminal of the second DC voltage source is grounded. At the same time, the output bias network further includes three capacitors, and each capacitor is connected in series between the positive terminal of the second DC voltage source and the ground.

[0061] Specifically, the output bias circuits connected to the drains of the carrier power transistor, the peak power transistor, and the drive power transistor have the same structure, and the voltage VD of the second DC voltage source in the output bias circuit is 48V.

[0062] By setting the output bias circuits connected to the drains of the carrier power transistor, the peak power transistor, and the drive power transistor, a stable DC voltage is provided for the drains of the transistors, preventing interference from the RF output signal to the DC power supply and improving the stability of the entire circuit.

[0063] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A compact Doherty power amplifier, characterized in that, Comprising: A drive power amplifier circuit, connected to the input end of a power divider; A carrier power amplifier circuit, connected to one output end of the power divider, and the carrier power amplifier circuit includes a carrier output matching network; A peak power amplifier circuit, connected to the other output end of the power divider, and the peak power amplifier circuit includes a peak output matching network and a π-shaped microstrip compensation line; The drive power amplifier circuit includes a drive input matching network, a drive power transistor, and a drive output matching network; The drive input matching network includes a first resistor, a third inductor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor; the first resistor is in parallel with the twelfth capacitor, one end of the parallel connection is the output end of the drive input matching network, the other end of the parallel connection is connected to one end of the third inductor, the other end of the third inductor is simultaneously connected to one end of the thirteenth capacitor and one end of the fourteenth capacitor, the other end of the thirteenth capacitor is the input end of the drive input matching network, and the other end of the fourteenth capacitor is grounded; The drive output matching network includes a fifth microstrip line, a fifteenth capacitor, and a sixteenth capacitor; One end of the fifth microstrip line is connected to one end of the fifteenth capacitor, the other end is the output end of the drive output matching network, the other end of the fifteenth capacitor is the input end of the drive output matching network, and the sixteenth capacitor is connected between the output end of the drive output matching network and the ground.

2. The compact Doherty power amplifier according to claim 1, wherein When a first power signal is input to the drive power amplifier circuit, the carrier output matching network matches the load impedance of the carrier power transistor to the combined point impedance, and the π-shaped microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the first power signal is amplified by the carrier power amplifier circuit; When a second power signal is input to the drive power amplifier circuit, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, and the peak output matching network matches the load impedance of the peak power transistor to 75 ohms, and the second power signal is amplified by the carrier power amplifier circuit and the peak power amplifier circuit together.

3. The compact Doherty power amplifier according to claim 2, characterized in that, The carrier power amplifier circuit further includes a carrier input matching network connected between one input end of the power divider and the carrier power transistor; The carrier input matching network includes a first inductor, a first capacitor, and a second capacitor; one end of the first inductor is simultaneously connected to one end of the first capacitor and one end of the second capacitor, the other end of the first inductor is connected to the gate of the carrier power transistor, the other end of the first capacitor is the input end of the carrier input matching network, and the other end of the second capacitor is grounded.

4. The compact Doherty power amplifier according to claim 3, wherein The carrier output matching network is connected between the carrier power transistor and the combined point, and includes a first microstrip line, a third capacitor, and a fourth capacitor. One end of the first microstrip line is connected to one end of the third capacitor, the other end of the first microstrip line is the output end of the carrier output matching network, the output end of the carrier output matching network is further connected to one end of the fourth capacitor, one end of the third capacitor is connected to the drain of the carrier power transistor, and the other end of the fourth capacitor is grounded.

5. The compact Doherty power amplifier according to claim 4, characterized in that, The carrier power amplifier circuit further includes a π-type phase compensation network connected between an output terminal of the power divider and the carrier input matching network; The π-type phase compensation network includes a second inductor, a fifth capacitor, and a sixth capacitor. The fifth capacitor and the sixth capacitor are respectively connected to both ends of the second inductor. One end of the second inductor is the input terminal of the ∑-type phase compensation network, and the other end is the output terminal of the π-type phase compensation network.

6. The compact Doherty power amplifier according to claim 1, characterized in that, The peak power amplifier circuit further includes a peak input matching network; The peak input matching network includes a second microstrip line, a seventh capacitor, and an eighth capacitor. One end of the second microstrip line is simultaneously connected to one end of the seventh capacitor and one end of the eighth capacitor. The other end of the seventh capacitor is the input terminal of the peak input matching network, the other end of the eighth capacitor is grounded, and the other end of the second microstrip line is the output terminal of the peak input matching network.

7. The compact Doherty power amplifier according to claim 6, wherein The peak output matching network includes a third microstrip line, a ninth capacitor, and a tenth capacitor. The third microstrip line is simultaneously connected to one end of the ninth capacitor and one end of the tenth capacitor. The other end of the ninth capacitor is the input terminal of the peak output matching network, and the other end of the tenth capacitor is grounded.

8. The compact Doherty power amplifier according to claim 7, wherein The π-type microstrip compensation line includes a fourth microstrip line and an eleventh capacitor, and shares the tenth capacitor with the peak output matching network. The tenth capacitor and the eleventh capacitor are respectively connected to both ends of the fourth microstrip line. Both ends of the fourth microstrip line are the input terminal and the output terminal of the π-type microstrip compensation line respectively.

9. The compact Doherty power amplifier according to claim 3, wherein It further includes an input bias circuit connected to the gates of the carrier power transistor, the peak power transistor, and the drive power transistor. The input bias circuit includes a fourth inductor, a second resistor, and a first DC voltage source. One end of the fourth inductor is the input terminal of the input bias circuit, the other end is connected to one end of the second resistor, the other end of the second resistor is connected to the positive terminal of the DC voltage source, and the negative terminal of the DC voltage source is grounded; It further includes an output bias circuit connected to the drains of the carrier power transistor, the peak power transistor, and the drive power transistor; The output bias circuit includes a fifth inductor and a second DC voltage source. One end of the fifth inductor is the input terminal of the output bias circuit. The other end of the fifth inductor is connected to the positive terminal of the second DC voltage source, and the negative terminal of the second DC voltage source is grounded.

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