A phase adjustable ADPLL circuit

Abstract

The application discloses a phase-adjustable ADPLL circuit and belongs to the field of digital circuits, comprising a phase detector, a lock-loss detection module, a phase-adjustable module, a digital filter, a DCO, an AFC module and a frequency divider; wherein the phase detector, the lock-loss detection module, the phase-adjustable module, the digital filter and the DCO are sequentially connected, the lock-loss detection module, the AFC and the DCO constitute a loop, and the DCO, the frequency divider and the phase detector constitute a loop. By adding the lock-loss detection module and the phase-adjustable module after the phase detector, the lock-loss detection module is used for generating a lock signal Lock, the phase-adjustable module is used for generating an adjusted phase difference signal PD_adj, phase adjustment in the internal loop of the ADPLL is realized, monitoring of whether the loop is locked is realized, the circuit structure of the application is simple, easy to realize and high in reusability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit, in particular to a phase-adjustable ADPLL circuit. BACKGROUND

[0002] A phase-locked loop (PLL) is a circuit with a feedback mechanism. In a PLL, the output of an oscillator is compared to a reference signal, and the oscillator is calibrated based on the difference of the comparison. Ideally, when the phase-locked loop is locked, the oscillator output frequency is the same as the expected oscillation frequency, and the phase error with the reference signal is maintained within a set range. With the development of digital circuit technology, phase-locked loops are developing towards digitization, generalization and integration. ADPLL (All-Digital Phase-Locked Loop) has developed into a new research object. The all-digital phase-locked loop uses digital circuits to realize the functions of analog circuits. Compared with analog phase-locked loops, all-digital phase-locked loops have strong portability and programmability, and their phase and frequency adjustment is easier to implement, which can simplify high-performance receivers.

[0003] Whether the ADPLL realizes the lock of the clock frequency needs to be determined by the clock judgment module. By judging the state of the output clock, it can be determined whether the chip can start stable work and the actual running performance. The lockout detection circuit as the clock judgment module, its output is usually used as the enable control signal of other modules and subsystems. For example, when it is judged that the output clock frequency does not meet the requirements, the lockout detection circuit notifies the automatic frequency calibration (AFC) module for processing through the enable control signal; when it is judged that the output clock frequency meets the requirements, the lockout detection circuit notifies the phase-adjustable module for processing through the lock signal.

[0004] The phase difference discrimination signal output by the phase detector circuit in the patent CN200410082395.0 is used in the PLL frequency lock judgment circuit to monitor the sliding of the phase, and the periodic phase difference sliding is used as the lockout decision condition to determine whether the phase-locked loop frequency is locked. This circuit can handle the temporary lockout caused by phase mutation, but the circuit structure is complex and many components are used; the patent CN202111084728.3 provides a digitally controlled oscillator that can realize dynamic phase selection, but the phase adjustment module needs to be designed together with the DCO, which increases the design difficulty of the DCO, and the circuit structure is complex and the reusability is not high. SUMMARY

[0005] The present application aims to provide a phase-adjustable ADPLL circuit to solve the problems in the background art.

[0006] To solve the above technical problems, the application provides a phase-adjustable ADPLL circuit, which comprises a phase detector, a lock loss detection module, a phase-adjustable module, a digital filter, a DCO, an AFC module and a frequency divider; wherein,

[0007] The phase detector, the lock loss detection module, the phase-adjustable module, the digital filter and the DCO are sequentially connected, the lock loss detection module, the AFC and the DCO form a loop, and the DCO, the frequency divider and the phase detector form a loop;

[0008] The phase detector is used for extracting a phase error between a reference clock and a feedback clock.

[0009] The lock loss detection module is used for judging whether the loop is locked.

[0010] The phase-adjustable module is used for adjusting the phase error output by the phase detector, and the digital filter is used for filtering high-frequency components in the phase error.

[0011] The DCO generates a clock signal corresponding to a frequency control word.

[0012] The AFC module is used for automatic frequency calibration.

[0013] The frequency divider divides the clock signal generated by the DCO to generate a feedback clock to the phase detector.

[0014] In an embodiment of the application, the lock loss detection module comprises a D flip-flop, a judging circuit, a modulo 128 counter and a data selector MUX1.

[0015] The phase difference signal PD[39:0] composed of 8-bit integer and 32-bit decimal is firstly sampled by the D flip-flop to obtain the sampling signal PD_Q[39:0]; then the integer bit PD_Q[39:32] is input to the judging circuit, if PD_Q[39:32] is greater than 2, the judging circuit outputs the control signal Flag_AFC with value 1 to the AFC module, indicating that the phase difference signal needs to be transferred to the AFC module for processing; if PD_Q[39:32] is not greater than 2, the judging circuit outputs the control signal Flag_AFC with value 0 to the AFC module, indicating that the phase difference signal does not need to be transferred to the AFC module for processing; if PD_Q[39:32] is not equal to 0, the judging circuit outputs the counter clear signal Flag_Clr with value 0 to the modulo 128 counter to clear the modulo 128 counter; if PD_Q[39:32] is equal to 0, the judging circuit outputs the counter clear signal Flag_Clr with value 1 to the modulo 128 counter, and the modulo 128 counter normally counts; if the modulo 128 counter counts 128 periods, the locking signal Lock with value 1 is output, indicating that the loop has been locked, and the Lock signal controls the one-of-two data selector MUX1 to select the digital ground signal GND as the clock input of the modulo 128 counter.

[0016] In one embodiment of the application, the judging circuit is composed of a value comparator 1 and a value comparator 2; the integer bit PD_Q[39:32] of the sampling signal is connected to one end of the value comparator 1 and the value comparator 2 respectively, the other end of the value comparator 1 is connected to the fixed value 8'h2, and the output end of the value comparator 1 outputs the control signal Flag_AFC connected to the AFC module; the other end of the value comparator 2 is connected to the fixed value 8'h0, and the output end of the value comparator 2 outputs the counter clear signal Flag_Clr connected to the clear end Clr of the modulo 128 counter.

[0017] In one embodiment of the application, the data end D of the D flip-flop is connected to the phase difference signal PD[39:0], the clock end Clk is connected to the global clock CKR, the reset end Reset is connected to the reset signal Reset, and the output end Q is output to the judging circuit; the clear end Clr of the modulo 128 counter is connected to the output end of the value comparator 2, the clock end Clk of the modulo 128 counter is connected to the output end of the one-of-two data selector MUX1, the carry end C outputs the locking signal Lock connected to the control end of the one-of-two data selector MUX1 and the control end of the one-of-two data selector MUX2 respectively; the data end D0 of the one-of-two data selector MUX1 is connected to the global clock CKR, the data end D1 is connected to the digital ground signal GND, the output end is connected to the clock end Clk of the modulo 128 counter, and the control end is connected to the carry end C of the modulo 128 counter.

[0018] In one embodiment of the application, the phase adjustable module comprises a two-way data selector MUX2, an adder and a four-way data selector MUX3; the sampling signal PD_Q[39:0] obtained by sampling through the D flip-flop is input to the phase adjustable module for processing, and the control signal S1S0 of the four-way data selector MUX3 selects one of the four input data to add with the sampling signal PD_Q[39:0], and the sum signal is input to the D1 end of the two-way data selector MUX2; the D0 end of the two-way data selector MUX2 is the sampling signal PD_Q[39:0], and the control signal of the two-way data selector MUX2 is the lock signal Lock, when the value of Lock is 1, the data at the D1 end is selected to output, which is the adjusted phase difference signal PD_adj[39:0].

[0019] In one embodiment of the application, the data end D00 of the four-way data selector MUX3 is connected with the fixed value 40'h1, the data end D01 is connected with the fixed value 40'h2, the data end D10 is connected with the fixed value 40'h4, the data end D11 is connected with the fixed value 40'h8, the output end is connected to one end of the adder, and the control ends S1 and S0 are connected with the control signals S1 and S0 respectively.

[0020] One input end of the adder is connected with the output end Q of the D flip-flop, the other input end is connected with the output end of the four-way data selector MUX3, and the output end of the adder is connected with the data end D1 of the two-way data selector MUX2.

[0021] The data end D0 of the two-way data selector MUX2 is connected with the output end Q of the D flip-flop, the data end D1 is connected with the output end of the adder, the output end outputs the adjusted phase difference signal PD_adj[39:0], and the control end is connected with the carry end C of the modulo 128 counter.

[0022] In the phase adjustable ADPLL circuit provided by the application, by adding the lock loss detection module and the phase adjustable module after the phase detector, the lock loss detection module is used to generate the lock signal Lock, and the phase adjustable module is used to generate the adjusted phase difference signal PD_adj, so that the phase adjustment in the internal loop of the ADPLL and the monitoring of whether the loop is locked are realized, and the circuit structure of the application is simple, easy to realize and high in reusability. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a phase adjustable ADPLL circuit provided by the application;

[0024] Figure 2is a circuit structure diagram of a lock loss detection module in a phase adjustable ADPLL circuit;

[0025] Figure 3 is a structure diagram of a judging circuit in the lock loss detection module;

[0026] Figure 4 is a circuit structure diagram of a phase adjustable module in the phase adjustable ADPLL circuit;

[0027] Figure 5 is a complete circuit structure diagram of the lock loss detection module and the phase adjustable module. DETAILED DESCRIPTION

[0028] The application will be further described below in conjunction with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description and claims. It should be noted that the drawings are very simplified and all use non-precise proportions, only for the purpose of facilitating and clarifying the purpose of assisting the description of the embodiments of the application.

[0029] The principle structure of the phase adjustable ADPLL circuit of the application is shown in Figure 1 which comprises a phase detector, a lock loss detection module, a phase adjustable module, a digital filter, a DCO (digital controlled oscillator), an AFC (automatic frequency calibration module) and a frequency divider; wherein the phase detector, the lock loss detection module, the phase adjustable module, the digital filter and the DCO are connected in sequence, the lock loss detection module, the AFC and the DCO form a loop, and the DCO, the frequency divider and the phase detector form a loop. The phase detector is used to extract the phase error between the reference clock and the feedback clock; the lock loss detection module is used to judge whether the loop is locked; the phase adjustable module is used to adjust the phase error output by the phase detector; the digital filter is used to filter out the high frequency components in the phase error; the DCO generates a clock signal corresponding to the frequency control word; the AFC module is used for automatic frequency calibration; and the frequency divider divides the clock signal generated by the DCO to generate a feedback clock to the phase detector.

[0030] The lock loss detection module is used to generate a lock signal Lock, and its structure is shown in Figure 2As shown, including D flip-flop, judgment circuit, modulo 128 counter, two-way data selector MUX1. The data terminal D of the D flip-flop is connected with phase difference signal PD[39:0], the clock terminal Clk is connected with global clock CKR, the reset terminal Reset is connected with reset signal Reset, and the output terminal Q outputs to the judgment circuit. The phase difference signal PD[39:0] composed of 8-bit integer and 32-bit fraction is firstly sampled by the D flip-flop to obtain the sampling signal PD_Q[39:0]; then the integer bits PD_Q[39:32] are input to the judgment circuit, if PD_Q[39:32] is greater than 2, the judgment circuit outputs the control signal Flag_AFC with value 1 to the AFC module, indicating that the phase difference signal needs to be transferred to the AFC module for processing; if PD_Q[39:32] is not greater than 2, the control signal Flag_AFC with value 0 is output to the AFC module, indicating that the phase difference signal does not need to be transferred to the AFC module for processing; if PD_Q[39:32] is not equal to 0, at the same time, the judgment circuit outputs the counter clear signal Flag_Clr with value 0 to the modulo 128 counter, and the modulo 128 counter is cleared; if PD_Q[39:32] is equal to 0, the counter clear signal Flag_Clr with value 1 is output to the modulo 128 counter, and the modulo 128 counter is normally counted; if the modulo 128 counter counts 128 periods, the lock signal Lock with value 1 is output, indicating that the loop has been locked, and the Lock signal controls the two-way data selector MUX1 to select the digital ground signal GND as the clock input of the modulo 128 counter.

[0031] As shown in Figure 3 The judgment circuit is composed of value comparator 1 and value comparator 2, and is used to generate control signal Flag_AFC and counter clear signal Flag_Clr. The integer bits PD_Q[39:32] of the sampling signal are respectively connected to one end of value comparator 1 and value comparator 2, the other end of value comparator 1 is connected with fixed value 8'h2, the output end of value comparator 1 outputs control signal Flag_AFC and is connected to the AFC module; the other end of value comparator 2 is connected with fixed value 8'h0, and the output end of value comparator 2 outputs counter clear signal Flag_Clr and is connected to the clear end Clr of the modulo 128 counter.

[0032] The phase adjustable module is used to generate adjusted phase difference signal PD_adj; its structure is as shown in Figure 4As shown, the phase adjustable module includes a two-way data selector MUX2, an adder and a four-way data selector MUX3. The sampling signal PD_Q[39:0] sampled by the D flip-flop is input to the phase adjustable module for processing. The four-way data selector MUX3 selects one of the four input data according to the control signal S1S0 and adds the selected data to the sampling signal PD_Q[39:0] to obtain a sum signal, which is input to the D1 terminal of the two-way data selector MUX2. The D0 terminal of the two-way data selector MUX2 is the sampling signal PD_Q[39:0], and the control signal of the two-way data selector MUX2 is the lock signal Lock. When the value of the lock signal Lock is 1, the data at the D1 terminal is selected and output, which is the adjusted phase difference signal PD_adj[39:0].

[0033] Please continue to refer to Figure 2 The clear terminal Clr of the modulo 128 counter is connected to the output terminal of the value comparator 2, the clock terminal Clk of the modulo 128 counter is connected to the output terminal of the two-way data selector MUX1, the carry terminal C outputs the lock signal Lock and is connected to the control terminal of the two-way data selector MUX1 and the control terminal of the two-way data selector MUX2, respectively. The data terminal D0 of the two-way data selector MUX1 is connected to the global clock CKR, the data terminal D1 is connected to the digital ground GND, the output terminal is connected to the clock terminal Clk of the modulo 128 counter, and the control terminal is connected to the carry terminal C of the modulo 128 counter.

[0034] Please continue to refer to Figure 4 The data terminal D00 of the four-way data selector MUX3 is connected to the fixed value 40'h1, the data terminal D01 is connected to the fixed value 40'h2, the data terminal D10 is connected to the fixed value 40'h4, the data terminal D11 is connected to the fixed value 40'h8, one input terminal of the adder is connected to the output terminal Q of the D flip-flop, the other input terminal is connected to the output terminal of the four-way data selector MUX3, and the control terminals S1 and S0 are connected to the control signals S1 and S0, respectively. The output terminal of the adder is connected to the data terminal D1 of the two-way data selector MUX2. The data terminal D0 of the two-way data selector MUX2 is connected to the output terminal Q of the D flip-flop, the data terminal D1 is connected to the output terminal of the adder, the output terminal outputs the adjusted phase difference signal PD_adj[39:0], and the control terminal is connected to the carry terminal C of the modulo 128 counter.

[0035] In summary, the ADPLL circuit provided by the application includes a lock loss detection module and a phase adjustable module in the internal loop, Figure 5As shown, the monitoring of whether the loop is locked and the phase adjustment are realized: the lock loss detection module judges the input phase difference signal, if the input phase difference value is large, it indicates that the loop is locked, and the AFC module needs to be turned to calibrate; if the difference is small, the modulo 128 counter starts counting until 128 cycles are counted, and the lock signal is output, indicating that the loop is locked. At the same time, the phase adjustment module processes the input phase difference signal through the control signal, and only when the loop is locked, the adjusted phase difference signal is output.

[0036] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A phase adjustable ADPLL circuit, characterized by, It includes a phase detector, a loss-of-lock detection module, a phase-adjustable module, a digital filter, a DCO, an AFC module, and a frequency divider; among which, The phase detector, the loss-of-lock detection module, the phase-adjustable module, the digital filter, and the DCO are connected in sequence. The loss-of-lock detection module, the AFC, and the DCO form a loop. The DCO, the frequency divider, and the phase detector also form a loop. The phase detector is used to extract the phase error between the reference clock and the feedback clock; The loss-of-lock detection module determines whether the loop has achieved locking; The phase-adjustable module is used to adjust the phase error of the phase detector output; the digital filter is used to filter out high-frequency components in the phase error. The DCO generates a clock signal corresponding to the frequency control word; The AFC module is used for automatic frequency calibration; The frequency divider divides the clock signal generated by the DCO to generate a feedback clock to the phase detector; The unlock detection module includes a D flip-flop, a judgment circuit, a modulo-128 counter, and a 2-to-1 data selector MUX1; The phase difference signal PD[39:0], consisting of an 8-bit integer and a 32-bit fractional, is first sampled by a D flip-flop to obtain the sampled signal PD_Q[39:0]. Then, its integer bits PD_Q[39:32] are input to a judgment circuit. If PD_Q[39:32] is greater than 2, the judgment circuit outputs a control signal Flag_AFC with a value of 1 to the AFC module, indicating that the phase difference signal needs to be processed by the AFC module. If PD_Q[39:32] is not greater than 2, the judgment circuit outputs a control signal Flag_AFC with a value of 0 to the AFC module, indicating that the phase difference signal does not need to be processed by the AFC module. If PD_Q[39:32] is not equal to 0, the judgment circuit outputs a counter clear signal Flag_Clr with a value of 0 to the modulo-128 counter to clear the modulo-128 counter; if PD_Q[39:32] is equal to 0, the judgment circuit outputs a counter clear signal Flag_Clr with a value of 1 to the modulo-128 counter, and the modulo-128 counter counts normally; if the modulo-128 counter counts for 128 cycles, it outputs a lock signal Lock with a value of 1, indicating that the loop has been locked. At the same time, the Lock signal controls the 2-to-1 data selector MUX1 to select the digital ground signal GND as the clock input of the modulo-128 counter. The judgment circuit consists of numerical comparator 1 and numerical comparator 2; the integer bits PD_Q[39:32] of the sampled signal are respectively connected to one end of numerical comparator 1 and numerical comparator 2, the other end of numerical comparator 1 is connected to a fixed value 8'h2, the output of numerical comparator 1 outputs a control signal Flag_AFC, which is connected to the AFC module; the other end of numerical comparator 2 is connected to a fixed value 8'h0, the output of numerical comparator 2 outputs a counter clear signal Flag_Clr, which is connected to the clear terminal Clr of the modulo 128 counter.

2. The phase-adjustable ADPLL circuit of claim 1, wherein, The data terminal D of the D flip-flop is connected to the phase difference signal PD[39:0], the clock terminal Clk is connected to the global clock CKR, the reset terminal Reset is connected to the reset signal Reset, and the output terminal Q is output to the judgment circuit; the clear terminal Clr of the modulo-128 counter is connected to the output terminal of the numerical comparator 2, the clock terminal Clk of the modulo-128 counter is connected to the output terminal of the 2-to-1 data selector MUX1, and the carry terminal C outputs the lock signal Lock, which is connected to the control terminals of the 2-to-1 data selector MUX1 and the 2-to-1 data selector MUX2 respectively; the data terminal D0 of the 2-to-1 data selector MUX1 is connected to the global clock CKR, the data terminal D1 is connected to the digital ground signal GND, the output terminal is connected to the clock terminal Clk of the modulo-128 counter, and the control terminal is connected to the carry terminal C of the modulo-128 counter.

3. The phase-adjustable ADPLL circuit of claim 2, wherein, The phase-adjustable module includes a 2-to-1 data selector MUX2, an adder, and a 4-to-1 data selector MUX3. The sampled signal PD_Q[39:0] obtained by the D flip-flop is simultaneously input to the phase-adjustable module for processing. The control signals S1 and S0 of the 4-to-1 data selector MUX3 select one data from the four input data and add it to the sampled signal PD_Q[39:0]. The resulting sum signal is input to the D1 terminal of the 2-to-1 data selector MUX2. The D0 terminal of the 2-to-1 data selector MUX2 is the sampled signal PD_Q[39:0]. The control signal of the 2-to-1 data selector MUX2 is the lock signal Lock. When the Lock value is 1, the data output of the D1 terminal is selected, which is the adjusted phase difference signal PD_adj[39:0].

4. The phase-adjustable ADPLL circuit of claim 3, wherein, The data terminal D00 of the four-to-one data selector MUX3 is connected to a fixed value 40'h1, the data terminal D01 is connected to a fixed value 40'h2, the data terminal D10 is connected to a fixed value 40'h4, the data terminal D11 is connected to a fixed value 40'h8, the output terminal is connected to one end of the adder, and the two control terminals are connected to control signals S1 and S0 respectively. One input of the adder is connected to the output Q of the D flip-flop, and the other input is connected to the output of the 4-to-1 data selector MUX3. The output of the adder is connected to the data terminal D1 of the 2-to-1 data selector MUX2. The data terminal D0 of the two-to-one data selector MUX2 is connected to the output terminal Q of the D flip-flop, the data terminal D1 is connected to the output terminal of the adder, the output terminal outputs the adjusted phase difference signal PD_adj[39:0], and the control terminal is connected to the carry terminal C of the modulo-128 counter.

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