Wafer stacking structure and testing method thereof, high-bandwidth memory and preparation method thereof

Abstract

A wafer stacking structure and a test method thereof, a high-bandwidth memory and a preparation method thereof, relate to the field of semiconductor storage technology, and can solve the problem of low production yield of wafer stacking structures in the prior art, resulting in high production cost of high-bandwidth memory. The test method tests the wafer stacking structure, wherein a logic wafer (10) and a multi-layer storage wafer (20) in the wafer stacking structure are connected via a bus (30), the bus (30) records the layer address of each storage wafer (20) in the wafer stacking structure, and a probe (40) reads the layer address and detection information corresponding to the three-dimensional layer address to be tested, and can adjust the connection state of a cutting unit (201) in the wafer stacking structure, so that the high-bandwidth memory obtained by cutting can address and shield the layer where the inferior storage chip is located, thereby adjusting the actual storage capacity of the high-bandwidth memory, and providing a plurality of high-bandwidth memories with partial capacity reduction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a wafer stacking structure and a testing method thereof, a high-bandwidth memory and a preparation method thereof. Background Art

[0002] High Bandwidth Memory (HBM) is a high-performance dynamic random access memory (DRAM) based on a 3D stacking process. It is suitable for applications with high bandwidth requirements and is usually used in conjunction with high-performance graphics accelerators or network devices. It was adopted by JEDEC (Joint Electron Device Engineering Council) as an industry standard in 2013.

[0003] The 3D stacking process is used to prepare high-bandwidth memory. Through Silicon Via (TSV) technology and micro-bump technology are used to achieve stacking and hierarchical interconnection of multi-layer DRAM chips and logic chips. Compared with the planar structure, it can effectively increase the storage capacity without expanding the planar area. The stacking methods for preparing high-bandwidth memory usually include Die to Die (D2D, chip to chip stacking) and Wafer to Wafer (W2W, wafer to wafer stacking). The Die to Die method can perform yield testing on each cutting unit (chip structure before cutting and packaging, Die) on the wafer at each stacked wafer level, so as to screen KGD (Known Good Die) to improve the yield of the prepared high-bandwidth memory. However, due to process limitations and die-by-die KGD screening, the improvement of the interconnection density on the chip is limited, and the preparation efficiency is low.

[0004] In the wafer to wafer stacking method, the yield test is usually carried out after all the multi-level wafers are stacked. In the existing technology, the yield of each single-level wafer can usually reach about 90%. However, as the number of wafer stacking layers increases, the yield of the finished high-bandwidth memory product will decrease exponentially. In the stacked wafer structure, the cutting unit yield test shows that it is a defective product and cannot be removed and replaced, which leads to a significant increase in the production cost of good high-bandwidth memory. Summary of the invention

[0005] The present application provides a wafer stacking structure and a testing method thereof, a high-bandwidth memory and a preparation method thereof, which can solve the problem in the prior art that the production yield of the wafer stacking structure is low, resulting in high production cost of the high-bandwidth memory.

[0006] According to a first aspect of an embodiment of the present application, a testing method for a wafer stacking structure is provided. The testing method is applied to a testing machine, which is used to test a wafer stacking structure. The wafer stacking structure includes a logic wafer and a multi-layer storage wafer stacked in sequence. The logic wafer and the multi-layer storage wafer are connected via a bus. The logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the multi-layer storage wafer via the bus. A probe of the testing machine is used to connect to the logic wafer. The method includes: obtaining a three-dimensional layer address to be tested, the three-dimensional layer address being used to respectively indicate the hierarchical address corresponding to each layer of storage wafer in the multi-layer storage wafer; according to the three-dimensional layer address, the probe reads detection information of the storage wafer corresponding to the three-dimensional layer address via the bus through the hierarchical address port of the logic wafer, the detection information being used to indicate the quality of the cutting unit in the storage wafer corresponding to the three-dimensional layer address.

[0007] The test method of the embodiment of the present application tests a wafer stacking structure, wherein the logic wafer and the multi-layer storage wafer in the wafer stacking structure are connected via a bus, the bus records the hierarchical address of each storage wafer in the wafer stacking structure, and the logic wafer includes a hierarchical address port for transmitting the hierarchical address between the multi-layer storage wafers. By obtaining the three-dimensional layer address to be tested, the probe reads the hierarchical address of each layer of the multi-layer storage wafer corresponding to the three-dimensional layer address to be tested through the hierarchical address port of the logic wafer via the bus, and the quality of the cutting unit in the storage wafer containing the corresponding hierarchical address can be detected. The information can be read, and the read detection information can be combined with the preparation process to adjust the connection status of the cutting unit in the wafer stacking structure, including performing corresponding repairs or shielding of inferior products, so that the high-bandwidth memory obtained by cutting the wafer stacking structure can achieve addressing and shielding for the layer where the corresponding storage chip marked as inferior is located, so that data is no longer accessed from the shielded storage chip during the use of the high-bandwidth memory. By adjusting the actual storable capacity in the high-bandwidth memory, a variety of high-bandwidth memories with partial capacity reduced are provided, thereby improving the preparation yield of the high-bandwidth memory and reducing the production cost of the high-bandwidth memory.

[0008] In a first possible implementation of the first aspect, according to the three-dimensional layer number address, after the probe reads the detection information of the storage wafer at the layer address corresponding to the three-dimensional layer number address through the layer address port of the logic wafer via the bus, the method also includes: outputting repair indication information according to the detection information, and the repair indication information is used to indicate the repairable position information in the cutting unit. Outputting the corresponding repair indication information according to the detection information can indicate the repairable position in the cutting unit to support the repair of the wafer stacking structure after the test, thereby improving the preparation yield of the wafer stacking structure.

[0009] In a second possible implementation of the first aspect, the detection information includes: an identification of the cutting unit, the number of failed storage units in the storage area of ​​each cutting unit, and position information of the failed storage units, and the identification of the cutting unit is used to indicate the two-dimensional row address and the two-dimensional column address of the cutting unit. The number and position of the failed storage units in the storage area of ​​the cutting unit are obtained through the detection information, and the two-dimensional row address and the two-dimensional column address can accurately indicate the position of the cutting unit on the storage wafer where the cutting unit is located, thereby providing more accurate repair indication information.

[0010] In a third possible implementation of the first aspect, the detection information further includes: the number of redundant storage units in each cutting unit; outputting repair instruction information based on the detection information, including: determining whether each cutting unit is repairable based on the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit; outputting repair instruction information when the cutting unit is repairable. Determine whether each cutting unit is repairable based on the number of failed storage units and the number of redundant storage units in the acquired storage area, and output repair instruction information when confirming that the cutting unit is repairable, so as to support repair in subsequent wafer stacking structure preparation.

[0011] In a fourth possible implementation of the first aspect, outputting the repair instruction information includes: when the cutting unit is repairable, determining the position information of the repairable storage unit in the repairable cutting unit; and outputting the position information of the repairable storage unit in the repairable cutting unit. In this way, in the repair process of preparing the wafer stacking structure, the position information of the repairable storage unit in the repairable cutting unit can be obtained according to the repair instruction information for repair, thereby improving the preparation yield of the wafer stacking structure by repairing the repairable storage unit.

[0012] In a fifth possible implementation of the first aspect, after determining whether each cutting unit is repairable based on the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit, the method further includes: when the cutting unit is not repairable, determining that the cutting unit is a defective product and outputting a defective product identification. For the cutting unit determined to be unrepairable, the output defective product identification can shield the corresponding defective cutting unit according to the defective product identification during the preparation process of the wafer stacking structure, thereby obtaining a high-bandwidth memory whose storage capacity can be flexibly adjusted according to the specific preparation results.

[0013] According to a second aspect of an embodiment of the present application, a method for preparing a high-bandwidth memory is provided. The high-bandwidth memory is obtained by cutting a wafer stacking structure. The wafer stacking structure includes logic wafers and multi-layer storage wafers stacked in sequence. The logic wafer and the multi-layer storage wafer are connected via a bus. The logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the multi-layer storage wafer via the bus. The preparation method includes: obtaining detection information output by a tester, the detection information is used to indicate the quality of a cutting unit in a storage wafer detected according to a three-dimensional layer address and a corresponding hierarchical address; adjusting the cutting unit in the wafer stacking structure according to the detection information. The connection state includes the signal connection relationship between the cutting unit and other cutting units located at adjacent levels; the wafer stacking structure after cutting adjustment is obtained to obtain a high-bandwidth memory, the high-bandwidth memory includes: a cutting unit for a logic wafer and a cutting unit for each stacked storage wafer, wherein the cutting unit for the logic wafer and the cutting unit for the multi-layer storage wafer are connected through a bus, the cutting unit for the logic wafer includes a hierarchical address port for transmitting a hierarchical address with the cutting unit for the multi-layer storage wafer through the bus, the cutting unit for the logic wafer serves as a logic chip, and the cutting unit for the storage wafer serves as a storage chip.

[0014] The bus records the hierarchical address of each storage wafer, so that the logic wafer can address the multi-layer storage wafer through the hierarchical address port and transmit data through the bus. When the detection information includes a cutting unit indicated as a defective product, the wafer stacking structure can be adjusted by adjusting the signal connection relationship between the cutting unit and other cutting units located at adjacent levels, so that the high-bandwidth memory obtained after cutting can shield the memory chip indicated as a defective product, thereby obtaining a high-bandwidth memory whose storage capacity can be flexibly adjusted according to the specific preparation results.

[0015] In a first possible implementation of the second aspect, the detection information includes: an identification of the cutting unit, the number of failed storage units in the storage area of ​​each cutting unit, and location information of the failed storage unit, and the identification of the cutting unit is used to indicate the two-dimensional row address and the two-dimensional column address of the cutting unit. By using the two-dimensional row address and the two-dimensional column address of the cutting unit as an indication of the cutting unit identification, the location of the cutting unit to be repaired on the storage wafer can be accurately known, so that, according to the detection information, the circuit originally connected to the failed storage unit can be bypassed and connected to the corresponding redundant storage unit, that is, the redundant storage unit can replace the work of the failed storage unit.

[0016] In a second possible implementation of the second aspect, the detection information also includes: the number of redundant storage units in each cutting unit; before cutting the adjusted wafer stacking structure and obtaining the high-bandwidth memory, the method also includes: determining the position information of the repairable storage unit in the repairable cutting unit according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit; locating the repairable storage unit according to the position information of the repairable storage unit, bypassing the connection of the repairable storage unit, and correspondingly connecting to the redundant storage unit. In this way, before cutting the wafer stacking structure and subsequent packaging processing to obtain the high-bandwidth memory, the repairable cutting unit can be repaired first, and the ones that are still failed or cannot be repaired after the repair are shielded. Whether the cutting unit is a repairable cutting unit is determined by whether the redundant storage units in the redundant area can meet the number of corresponding replacement failed storage units. For the repairable cutting unit, the repair can be achieved by locating the position information and replacing the connection.

[0017] In a third possible implementation of the second aspect, the connection state of the cutting unit in the wafer stacking structure is adjusted according to the detection information, including: shielding the cutting unit indicated as a defective product in the detection information. The shielding operation is performed on the cutting unit indicated as a defective product, and the address information of the shielded cutting unit is recorded and marked. When used as a high-bandwidth memory after cutting, the data transmission shields the storage chip corresponding to the marked address, and the storage chip is no longer used to access data, while the storage chips at other levels can access data normally.

[0018] According to a third aspect of an embodiment of the present application, a wafer stacking structure is provided, comprising a logic wafer and a multi-layer storage wafer stacked in sequence, wherein the logic wafer and the multi-layer storage wafer are connected via a bus, and the logic wafer includes a hierarchical address port.

[0019] The hierarchical address port is used to connect to the address bus in the bus to transmit the hierarchical address of the multi-layer storage wafer. When the cutting unit in a certain hierarchical storage wafer is indicated as defective according to the test result of the test machine, the hierarchical address can be used to accurately address the hierarchical level of the storage wafer where the cutting unit indicated as defective is located, so that the cutting unit indicated as defective can be marked in a shielding manner, and data is no longer accessed in the cutting unit, thereby making the wafer stacking structure containing the defective cutting unit still usable after shielding, thereby improving the preparation yield of the high-bandwidth memory formed after cutting.

[0020] In a first possible implementation of the third aspect, the bus records the hierarchical address of each storage wafer, and the hierarchical address port on the logic wafer is used to transmit the hierarchical address of each storage wafer. The wafer stacking structure of the embodiment of the present application can accurately address the storage wafers of each layer and confirm the location of the corresponding storage wafer required for data access.

[0021] In a second possible implementation of the third aspect, the logic wafer and the multi-layer memory wafer are interconnected through silicon vias or hybrid bonding buses. Both the through silicon vias and hybrid bonding methods have good connection reliability and low process cost, and have good heat dissipation and a compact structure of the prepared high-bandwidth memory, which is conducive to the miniaturization of the device structure using the high-bandwidth memory.

[0022] According to a fourth aspect of an embodiment of the present application, a high-bandwidth memory is provided, comprising a logic chip and a multi-layer memory chip stacked in sequence, wherein the logic chip and the multi-layer memory chip are connected via a bus, the bus records the hierarchical address of each memory chip, and the logic chip comprises a hierarchical address port for transmitting the hierarchical address to the multi-layer memory chip via the bus.

[0023] The hierarchical address port is used to connect to the address bus in the bus to transmit the hierarchical address of the multi-layer storage wafer. Thus, by adjusting the connection state such as shielding or repairing after addressing, a high-bandwidth memory whose storage capacity can be flexibly adjusted according to the specific preparation results after cutting can be obtained, thereby improving the preparation yield of the high-bandwidth memory formed after cutting.

[0024] In a first possible implementation of the fourth aspect, the multi-layer memory chip includes at least one layer of shielded memory chips. According to the test results of the tester, and the addressing, shielding or repair of the cutting unit in the wafer stacking structure after the test, the actual storage capacity of the high-bandwidth memory obtained after cutting is adjusted, and a plurality of high-bandwidth memories with partial capacity reduced can be provided, thereby improving the preparation efficiency and preparation yield of the high-bandwidth memory and reducing the production cost of the high-bandwidth memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 One of the structural schematic diagrams of a wafer stacking structure provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a wafer stack structure provided in an embodiment of the present application being tested by a probe of a testing machine;

[0027] Figure 3 One of the flow charts of a method for testing a wafer stacking structure provided in an embodiment of the present application;

[0028] Figure 4 A test logic relationship diagram of a test method for a wafer stacking structure provided in an embodiment of the present application;

[0029] Figure 5 A second flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application;

[0030] Figure 6A third flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application;

[0031] Figure 7 A fourth flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application;

[0032] Figure 8 A fifth flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application;

[0033] Fig. 9 A second structural schematic diagram of a wafer stacking structure provided in an embodiment of the present application;

[0034] Fig.10 One of the flow charts of a method for preparing a high-bandwidth memory provided in an embodiment of the present application;

[0035] Fig.11 A schematic diagram of the formation relationship of obtaining a high-bandwidth memory by cutting a wafer stack structure provided in an embodiment of the present application;

[0036] Fig.12 A second flowchart of a method for preparing a high-bandwidth memory provided in an embodiment of the present application;

[0037] Fig.13 A third flow chart of a method for preparing a high-bandwidth memory provided in an embodiment of the present application;

[0038] Fig.14 A schematic diagram of the structure of a high-bandwidth memory provided in an embodiment of the present application.

[0039] Icons: 10-logic wafer; 101-cutting unit of logic wafer; 11-logic chip; 20-storage wafer, 201-cutting unit of storage wafer; 21-storage chip; 30-bus; 40-probe. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0042] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0043] In the description of the embodiments of the present application, it should be noted that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0044] In the description of the embodiments of the present application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0045] The stacking methods for preparing high-bandwidth memory usually include Die to Die (D2D, chip stacking) and Wafer to Wafer (W2W, wafer stacking).

[0046] The Die to Die method refers to testing and screening each cutting unit (chip structure before cutting and packaging, Die) as a unit, first testing and screening each cutting unit to be stacked, and selecting the KGD (Known Good Die) that has passed the test for stacking, so as to achieve a high yield of the prepared high-bandwidth memory. However, the testing and screening of KGDs one by one makes the preparation efficiency of high-bandwidth memory prepared by stacking through the Die to Die method low. Moreover, due to the miniaturization of the volume of micro-bumps and the compactness of adjacent micro-bumps in the Die to Die preparation process, the size of the smallest physical repeating unit of the interconnected micro-bumps is relatively large, usually around 40μm, resulting in the limitation of the increase in the interconnection density on the chip. The overall volume of the prepared high-bandwidth memory is large. Moreover, since the Die to Die preparation process requires the use of underfill for interconnection, the thermal conductivity of the device is high and cannot meet the requirements of high-power heat dissipation.

[0047] Wafer to Wafer stacking is a whole-layer stacking method based on wafer levels, which can effectively improve the preparation efficiency. Wafer to Wafer stacking is usually performed after all multi-level wafers are stacked and then the yield test is performed. In the prior art, the preparation yield of each single-level wafer can usually reach about 90%. When multiple layers of wafers are stacked, their yield must meet the formula: p = αnβn-1; where α is the yield of a wafer, β is the yield of the stacking, and n is the number of stacked layers. It can be seen from the formula that as the number of wafer stacking layers increases, the yield of the finished high-bandwidth memory product decreases exponentially. In the wafer stacking structure prepared by the Wafer to Wafer stacking method, the logic wafer has no knowledge of the layer of storage wafers stacked thereon. Therefore, for the high-bandwidth memory obtained after cutting, if any layer of storage chip on the logic chip is detected as defective, the entire high-bandwidth memory will be unusable and can only be discarded as a defective product. As a result, the production cost of good high-bandwidth memory prepared by the Wafer to Wafer stacking method is greatly increased.

[0048] A test method for a wafer stacking structure provided in an embodiment of the present application is applied to a tester, which is used to test the wafer stacking structure. The test of the wafer stacking structure usually performed by the tester includes a DC test and a functional test. The tester usually includes a host (Tester) and a probe (prober), wherein the host is a controller for executing a test program, and the probe is connected to the wafer to be tested through a test probe to realize a signal connection with each test point (cutting unit) in the wafer to be tested.

[0049] Figure 1 One of the structural schematic diagrams of a wafer stacking structure provided in an embodiment of the present application is as follows: Figure 1 As shown, the wafer stacking structure includes a logic wafer 10 and a multi-layer storage wafer 20 stacked in sequence, and the logic wafer 10 and the multi-layer storage wafer 20 are connected via a bus 30 ( Figure 1 In the figure, a four-layer storage wafer 20 is taken as an example, and the same applies below. The logic wafer 10 sends a control signal to transmit and store data to the storage wafer 20 through the bus 30. Figure 2 A schematic diagram of a wafer stack structure provided in an embodiment of the present application being tested by a probe of a testing machine, such as Figure 2 As shown, the probe 40 of the tester is used to connect with the logic wafer 10. Figure 1 For the wafer stacking structure in, the probe 40 of the tester is connected to the test port (pad) reserved on the logic wafer 10. Through the connection with the logic wafer 10, the connection with the multi-layer storage wafer 20 stacked on the logic wafer 10 is realized. In one embodiment, the test port reserved on the logic wafer 10 corresponds to the cutting unit 101 on each logic wafer 10, and the cutting unit 101 on each logic wafer 10 is interconnected with the cutting unit 201 of the multi-layer storage wafer 20 stacked on the cutting unit 101. The hierarchical address of each storage wafer 20 is recorded on the bus 30. Therefore, by connecting the probe 40 of the tester to the test port on the logic wafer 10, each layer of the storage wafer 20 can be addressed for testing.

[0050] Figure 3 A flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application is shown in FIG. Figure 3 The method is executed by a testing machine.

[0051] The test method of the wafer stacking structure provided in the embodiment of the present application includes:

[0052] S101. Obtain a three-dimensional layer address to be tested, where the three-dimensional layer address is used to indicate a layer address corresponding to each layer of a storage wafer in a multi-layer storage wafer.

[0053] In the wafer stacking structure, Figure 1Taking the structural schematic diagram of the wafer stacking structure shown in as an example, the multi-layer storage wafers 20 stacked on the logic wafer 10 have their own hierarchical addresses recorded on the bus 30. The logic wafer 10 is provided with a corresponding port for the signal transmission corresponding to the bus 30, wherein the hierarchical address port provided on the logic wafer 10 is used to transmit the hierarchical address of the multi-layer storage wafer 20, and the hierarchical address is transmitted through the hierarchical address port and in the address bus of the bus 30, and the hierarchical address of each layer of the storage wafer 20 is recorded and read accordingly. The three-dimensional layer number address corresponds to the hierarchical address of each layer of the storage wafer 20 of the multi-layer storage wafer 20 respectively. The test machine obtains the three-dimensional layer number address to be tested, that is, it can correspond to the hierarchical address of a specific layer in the multi-layer storage wafer 20, so as to determine the level of the wafer to be tested currently tested in the test machine in the wafer stacking structure.

[0054] Among them, the three-dimensional layer address to be tested can be written in the test program preset by the tester, and the probe 40 of the tester is connected to the test port (pad) reserved on the logic wafer 10, and the test program in the tester is run, and the multi-layer storage wafer 20 can be tested separately through the three-dimensional layer address added in the test program, or, it is also possible not to change the preset test program in the tester, but to indicate the three-dimensional layer address to be tested to the tester through an external signal, and the tester detects the storage wafer 20 of the corresponding level address according to the three-dimensional layer address of the external signal. In the embodiment of the present application, the data source of the three-dimensional layer address is not limited. It is sufficient to obtain the three-dimensional layer address to be tested and address it corresponding to the level address of the multi-layer storage wafer 20.

[0055] S102. According to the three-dimensional layer address, the probe reads detection information of the storage wafer corresponding to the layer address of the three-dimensional layer address through the layer address port of the logic wafer via the bus, and the detection information is used to indicate the quality of the cutting unit in the storage wafer corresponding to the three-dimensional layer address.

[0056] Fig. 9 The second structural diagram of a wafer stacking structure provided in an embodiment of the present application is as follows: Fig. 9 As shown, each layer of the storage wafer 20 includes a plurality of cutting units 201, which are used as the storage chips 21 of the layer in each high-bandwidth memory after cutting. Each cutting unit 201 has a unique and clear physical position on the storage wafer 20. The cutting units 201 on the multi-layer storage wafer 20 are stacked and electrically connected in the hierarchical direction. The stacked cutting units 201 form a stacked high-bandwidth memory structure after subsequent cutting and packaging steps. The test machine determines the level of the current storage wafer 20 to be detected by corresponding the level address of the three-dimensional layer number address, and reads the detection information of the storage wafer 20 of the level accordingly. The detection information includes the quality of each cutting unit 201 on the storage wafer 20.

[0057] The logic wafer 10 and the multi-layer storage wafer 20 are connected via a bus 30, and the bus 30 records and transmits information of the storage wafer 20. In one embodiment, the bus 30 may include an address bus, a data bus, and a control bus, and corresponding ports are respectively provided on the logic wafer 10. The logic wafer 10 includes a hierarchical address port, and the hierarchical address can be transmitted between the hierarchical address port and the multi-layer storage wafer 20 via the bus 30. The logic wafer 10 is connected to the address bus in the bus 30 via the hierarchical address port, and the hierarchical address is transmitted between the multi-layer storage wafers 20 connected to the bus 30. For example, Figure 4 A test logic relationship diagram of a test method for a wafer stacking structure provided in an embodiment of the present application, such as Figure 4 As shown, the address bus includes a hierarchical address port (HI.Add) for transmitting the hierarchical address of each storage wafer 20, and a two-dimensional address port for the two-dimensional address of each cutting unit 201 on the storage wafer 20, and the data bus includes a test data input port (TDI) for transmitting test data information, and a corresponding test mode selection (TMS) and a corresponding port for receiving a test clock signal (TCK).

[0058] The tester tests the wafer stacking structure by acquiring the address of the three-dimensional layer to be tested, which corresponds to the layer address of a specific storage wafer 20 to be tested in the wafer stacking structure. The tester tests each cutting unit 201 of the storage wafer 20 in the layer according to the test items according to the written test program. The tester inputs the corresponding address information and data information through the port respectively, accesses the cutting unit 201 in the storage wafer 10 after conversion by the circuit in the logic wafer 10, and the measured detection information is received by the tester after being processed by the circuit in the logic wafer 10.

[0059] In one embodiment, after completing the test of the layer of storage wafer 20, the above steps can be repeated to determine other storage wafers 20 with corresponding layer addresses according to different three-dimensional layer addresses, and then test each cutting unit 201 of the storage wafer 20 until the layer-by-layer testing of the stacked multi-layer storage wafers 20 is completed.

[0060] Taking the test of a certain layer of storage wafer 20 as an example, the physical position of each cutting unit 201 on the storage wafer 20 is indicated by a two-dimensional row address and a two-dimensional column address. According to the clock signal (TCK), the probe 40 sequentially accesses, reads and records the information of each cutting unit 201 in a row-by-row or column-by-column manner as the detection information of the storage wafer 20 of this layer. The detection information can indicate the quality of each cutting unit 201 in the storage wafer 20 of this layer according to the information of each cutting unit 201.

[0061] Through the above-mentioned test method, after the test is completed, the test machine can know the quality of each cutting unit 201 on each layer of storage wafer 20 in the wafer stacking structure, and can clearly know the two-dimensional address on the storage wafer 20 where each cutting unit 201 is located and the hierarchical address where the storage wafer 20 is located. In this way, the inferior cutting unit 201 can be addressed and shielded as needed, and the shielded cutting unit 201 will not access data in the use of the high-bandwidth memory formed subsequently, and the good cutting units 201 of other levels can normally access data in the formed high-bandwidth memory, which is equivalent to reducing the layer and reducing the capacity of the corresponding layer before use, so that the memory that was originally unusable can be optimized and used, which improves the preparation yield of the wafer stacking structure and reduces the production cost of preparing the high-bandwidth memory.

[0062] In one embodiment, the detection information gives a direct indication result of the quality of the cutting unit 201. The detection information obtains the connectivity and data accessibility status of each storage unit in the cutting unit 201, determines the availability of each storage unit, and derives whether the cutting unit 201 is good or bad according to the availability of the storage units in the cutting unit 201. For example, if the storage units in the cutting unit 201 are all valid, or by recording the number of storage units tested as failed in the cutting unit 201 and comparing it with the number of redundant storage units preset in the cutting unit 201, if the number of failed storage units is less than the number of redundant storage units preset, the failed storage units can be repaired by replacing the lines, and the cutting unit 201 can be indicated as good by the detection information; on the contrary, by recording the number of storage units tested as failed in the cutting unit 201 and comparing it with the number of redundant storage units preset in the cutting unit 201, if the number of failed storage units is greater than the number of redundant storage units preset, the cutting unit 201 can be indicated as bad by the detection information. The quality of the cutting unit 201 in the specific level of the storage wafer 20 directly indicated by the detection information provides a basis for the corresponding steps in the subsequent preparation method to adjust the signal connection relationship between the cutting unit 201 and other cutting units 201 located at adjacent levels.

[0063] It should be noted that, in the embodiments of the present application, there is no limitation on the specific information form of the detection information, and the specific information form can be set according to the test program written in the tester. In one embodiment, the detection information can give a direct or indirect indication of the quality of the cutting unit 201, or, in another embodiment, the detection information may not reflect the quality, and other devices or terminals interpret the detection information and make a judgment. The detection information can include the layer address of the storage wafer 20 corresponding to the three-dimensional layer address, and the corresponding information that can indicate the quality of the cutting unit 201 in the storage wafer 20 of this layer. The embodiment of the present application provides a wafer stacking structure and a test method thereof, a high-bandwidth memory and a preparation method thereof. The test method of the wafer stacking structure is applied to a test machine, and the test machine is used to test the wafer stacking structure. The wafer stacking structure includes logic wafers and multi-layer storage wafers stacked in sequence, and the logic wafers and the multi-layer storage wafers are connected through a bus. The logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the multi-layer storage wafer through the bus. The probe of the test machine is used to connect with the logic wafer. The method includes: obtaining a three-dimensional layer address to be tested, and the three-dimensional layer address is used to respectively indicate the hierarchical address corresponding to each layer of storage wafer in the multi-layer storage wafer; according to the three-dimensional layer address, the probe reads the detection information of the storage wafer with the hierarchical address corresponding to the three-dimensional layer address through the hierarchical address port of the logic wafer via the bus, and the detection information is used to indicate the quality of the cutting unit in the storage wafer corresponding to the three-dimensional layer address. The test method of the embodiment of the present application tests a wafer stacking structure, wherein the logic wafers in the wafer stacking structure are respectively connected to the multi-layer storage wafer bus through the hierarchical address port, and the bus records the hierarchical address of each storage wafer in the wafer stacking structure. By obtaining the three-dimensional layer address to be tested and reading the hierarchical address corresponding to the three-dimensional layer address to be tested through a probe, the detection information of the quality of the cutting unit in the storage wafer corresponding to the hierarchical address can be read, and the read detection information can be combined with the preparation process to adjust the connection state of the cutting unit in the wafer stacking structure, including performing corresponding repair or inferior product shielding, so that the high-bandwidth memory obtained by cutting the wafer stacking structure can achieve addressing shielding for the layer where the corresponding storage chip marked as inferior is located, so that data is no longer accessed from the shielded storage chip during the use of the high-bandwidth memory, and a plurality of high-bandwidth memories with partial capacity reduced are provided by adjusting the actual storable capacity in the high-bandwidth memory, thereby improving the preparation yield of the high-bandwidth memory and reducing the production cost of the high-bandwidth memory.

[0064] Optionally, for the case where the row address and the column address jointly indicate the two-dimensional address of the cutting unit 201 on the storage wafer 20 where it is located, and the corresponding repair operation can be performed on the wafer stacking structure under test according to actual needs after the test, the detection information includes: the identification of the cutting unit 201, the number of failed storage cells in the storage area of ​​each cutting unit 201, and the location information of the failed storage cells. The identification of the cutting unit 201 is used to indicate the two-dimensional row address and the two-dimensional column address of the cutting unit 201.

[0065] Figure 5 The second flowchart of a wafer stacking structure testing method provided in an embodiment of the present application, in step S102, according to the three-dimensional layer address, the probe reads the detection information of the storage wafer corresponding to the layer address of the three-dimensional layer address through the layer address port of the logic wafer through the bus, such as Figure 5 As shown, the testing method of the embodiment of the present application also includes:

[0066] S103. Outputting repair indication information according to the detection information, where the repair indication information is used to indicate repairable position information in the cutting unit.

[0067] For each cutting unit 201 on the storage wafer 20, in one embodiment, during design, each cutting unit 201 is divided into a mutually isolated storage area and a redundant area, wherein the storage area includes multiple storage units, and the redundant area also includes multiple redundant storage units (Redundancy). It should be understood that the sum of the capacities of the multiple storage units in the storage area is the storage capacity of the cutting unit 201. The redundant storage units in the redundant area are prepared as backups, and may not play a role in data access in the actual use of the cutting unit 201 after cutting, and need to be determined according to specific wiring connections.

[0068] During the preparation process of the cutting unit 201, it cannot be guaranteed that the multiple storage units in the storage area can always be effectively available during the preparation and interconnection process. The quality of the wafer itself, the error during preparation, and the influence of external factors may cause some storage units in the storage area to fail. Therefore, redundant storage units in the redundant area are preset during design. In one embodiment, the ratio of the number of redundant storage units to the number of storage units on the cutting unit 201 is about 1:10. In this way, if some storage units in the storage area fail during the preparation process, such as being determined as failed units during electrical testing, there is still a chance to replace them with redundant storage units in the redundant area for repair.

[0069] The detection information includes a cutting unit 201 identifier, which is used to indicate the two-dimensional row address and two-dimensional column address of the cutting unit 201. The physical position of each cutting unit 201 on the storage wafer 20 is determined by the cutting unit 201 identifier. Since the physical position of each cutting unit 201 is immutable after the storage wafer 20 is stacked, the cutting unit 201 at each physical position on the storage wafer 20 can be clearly indicated by the cutting unit 201 identifier. In addition, the detection information also includes the number of failed storage units in the storage area of ​​each cutting unit 201 and the position information of all failed storage units. When repairing the failed storage units in the cutting unit 201, the position of each failed storage unit in the cutting unit 201 can be found according to the number of failed storage units and the position information of all failed storage units. In this way, the repair indication information can be output according to the detection information to indicate the repairable position information in the cutting unit 201. By including the repair indication information indicating the repairable position information, the cutting unit 201 to be repaired can be addressed and repaired.

[0070] Since the cutting unit 201 is pre-set with a redundant area during design, a redundant storage unit is arranged in the redundant area, and the redundant storage unit has the same structure and function as the storage unit in the storage area, the redundant storage unit can be replaced with the storage unit one-to-one by adjusting the line connection when necessary. Optionally, the detection information also includes: the number of redundant storage units in each cutting unit 201. Figure 6 The third flowchart of a method for testing a wafer stack structure provided in an embodiment of the present application, in the testing method of the present application, Figure 6 As shown, step S103, outputting repair instruction information according to the detection information, includes:

[0071] S1031, determining whether each cutting unit is repairable according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit;

[0072] S1032. When the cutting unit can be repaired, output repair instruction information.

[0073] Since the number of failed memory cells in the storage area obtained by the test in the cutting unit 201 is unpredictable, if the number of redundant memory cells in the preset redundant area is too large, a large number of redundant memory cells will be idle, which will increase the preparation cost and also affect the miniaturization of the prepared high-bandwidth memory. If the number of redundant memory cells in the preset redundant area is too small, the repairability will be reduced, affecting the production yield of the high-bandwidth memory.

[0074] In one embodiment, the redundant storage cells preset in the redundant area are usually divided and set according to a ratio of about 1:10 to the number of storage cells set. If some storage cells in the storage area are wrong during the preparation process and are determined to be failed during the electrical test, they can also be replaced by the redundant storage cells in the redundant area for repair. For example, if the storage area includes 1000 storage cells, 100 redundant storage cells are set in the redundant area. The cutting unit 201 is electrically tested by the probe 40. If it is measured that some storage cells in the storage area are failed, and the number of failed storage cells is less than the number of redundant storage cells, it can be determined that the cutting unit 201 is repairable.

[0075] When the cutting unit 201 is repairable, repair instruction information is output.

[0076] Figure 7 A fourth flow chart of a method for testing a wafer stack structure provided in an embodiment of the present application is as follows: Figure 7 As shown, step S1032 outputs repair instruction information when the cutting unit is repairable, including:

[0077] S10321. When the cutting unit is repairable, determine the location information of the repairable storage unit in the repairable cutting unit;

[0078] S10322. Output the location information of the repairable storage unit in the repairable cutting unit.

[0079] According to the comparison between the number of failed storage units and the number of redundant storage units in the cutting unit 201, if the number of failed storage units in the cutting unit 201 is less than the number of redundant storage units, the cutting unit 201 is confirmed to be repairable, and the position information of the repairable storage units in the repairable cutting unit 201 is determined, and the position information of the repairable storage units in the repairable cutting unit 201 is output. In this way, the corresponding failed storage unit can be addressed according to the repair indication information, the circuit connection of the failed storage unit can be modified, and the failed storage unit can be replaced with a redundant storage unit to complete the repair.

[0080] Figure 8 The fifth flowchart of a method for testing a wafer stack structure provided by an embodiment of the present application, step S1031 determines whether each cutting unit is repairable according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit. Figure 8 As shown, the test method also includes:

[0081] S1033. When the cutting unit cannot be repaired, determine that the cutting unit is a defective product, and output a defective product identification.

[0082] In one embodiment, the number of redundant storage units in the redundant area is set according to a conventional ratio or a ratio required by the design. Therefore, not all cutting units 201 can be repaired when it is detected that there are failed storage units in the storage units. If the number of failed storage units in the cutting unit 201 is greater than the number of redundant storage units, the cutting unit 201 is unrepairable. Alternatively, in another embodiment, after the repairable cutting unit 201 is repaired, an electrical test is required for inspection. If the repairable cutting unit 201 after replacement of the redundant storage unit still fails to pass the electrical test, the repair of the cutting unit 201 is unsuccessful, and the cutting unit 201 can also be considered unrepairable. The unrepairable cutting unit 201 will be marked as a defective product and a defective product identification will be output. The cutting unit 201 marked as defective will be abandoned after the wafer stacking structure is cut. For example, as described above, for the storage chip formed by the cutting unit 201 marked as defective in the high-bandwidth memory structure formed after cutting, the access to data in the storage chip of this layer can be abandoned by masking the address, and it will not affect the data access of storage chips in other levels.

[0083] Another aspect of the present application provides a method for preparing a high-bandwidth memory, wherein the high-bandwidth memory is obtained by cutting a wafer stack structure. The method is performed by a preparation device, Fig. 9 Another structural schematic diagram of a wafer stacking structure provided in an embodiment of the present application is as follows: Fig. 9 As shown, the wafer stacking structure is Fig. 9 The wafer stacking structure includes a logic wafer 10 and a multi-layer storage wafer 20 stacked in sequence, the logic wafer 10 and the multi-layer storage wafer 20 are connected through a bus 30, and the logic wafer 10 includes a hierarchical address port for transmitting hierarchical addresses to the multi-layer storage wafer 20 through the bus 30.

[0084] Fig.10 One of the flow charts of a method for preparing a high-bandwidth memory provided in an embodiment of the present application is as follows: Fig.10 As shown, the method for preparing the high-bandwidth memory of the embodiment of the present application includes:

[0085] S201. Acquire detection information output by a tester, where the detection information is used to indicate the quality of a cutting unit in a storage wafer detected according to a three-dimensional layer address and a corresponding layer address.

[0086] S202, adjusting the connection state of the cutting unit in the wafer stacking structure according to the detection information, the connection state including the connection relationship between the cutting unit and other cutting units located at adjacent levels.

[0087] S203, cutting the adjusted wafer stacking structure to obtain a high-bandwidth memory, wherein the high-bandwidth memory includes: a cutting unit for the logic wafer and a cutting unit for each stacked storage wafer, wherein the cutting unit for the logic wafer and the cutting unit for the multi-layer storage wafer are connected via a bus, the cutting unit for the logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the cutting unit for the multi-layer storage wafer via the bus, the cutting unit for the logic wafer serves as a logic chip, and the cutting unit for the storage wafer serves as a storage chip.

[0088] Those skilled in the art should know that the preparation process of the wafer stacking structure, before testing and repairing, must also include preparation process steps such as stacking and interconnection of the logic wafer 10 and the multi-layer storage wafer 20. In the embodiments of the present application, these preparation processes are not specifically limited. For example, it is not limited to stacking the multi-layer storage wafers 20 in sequence first and then stacking them with the logic wafer 10, or first setting the logic wafer 10 and then stacking the multi-layer storage wafers in sequence on the logic wafer 10. In one embodiment, the above-mentioned preparation process steps can adopt the preparation equipment and preparation process commonly used in the art, as long as the wafer stacking structure includes the logic wafer 10 and the multi-layer storage wafer 20 stacked in sequence, and the logic wafer 10 and the multi-layer storage wafer 20 are connected through the bus 30, the hierarchical address of each storage wafer 20 is recorded in the bus 30, and the logic wafer 10 includes a hierarchical address port, and the hierarchical address is transmitted between the logic wafer 10 and the multi-layer storage wafer 20 through the bus 30, so that the multi-layer storage wafer 20 can be addressed and data can be transmitted.

[0089] After the wafer stacking structure having the above structure is formed, the detection information output by the tester is obtained, and the detection information output by the tester is used to indicate the quality of the cutting unit 201 in the storage wafer 20 detected according to the three-dimensional layer address and the corresponding level address.

[0090] Based on the indication of the quality of each cutting unit 201 in a storage wafer 20 of a certain level by the detection information, in one embodiment, if the detection information indicates that a cutting unit 201 is a defective product, the connection status of the cutting unit 201 indicated as a defective product in the wafer stacking structure can be adjusted in the preparation equipment to obtain an adjusted wafer stacking structure, and the connection status includes the signal connection relationship between the cutting unit 201 and other cutting units 201 located at adjacent levels.

[0091] The adjustment method for changing the connection status of the cutting unit 201 indicated as a defective product in the wafer stacking structure includes, in one embodiment, marking the address of the cutting unit 201 indicated as a defective product (including a two-dimensional row address, a two-dimensional column address and a hierarchical address to determine the cutting unit 201 on the only storage wafer 20 in the wafer stacking structure) on the cutting unit 101 corresponding to the logic wafer 10, thereby shielding the cutting unit 201 indicated as a defective product through the addressing operation of the address bus, so that the shielded cutting unit 201 is no longer used to access data. Shielding the defective cutting unit 201 can also be performed in the preparation equipment, so that an adjusted wafer stacking structure is obtained.

[0092] The adjusted wafer stack structure is then cut through the preparation equipment to obtain high-bandwidth memory. Fig.11 A schematic diagram of the formation relationship of obtaining a high-bandwidth memory by cutting a wafer stack structure provided in an embodiment of the present application is shown in FIG. Fig.11 As shown, along Fig.11 The position indicated by the dotted line in the wafer stacking structure is cut. After cutting, the part in the dotted box on the right side of the arrow is a high-bandwidth memory. The high-bandwidth memory includes: a cutting unit 101 of the logic wafer 10 and a cutting unit 201 of each stacked storage wafer 20, wherein the cutting unit 101 of the logic wafer 10 and the cutting unit 201 of the multi-layer storage wafer 20 are connected through a bus 30, and the cutting unit 101 of the logic wafer 10 includes a hierarchical address port. The cutting unit 101 of the logic wafer 10 transmits the hierarchical address to the cutting unit 201 of the multi-layer storage wafer 20 through the hierarchical address port. The cutting unit 101 of the logic wafer 10 serves as a logic chip 11, and the cutting unit 201 of the storage wafer 20 serves as a storage chip 21.

[0093] It should be noted that those skilled in the art should know that Fig.11 The wafer stacking structure and the high-bandwidth memory after cutting shown in the figure are both hierarchical structures in the main viewing direction. In fact, in the top view plane of the wafer stacking structure, the storage wafer 20 should include cutting units 201 arranged in a matrix form with multiple rows and columns. Fig.11 Only a schematic diagram of cutting along the row direction or column direction is shown. In one embodiment, cutting is performed in both the row direction and the column direction in actual cutting. The top-view direction of the high-bandwidth memory formed after cutting only includes the area range of a cutting unit 101 of a logic wafer 10 or a cutting unit 201 of a storage wafer 20.

[0094] The detection information obtained in the preparation method of the embodiment of the present application comes from the test machine. The detection information detected by the test machine includes: the identification of the cutting unit 201, the number of failed storage units in the storage area of ​​each cutting unit 201, and the location information of the failed storage units. The identification of the cutting unit 201 is used to indicate the two-dimensional row address and the two-dimensional column address of the cutting unit 201.

[0095] In one embodiment, each cutting unit 201 is divided into mutually isolated storage areas and redundant areas during design. Redundant storage units are arranged in the redundant areas. The redundant storage units have the same structure and function as the storage units in the storage areas. When some storage units in the storage areas fail during the preparation process, the failed storage units can be replaced with redundant storage units in the redundant areas. In one embodiment, a specific method can be to bypass the circuit originally connected to the failed storage unit and then connect it to the corresponding redundant storage unit, that is, to replace the failed storage unit with the redundant storage unit.

[0096] To implement the above replacement to repair the cutting unit 201 of the failed storage unit, it is first necessary to know the position of the cutting unit 201 to be repaired on the storage wafer 20. In one embodiment, this information can be obtained by the two-dimensional row address and two-dimensional column address (identification of the cutting unit 201) of the cutting unit 201 indicated in the detection information. The identification of the cutting unit 201 is indicated in the form of a two-dimensional row address and a two-dimensional column address. In another embodiment, the identification of the cutting unit 201 can also be other information that can indicate the unique physical position of the cutting unit 201 on the storage wafer 20. After determining the position of the cutting unit 201 to be repaired on the storage wafer 20, it is also necessary to know the number of failed storage units in the storage area that needs to be repaired, as well as the position of each failed storage unit, so as to accurately address and repair during repair.

[0097] Since the cutting unit 201 is designed with a redundant area, the redundant storage unit set in the redundant area has the same structure and function as the storage unit set in the storage area, and the redundant storage unit can be replaced one-to-one with the storage unit by adjusting the line. Optionally, the detection information also includes: the number of redundant storage units in each cutting unit 201.

[0098] Fig.12 The second flowchart of a method for preparing a high-bandwidth memory provided in an embodiment of the present application, step S203 cuts the adjusted wafer stack structure to obtain the high-bandwidth memory, such as Fig.12 As shown, the preparation method of the present application also includes:

[0099] S301, determining location information of repairable storage units in repairable cutting units according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit.

[0100] S302, locating the repairable storage unit according to the position information of the repairable storage unit, bypassing the connection of the repairable storage unit, and correspondingly connecting to the redundant storage unit.

[0101] In the embodiment of the present application, before cutting and subsequently packaging the wafer stack structure to obtain high-bandwidth memory, the repairable cutting unit 201 is first repaired, and the 201 that is still invalid or unrepairable after the repair is shielded.

[0102] In one embodiment of the present application, before repairing the cutting unit 201, it is first necessary to confirm whether the cutting unit 201 is repairable. The detection information detected by the tester also includes the number of redundant storage units in the redundant area. According to the above description, the repair of the failed storage unit in the cutting unit 201 is mainly achieved by replacing the failed storage unit through line switching between the redundant storage unit and the failed storage unit. Then, whether the cutting unit is repairable mainly depends on whether the redundant storage units in the redundant area can meet the number of corresponding replacement failed storage units.

[0103] Therefore, first, step S301 compares the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit to confirm whether it is repairable. For the same cutting unit 201, if the number of redundant storage units is greater than or equal to the number of failed storage units, it can be indicated that the cutting unit 201 is repairable, and the failed storage units in the cutting unit 201 are considered to be repairable storage units, and the location information of the repairable storage units in the repairable cutting unit 201 is determined to facilitate addressing and repair in the subsequent repair process.

[0104] Then, step S302 is performed for each repairable cutting unit, the repairable storage unit is located according to the position information of the repairable storage unit, the connection of the repairable storage unit is bypassed, and the redundant storage unit is connected accordingly. The replaced redundant storage unit is also subject to electrical testing. After passing the electrical test, the repairable storage unit can be considered valid.

[0105] Fig.13 The third flowchart of a method for preparing a high-bandwidth memory provided in an embodiment of the present application is as follows: Fig.13 As shown, step S202 adjusts the connection state of the cutting unit in the wafer stacking structure according to the detection information, including:

[0106] S2021. Shield the cutting units indicated as defective in the detection information.

[0107] If the detection information indicates that a cutting unit 201 on a storage wafer 20 has failed the test and based on the comparison of the number of failed storage units and redundant storage units thereon, the redundant unit cannot repair all the failed storage units, then the cutting unit 201 is unrepairable, the position of the cutting unit 201 is indicated, and the cutting unit 201 is marked as a defective product.

[0108] For the cutting unit 201 indicated as a defective product, step S2021 is executed to shield the defective cutting unit. The address information of the shielded cutting unit 201 is recorded and marked. The shielded cutting unit 201 is no longer used to access data. When used as a high-bandwidth memory after cutting, the data transmission shields the storage chip 21 corresponding to the marked address.

[0109] It should be noted that in the embodiments of the present application, there is no specific limitation on the preparation equipment for executing the preparation method of high-bandwidth memory. In some cases, the preparation equipment also includes a plurality of devices that respectively execute different steps. In one embodiment, the preparation process steps of stacking and interconnecting the logic wafer 10 and the multi-layer storage wafer 20 are first performed in the stacking preparation equipment, and then the repairable cutting unit 201 is repaired in the repair equipment according to the detection information output by the tester, and the connection status of the cutting unit 201 indicated as a defective product is adjusted. Then, the cutting operation of the wafer stacking structure is performed by the cutting equipment to obtain the high-bandwidth memory.

[0110] In another embodiment, the method for preparing the high-bandwidth memory of the embodiment of the present application can also be applied to the preparation of other 3DIC products in a wafer to wafer stacking manner, such as the stacking of photosensitive devices in image sensors used in mobile phones or other small mobile terminals, or the stacking of other components.

[0111] In another aspect of the embodiment of the present application, a wafer stacking structure is provided. Please continue to refer to the above Figure 1, including a logic wafer 10 and a multi-layer storage wafer 20 stacked in sequence, the logic wafer 10 and the multi-layer storage wafer 20 are connected via a bus 30, and the logic wafer 10 includes a hierarchical address port. The wafer stacking structure of the embodiment of the present application includes a hierarchical address port on the logic wafer 10, which is used to connect to the address bus in the bus 30 to transmit the hierarchical address of the multi-layer storage wafer 10. In one embodiment, when the cutting unit 201 in a certain level of storage wafer 20 is indicated as defective according to the test results of the test machine, the level of the storage wafer 20 where the cutting unit 201 indicated as defective is located can be accurately addressed according to the level address through the level address port connected to the bus 30 on the logic wafer 10, and its two-dimensional address in the storage wafer 20 can be obtained, so that the cutting unit 201 indicated as defective can be marked in a shielding manner, and data is no longer accessed in the cutting unit 201, thereby making the wafer stacking structure containing the defective cutting unit 201 still usable after shielding, thereby improving the preparation yield of the high-bandwidth memory formed after cutting.

[0112] The bus 30 records the hierarchical address of each storage wafer 20 , and the hierarchical address port on the logic wafer 10 is used to transmit the hierarchical address of each storage wafer.

[0113] The hierarchical address of each storage wafer 20 is recorded in the bus 30, and the hierarchical address of the storage wafer 20 can be addressed according to the recorded hierarchical address. In one embodiment, a control center is included on the logic wafer 10, and an address decoding device is respectively provided on each layer of the storage wafer 20. The connection between the logic wafer 10 and the storage wafer 20 of each layer is realized by sending instructions through the control center of the logic wafer 10 and processing by the address decoding device of the corresponding layer, so as to determine the hierarchical address corresponding to the level. Among them, the hierarchical address of each storage wafer 20 is transmitted through the hierarchical address port on the logic wafer 10. Therefore, the wafer stacking structure of the embodiment of the present application can accurately address the storage wafer 20 of each layer and confirm the location of the storage wafer 20 corresponding to the data access.

[0114] In one embodiment, regarding the physical implementation of the bus 30 interconnection between the logic wafer 10 and the multi-layer storage wafer 20, the logic wafer 10 and the multi-layer storage wafer 20 can be interconnected through silicon vias or hybrid bonding.

[0115] Through silicon via (TSV), also known as through silicon via technology, is a technical solution for interconnecting chips between stacked wafers in three-dimensional integrated circuits. Through silicon via technology can effectively realize the stacking interconnection of 3D chips, and the chip level interconnection realized in this way can make the chip stacking density in the level direction higher, the interconnection line between chips shorter, the size smaller, and the connection reliability higher. Hybrid bonding technology (HB), as another technology to realize the level interconnection between three-dimensional stacked wafers, can realize the internal interconnection of thousands of chips while bonding two wafers, with high connection reliability and low cost. The wafer stacking structure of the embodiment of the present application adopts the wafer to wafer stacking method, and can realize the interconnection by through silicon via or hybrid bonding to realize the bus connection between the logic wafer 10 and the multi-layer storage wafer 20. Both through silicon via and hybrid bonding have good connection reliability and low process cost, and have good heat dissipation, and the structure of the prepared high-bandwidth memory is compact, which is conducive to the miniaturization of the device structure using the high-bandwidth memory.

[0116] According to another aspect of the embodiments of the present application, a high-bandwidth memory is provided. The high-bandwidth memory of the embodiments of the present application is obtained by cutting a wafer stack structure. Fig.11 A schematic diagram of the formation relationship of obtaining a high-bandwidth memory by cutting a wafer stack structure provided in an embodiment of the present application is shown in FIG. Fig.11 As shown in the schematic diagram on the right side of the middle arrow, it includes a logic chip 11 and a multi-layer memory chip 21 stacked in sequence, the logic chip 11 and the multi-layer memory chip 21 are connected via a bus 30, the bus 30 records the hierarchical address of each memory chip 21, and the logic chip 11 includes a hierarchical address port for transmitting the hierarchical address to the multi-layer memory chip 21 via the bus 30.

[0117] Fig.11 The location of bus 30 in the high bandwidth memory structure is not shown. In fact, Fig.11 As can be seen from the schematic diagram before cutting shown on the left side of the middle arrow, each high-bandwidth memory structure formed after cutting includes a logic chip 11 and a multi-layer memory chip 21, and a bus connecting the logic chip 11 and the multi-layer memory chip 21. The bus includes a control center portion arranged on the logic chip 11, an address decoding device respectively arranged on each layer of the memory chip 21, and also includes an electrical connection line respectively connecting the logic chip 11 and each layer of the memory chip 21. When marking address information and storing data, the control center in the logic chip 11 sends instructions and is decoded by the address decoding device on the memory chip 21 of the corresponding layer, so as to realize the determination and data access of the memory chip 21 of the corresponding layer.

[0118] In the high-bandwidth memory of the embodiment of the present application, in one implementation manner, the multi-layer memory chip 21 includes at least one layer of shielded memory chip 21 .

[0119] Fig.14 A schematic diagram of the structure of a high-bandwidth memory provided in an embodiment of the present application is shown in FIG. Fig.14 As shown, take stacking four layers of memory chips 21 on a logic chip 11 and shielding one layer of memory chips 21 as an example. Four layers of memory wafers 20 are stacked on a layer of logic wafer 10 in sequence and connected by bus. The bus records the hierarchical addresses of the four layers of memory wafers 20. The bus also records the two-dimensional address of each cutting unit 201 in each layer of memory wafer 20. After stacking, electrical testing is performed and the repairable cutting unit 201 on the memory wafer 20 is repaired. After the wafer stacking structure is cut, one of the high-bandwidth memory chips is formed as shown in FIG. Fig.14 As shown, in one embodiment, the high-bandwidth memory includes a logic chip 11 and four layers of memory chips 21 stacked sequentially on the logic chip 11, wherein the memory chip 21 of the third layer is marked as a defective product on the bus for shielding because it is a defective product and cannot be repaired, or still fails to pass the electrical test after repair. The hierarchical address of the memory chip 21 is recorded on the bus of the high-bandwidth memory of the embodiment of the present application. For the memory chip 21 of the third layer that is marked as a defective product and shielded, the data of the memory chip 21 of this layer can be accessed without performing address marking. In this way, in one embodiment, if the capacity of the memory chip 21 of each layer is 2Gbit, the high-bandwidth memory of good quality should have a memory capacity of 8Gbit. For the prior art, in the early preparation process, when any layer of the memory chip 21 is a defective product, the entire high-bandwidth memory can only be discarded as fail and unavailable. This method leads to a large waste of cost due to the low yield. The high-bandwidth memory provided by the embodiment of the present application can address and shield the memory chip 21 marked as a defective product through the hierarchical address recorded on the bus, as shown in FIG. Fig.14 As shown, when the memory chip 21 of the third layer is marked as defective, it can be addressed and shielded before the wafer stack structure is cut, so that in the high-bandwidth memory formed after cutting, data is not accessed in the memory unit 21 of the layer marked as defective, so that the high-bandwidth memory can achieve theoretical layer reduction (since the layer where the defective memory unit 21 is located is not actually reduced in terms of the actual physical structure, it is called theoretical layer reduction), with three layers of available memory chips 21 and a memory capacity of 6Gbit for normal use, thereby improving the preparation yield of the high-bandwidth memory and reducing the production cost of the high-bandwidth memory.

[0120] Similarly, in another embodiment, the high-bandwidth memory of the embodiment of the present application, when the number of memory chips 21 stacked on the logic chip 11 is another number of layers, and when there is more than one layer of memory chips 21 marked as inferior products, can be shielded in this manner and then used with reduced layers. The methods of testing, shielding, cutting, and use are the same as the principles of the above examples and will not be repeated here.

[0121] The embodiments of the present application provide a wafer stacking structure and a test method thereof, a high-bandwidth memory and a preparation method thereof. Through testing, and addressing, shielding or repairing of the cutting units in the wafer stacking structure after the test, the actual storage capacity of the high-bandwidth memory obtained after cutting is adjusted, and a variety of high-bandwidth memories with partial capacity reduced are provided, thereby improving the preparation efficiency and preparation yield of the high-bandwidth memory and reducing the production cost of the high-bandwidth memory.

[0122] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A method for testing a wafer stack structure, characterized in that: The method is applied to a tester, the tester is used to test a wafer stacking structure, the wafer stacking structure includes a logic wafer and a multi-layer storage wafer stacked in sequence, the logic wafer and the multi-layer storage wafer are connected via a bus, the logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the multi-layer storage wafer via the bus, the probe of the tester is used to connect with the logic wafer, and the method includes: Acquire a three-dimensional layer number address to be tested, where the three-dimensional layer number address is used to indicate a layer address corresponding to each layer of a storage wafer in a multi-layer storage wafer; According to the three-dimensional layer address, the probe reads the detection information of the storage wafer at the layer address corresponding to the three-dimensional layer address through the layer address port of the logic wafer via the bus, and the detection information is used to indicate the quality of the cutting unit in the storage wafer corresponding to the three-dimensional layer address.

2. The method for testing a wafer stack structure according to claim 1, characterized in that: After the probe reads the detection information of the storage wafer at the layer address corresponding to the three-dimensional layer address through the layer address port of the logic wafer via the bus according to the three-dimensional layer address, the method further includes: According to the detection information, repair indication information is output, where the repair indication information is used to indicate repairable position information in the cutting unit.

3. The method for testing a wafer stack structure according to claim 2, characterized in that: The detection information includes: an identification of a cutting unit, the number of failed storage units in a storage area of ​​each cutting unit, and location information of the failed storage units. The identification of the cutting unit is used to indicate a two-dimensional row address and a two-dimensional column address of the cutting unit.

4. The method for testing a wafer stack structure according to claim 3, characterized in that: The detection information also includes: the number of redundant storage units in each of the cutting units; The step of outputting repair instruction information according to the detection information comprises: Determining whether each cutting unit is repairable according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit; When the cutting unit is repairable, repair instruction information is output.

5. The method for testing a wafer stack structure according to claim 4, characterized in that: The output repair instruction information includes: When the cutting unit is repairable, determining position information of a repairable storage unit in the repairable cutting unit; Outputting the position information of the repairable storage unit in the repairable cutting unit.

6. The method for testing a wafer stack structure according to claim 4, characterized in that: After determining whether each cutting unit is repairable according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit, the method further includes: When the cutting unit is not repairable, the cutting unit is determined to be a defective product, and an identification of the defective product is output.

7. A method for preparing a high-bandwidth memory, characterized in that: The high-bandwidth memory is obtained by cutting a wafer stack structure, the wafer stack structure includes a logic wafer and a multi-layer storage wafer stacked in sequence, the logic wafer and the multi-layer storage wafer are connected through a bus, and the logic wafer includes a hierarchical address port for transmitting hierarchical addresses with the multi-layer storage wafer through the bus. The method includes: Acquire detection information output by the tester, the detection information being used to indicate the quality of the cutting unit in the storage wafer detected according to the three-dimensional layer number address and the corresponding layer address; Adjusting the connection state of the cutting unit in the wafer stacking structure according to the detection information, the connection state including the signal connection relationship between the cutting unit and other cutting units located at adjacent levels; The adjusted wafer stacking structure is cut to obtain the high-bandwidth memory, wherein the high-bandwidth memory includes: a cutting unit for the logic wafer and a cutting unit for each of the stacked storage wafers.

8. The method for preparing a high-bandwidth memory according to claim 7, characterized in that: The detection information includes: an identification of a cutting unit, the number of failed storage units in a storage area of ​​each cutting unit, and location information of the failed storage units. The identification of the cutting unit is used to indicate a two-dimensional row address and a two-dimensional column address of the cutting unit.

9. The method for preparing a high-bandwidth memory according to claim 8, characterized in that: The detection information also includes: the number of redundant storage units in each of the cutting units; Before cutting the adjusted wafer stack structure to obtain the high-bandwidth memory, the method further includes: Determine the location information of the repairable storage unit in the repairable cutting unit according to the number of failed storage units in the storage area of ​​each cutting unit and the number of redundant storage units in each cutting unit; The repairable storage unit is positioned according to the position information of the repairable storage unit, and the connection of the repairable storage unit is bypassed and connected to the redundant storage unit accordingly.

10. The method for preparing a high-bandwidth memory according to any one of claims 7 to 9, characterized in that: The step of adjusting the connection state of the cutting unit in the wafer stacking structure according to the detection information includes: The cutting units indicated as defective in the detection information are shielded.

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