Solid-state image pickup element and electronic device

Abstract

A solid-state imaging device includes a pair of first floating diffusion layers arranged in a vertical direction perpendicular to a predetermined direction, a pair of second floating diffusion layers arranged in the vertical direction and adjacent to the pair of first floating diffusion layers in the predetermined direction, a first connection circuit configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring, a second connection circuit configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring, and an output circuit configured to output an output signal corresponding to a charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers.

Description

Technical Field

[0001] This technology relates to solid-state camera elements. More specifically, this technology relates to solid-state camera elements and electronic devices for processing signals after pixel addition. Background Technology

[0002] In the past, in solid-state imaging devices, a pixel-adding technique for adding multiple pixel signals has been used to improve sensitivity and reduce noise. For example, a solid-state imaging device has been proposed in which a connecting transistor for connecting two adjacent floating diffusion layers (FDs) in the vertical direction is provided (see, for example, Patent Document 1).

[0003] [List of cited references]

[0004] [Patent Literature]

[0005] [Patent Document 1]: JP 2013-197989 A Summary of the Invention

[0006] [Technical problem to be solved]

[0007] In the aforementioned related technologies, a connecting transistor is provided between two adjacent FDs in the vertical direction, thereby adding the pixel signals of two pixels arranged in the vertical direction. However, the aforementioned solid-state camera elements have difficulty performing pixel addition on multiple pixels arranged in directions other than the vertical direction. For example, in a Bayer array, multiple green (G) pixels are arranged diagonally, but the aforementioned solid-state camera elements have difficulty adding the pixel signals of these pixels. Therefore, in the aforementioned solid-state camera elements, there is a problem that the arrangement direction of the pixel addition objects is limited to the vertical direction, resulting in a lack of flexibility.

[0008] This technology was created in view of the above situation, and it is expected to improve the flexibility of the arrangement orientation of the additive objects in solid-state imaging elements used to perform pixel addition technology.

[0009] [Technical solution to the problem]

[0010] According to a first aspect of the present invention, a solid-state imaging element is provided, comprising: a pair of first floating diffusion layers disposed in a vertical direction perpendicular to a predetermined direction; a pair of second floating diffusion layers disposed in the vertical direction and adjacent to the pair of first floating diffusion layers in the predetermined direction; a first connection circuit configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring; a second connection circuit configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring; and an output circuit configured to output an output signal corresponding to the charge amount of at least one of the pair of first and second floating diffusion layers. This results in an effect that improves the flexibility of pixel-addition objects.

[0011] Furthermore, in the first aspect, the first connection circuit may include: a first connection transistor configured to connect one of the pair of first floating diffusion layers to the first wiring according to a first control signal; and a second connection transistor configured to connect the other of the pair of first floating diffusion layers to the first wiring according to a second control signal. Moreover, the second connection circuit may include: a third connection transistor configured to connect one of the pair of second floating diffusion layers to the first wiring according to a third control signal; and a fourth connection transistor configured to connect the other of the pair of second floating diffusion layers to the first wiring according to a fourth control signal. This results in the effect that four floating diffusion layers can be connected to the first wiring respectively according to control signals.

[0012] Furthermore, in the first aspect, a reset transistor may be disposed between the first connecting transistor and the third connecting transistor in the predetermined direction, and a select transistor may be disposed between the first connecting transistor and the second connecting transistor in the vertical direction. This allows the connecting transistors to be connected to a first wiring installed in the vertical direction.

[0013] Furthermore, in the first aspect, the first connecting transistor and the third connecting transistor can be arranged adjacent to each other in the predetermined direction, and a selection transistor can be disposed between the first connecting transistor and the second connecting transistor in the vertical direction. This results in a reduction in the number of wiring connections.

[0014] Furthermore, in the first aspect, a reset transistor may be disposed between the first connecting transistor and the third connecting transistor in the predetermined direction, and the first connecting transistor and the second connecting transistor may be configured to be adjacent to each other in the vertical direction. This results in a reduction in wiring distance in the vertical direction.

[0015] Furthermore, in the first aspect, the first connecting transistor and the third connecting transistor can be configured to be adjacent to each other in the predetermined direction, and the first connecting transistor and the second connecting transistor can be configured to be adjacent to each other in the vertical direction. This results in a reduction in wiring distance in the horizontal direction.

[0016] Furthermore, in the first aspect, the second connection circuit may further include: a fifth connection transistor configured to connect one of the pair of second floating diffusion layers to a predetermined second wiring according to a fifth control signal; and a sixth connection transistor configured to connect the other of the pair of second floating diffusion layers to a predetermined third wiring according to a sixth control signal. This results in the ability to increase the number of pixels in the additive object.

[0017] Furthermore, in the first aspect, a reset transistor may be disposed adjacent to the fifth connecting transistor in the predetermined direction. This allows the connecting transistor to be connected to the first, second, and third wirings installed in the vertical direction.

[0018] Furthermore, in the first aspect, a predetermined number of the fifth connecting transistors can be arranged adjacent to each other in the predetermined direction. This results in a reduction in the number of wiring connections.

[0019] Furthermore, in the first aspect, the output circuit may further include: a first reset transistor configured to connect a predetermined power node to the first wiring according to a first reset signal; and a second reset transistor configured to connect a predetermined power node to the first wiring according to a second reset signal. This provides the effect of maintaining circuit symmetry when initializing the left and right sides.

[0020] Furthermore, in the first aspect, it may also include: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction and adjacent to the pair of third floating diffusion layers in the predetermined direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring. This results in the ability to increase the number of pixels in the additive object.

[0021] Furthermore, the first aspect may also include a signal processing unit configured to perform distance measurement processing corresponding to the time of flight of light based on the output signal. This results in the ability to measure the distance to an object.

[0022] Furthermore, in the first aspect, it may also include: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to a predetermined second wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the second wiring. Moreover, the output circuit can output an output signal corresponding to the charge amount of at least one of the pair of first and second floating diffusion layers and an output signal corresponding to the charge amount of at least one of the pair of third and fourth floating diffusion layers. This results in the ability to measure the distance to an object.

[0023] Furthermore, in the first aspect, it may also include: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring. Moreover, the output circuit can output an output signal corresponding to the charge amount of at least one of the pair of first and second floating diffusion layers and an output signal corresponding to the charge amount of at least one of the pair of third and fourth floating diffusion layers. This provides the effect of adding signals with different phase differences.

[0024] Furthermore, in the first aspect, it may also include: a first transfer transistor configured to transfer charge from a first photoelectric conversion element to one of the pair of first floating diffusion layers; a second transfer transistor configured to transfer charge from the first photoelectric conversion element to the other of the pair of first floating diffusion layers; a third transfer transistor configured to transfer charge from a second photoelectric conversion element to one of the pair of second floating diffusion layers; and a fourth transfer transistor configured to transfer charge from the second photoelectric conversion element to the other of the pair of second floating diffusion layers. This results in the ability to transmit signals with different phase differences to each floating diffusion layer arranged in the vertical direction.

[0025] Furthermore, in the first aspect, the first connection circuit may include: a first connection transistor configured to connect one of the pair of first floating diffusion layers to a second wiring connected to the first wiring according to a first control signal; a second connection transistor configured to connect the other of the pair of first floating diffusion layers to a third wiring according to a second control signal; and a third connection transistor configured to connect the first wiring to the third wiring according to a third control signal. Moreover, the second connection circuit may include: a fourth connection transistor configured to connect one of the pair of second floating diffusion layers to the second wiring according to a fourth control signal. This results in a variable FD sharing range.

[0026] Furthermore, according to a second aspect of the present technology, an electronic device is provided, comprising: a pair of first floating diffusion layers arranged in a vertical direction perpendicular to a predetermined direction; a pair of second floating diffusion layers arranged in the vertical direction and adjacent to the pair of first floating diffusion layers in the predetermined direction; a first connection circuit configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring; a second connection circuit configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring; an output circuit configured to output an output signal corresponding to the charge amount of at least one of the pair of first and second floating diffusion layers; and an analog-to-digital converter configured to perform analog-to-digital conversion processing on the output signal. This results in improved flexibility in pixel-adding objects and the ability to convert the added signal into a digital signal.

[0027] [Beneficial effects of the invention]

[0028] The row selection section can improve the flexibility of the arrangement direction of the objects to be added. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a construction example of a camera device according to a first embodiment of the present technology.

[0030] Figure 2 This is a diagram illustrating an example of the stacked structure of a solid-state camera element in a first embodiment of the present technology.

[0031] Figure 3 This is a block diagram illustrating a construction example of a solid-state camera element in a first embodiment of the present technology.

[0032] Figure 4 This is a diagram illustrating a construction example of the pixel array section in the first embodiment of the present technology.

[0033] Figure 5 This is a circuit diagram illustrating a construction example of the upper left FD shared block within a pixel block in the first embodiment of this technology.

[0034] Figure 6 This is a circuit diagram illustrating a construction example of the lower left FD shared block within a pixel block in the first embodiment of this technology.

[0035] Figure 7 This is a circuit diagram illustrating a construction example of the upper right FD shared block within a pixel block in the first embodiment of this technology.

[0036] Figure 8 This is a circuit diagram illustrating a construction example of the lower right FD shared block within a pixel block in the first embodiment of this technology.

[0037] Figure 9 This is a block diagram illustrating a construction example of the analog-to-digital converter in the first embodiment of the present technology.

[0038] Figure 10 This is a diagram illustrating an example of the control method in the normal mode and the conversion efficiency changing mode of the first embodiment of this technology.

[0039] Figure 11 This is a diagram illustrating an example of a control method in a pixel addition mode according to a first embodiment of the present technology.

[0040] Figure 12 This is a plan view illustrating an example layout of the elements and wiring of the pixel array section in the first embodiment of the present technology.

[0041] Figure 13 This is a plan view illustrating an example of a Bayer array in a first embodiment of the present technology.

[0042] Figure 14This is a plan view illustrating an example arrangement other than the Bayer array in the first embodiment of this technology.

[0043] Figure 15 This is a plan view illustrating an example arrangement of infrared (IR) pixels in a first embodiment of the present technology.

[0044] Figure 16 This is a circuit diagram illustrating a construction example of a pixel block in the first embodiment of the present technology.

[0045] Figure 17 This is a simplified circuit diagram of the pixel block in the first embodiment of this technology.

[0046] Figure 18 This is a diagram illustrating the readout method in the normal mode of the first embodiment of this technology.

[0047] Figure 19 This is a diagram illustrating the readout method in the pixel addition mode of 16 pixels in the first embodiment of this technology.

[0048] Figure 20 This is a plan view illustrating an example of the layout of elements and wiring in a pixel array section of a first variation of the first embodiment of the present technology.

[0049] Figure 21 This is a plan view illustrating an example of the layout of elements and wiring in a pixel array section of a second variation of the first embodiment of the present technology.

[0050] Figure 22 This is a plan view illustrating an example layout of elements and wiring in a pixel array section of a third variation of the first embodiment of the present technology.

[0051] Figure 23 This is a circuit diagram illustrating a construction example of the pixel array section in the second embodiment of the present technology.

[0052] Figure 24 This is a plan view illustrating an example layout of the elements and wiring in the pixel array section of the second embodiment of the present technology.

[0053] Figure 25 This is a plan view illustrating an example layout of elements and wiring in a pixel array section of a modified embodiment of the present technology.

[0054] Figure 26 This is a circuit diagram illustrating a construction example of the pixel array section in the third embodiment of the present technology.

[0055] Figure 27This is a circuit diagram illustrating a construction example of the pixel array section in the fourth embodiment of the present technology.

[0056] Figure 28 This is a block diagram illustrating a construction example of an electronic device according to a fifth embodiment of the present technology.

[0057] Figure 29 This is a circuit diagram illustrating a construction example of the left two pixels within a pixel block in the fifth embodiment of the present technology.

[0058] Figure 30 This is a circuit diagram illustrating a construction example of the two rightmost pixels within a pixel block in the fifth embodiment of the present technology.

[0059] Figure 31 This is a timing diagram illustrating an example of the operation of an electronic device according to a fifth embodiment of the present technology.

[0060] Figure 32 This is a circuit diagram illustrating a construction example of the left two pixels within a pixel block in a first variation of the fifth embodiment of the present technology.

[0061] Figure 33 This is a circuit diagram illustrating a construction example of a pixel block in a second variation of the fifth embodiment of the present technology.

[0062] Figure 34 This is a circuit diagram illustrating a construction example of the upper FD common block in the sixth embodiment of this technology.

[0063] Figure 35 This is a circuit diagram illustrating a construction example of the lower FD common block in the sixth embodiment of this technology.

[0064] Figure 36 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0065] Figure 37 This is an explanatory diagram showing an example of the installation location of the camera unit. Detailed Implementation

[0066] The following will describe the modes used to implement this technology (hereinafter referred to as implementation schemes). They will be described in the following order.

[0067] 1. First Implementation Scheme (Example of connecting multiple FDs to FD wiring)

[0068] 2. Second Implementation Scheme (Example of adding FD wiring and connecting multiple FDs to the FD wiring)

[0069] 3. Third implementation scheme (example of connecting the reset transistor and multiple FDs to the FD wiring)

[0070] 4. Fourth Implementation Scheme (Example of connecting 8 FDs to FD wiring)

[0071] 5. Fifth Implementation Scheme (Example of connecting multiple FDs to FD wiring and performing distance measurement)

[0072] 6. Sixth Implementation Scheme (Example of connecting multiple FDs to FD wiring and making the shared range of FDs variable)

[0073] 7. Examples of applications of moving bodies

[0074] <1. First Implementation Plan>

[0075] [Example of camera device construction]

[0076] Figure 1 This is a block diagram illustrating a construction example of a camera device 100 according to a first embodiment of the present invention. The camera device 100 is a means for capturing image data (frames) and includes an optical unit 110, a solid-state imaging element 200, and a digital signal processing (DSP) circuit 120. Furthermore, the camera device 100 also includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As a camera device 100, for example, it is assumed that in addition to a digital camera such as a digital camera, it could also be a smartphone, personal computer, vehicle camera, etc., with video recording capabilities. Note that the camera device 100 is an example of an electronic device described in the claims.

[0077] The optical unit 110 focuses light from an object and guides the focused light to the solid-state imaging element 200. The solid-state imaging element 200 generates frames through photoelectric conversion synchronized with a vertical synchronization signal. Here, the vertical synchronization signal is a periodic signal with a predetermined frequency used to represent the timing of image capture. The solid-state imaging element 200 provides the generated image data to the DSP circuit 120 via signal line 209.

[0078] The DSP circuit 120 performs predetermined signal processing on the frames from the solid-state imaging element 200. The DSP circuit 120 outputs the processed frames to the frame memory 160, etc., via the bus 150.

[0079] The display unit 130 is used to display frames. The display unit 130 may, for example, be a liquid crystal panel or an organic electroluminescence (EL) panel. The operation unit 140 generates operation signals based on user operations.

[0080] Bus 150 is a common path for the optical unit 110, solid-state imaging element 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170 and power supply unit 180, and is used to exchange data with each other.

[0081] The frame memory 160 is used to store image data. The storage unit 170 stores various data such as frames. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, etc.

[0082] [Example of solid-state camera element construction]

[0083] Figure 2 This diagram illustrates an example of the stacked structure of a solid-state imaging element 200 according to a first embodiment of the present invention. The solid-state imaging element 200 includes a circuit chip 202 and pixel chips 201 stacked on the circuit chip 202. These chips are electrically connected to each other via connections such as VIAs (Vertical Interconnect Access). Note that in addition to VIAs, these chips can also be connected via Cu-Cu bonding or bumps. These chips can also be connected by other methods (such as magnetic bonding). Furthermore, although two chips are shown stacked here, three or more layers can also be stacked.

[0084] Figure 3 This is a block diagram illustrating a construction example of a solid-state imaging element 200 according to a first embodiment of the present invention. The solid-state imaging element 200 includes a row selection unit 210, a digital-to-analog converter (DAC) 220, and a timing control circuit 230. Furthermore, the solid-state imaging element 200 also includes a pixel array unit 300, an analog-to-digital converter 240, a horizontal transmission scanning unit 250, and a signal processing unit 260. Moreover, a plurality of pixels are arranged in a two-dimensional grid pattern in the pixel array unit 300.

[0085] The timing control circuit 230 controls the operation timing of the line selection unit 210, DAC 220, analog-to-digital converter 240 and horizontal transmission scanning unit 250 in sync with the vertical synchronization signal Vsync.

[0086] The row selection unit 210 selects and drives each row sequentially, and outputs the analog pixel signal to the analog-to-digital converter 240.

[0087] DAC 220 generates a reference signal through digital-to-analog (DA) conversion and provides the reference signal to analog-to-digital converter 240. For example, a sawtooth ramp signal can be used as the reference signal.

[0088] The analog-to-digital converter 240 converts the analog pixel signals of each column into digital signals using a reference signal. Under the control of the horizontal transmission scanning unit 250, the analog-to-digital converter 240 provides the digital signals to the signal processing unit 260.

[0089] The horizontal transmission scanning unit 250 controls the analog-to-digital converter 240 to output digital signals sequentially.

[0090] The signal processing unit 260 performs predetermined image processing on the frame containing the aforementioned digital signals. The signal processing unit 260 then provides the processed frame to the DSP circuit 120.

[0091] Furthermore, the aforementioned circuits in the solid-state imaging element 200 are distributed across the pixel chip 201 and the circuit chip 202. For example, the pixel array section 300 is disposed in the pixel chip 201, and other circuits besides the pixel array section 300 (such as the analog-to-digital converter 240) are disposed in the circuit chip 202. Note that the circuits disposed in the pixel chip 201 and the circuits disposed in the circuit chip 202 are not limited to the above-described combination. For example, the pixel array section 300 may be disposed in the pixel chip 201 together with the comparator in the analog-to-digital converter 240, and other circuits may be disposed in the circuit chip 202.

[0092] [Example of pixel array construction]

[0093] Figure 4 This diagram illustrates a structural example of the pixel array section 300 according to the first embodiment of the present invention. In the pixel array section 300, a plurality of pixel blocks 310 are arranged in a two-dimensional grid pattern. In each pixel block 310, a plurality of shared FD blocks are arranged in a two-dimensional grid pattern. For example, shared FD blocks 320, 330, 340 and 350 are arranged in each pixel block 310.

[0094] In FD shared block 320, multiple pixels 311 sharing one FD are arranged in a two-dimensional grid. For example, eight pixels are arranged in four rows and two columns in FD shared block 320. Similarly, eight pixels are arranged in FD shared blocks 330, 340 and 350.

[0095] Note that the number of pixels arranged in the shared blocks of each FD is not limited to eight pixels; it can also be two pixels or other numbers.

[0096] [Example of pixel block construction]

[0097] Figure 5 This is a circuit diagram illustrating a construction example of the upper left FD common block 320 in pixel block 310 of the first embodiment of the present technology.

[0098] Here, in the pixel array section 300, vertical signal lines are installed vertically for each column of the FD common block, and each column is connected to a corresponding vertical signal line. For example, the columns of the left FD common block, including FD common blocks 320 and 330, are connected to vertical signal line 309-1. Furthermore, the columns of the right FD common block, including FD common blocks 340 and 350, are connected to vertical signal line 309-2. Additionally, FD wiring 308 is installed in the pixel block 310, and FD common blocks 320, 330, 340, and 350 are connected to FD wiring 308.

[0099] Now focus on the top left common block 320 (FD). FD common block 320 includes connection transistor 401, reset transistor 402, transfer transistors 403 to 410, photoelectric conversion elements 411 to 418, and FD 321. Additionally, FD common block 320 also includes amplification transistor 419 and selection transistor 420.

[0100] The connection transistor 401 connects FD321 to FD wiring 308 according to the control signal FDG_b0 from the line selection unit 210.

[0101] The reset transistor 402 connects the power supply node to FD321 and initializes the charge of FD321 according to the reset signal RST_b0 from the row selection unit 210.

[0102] Transmission transistor 403 transfers charge from photoelectric conversion element 411 to FD 321 according to the transmission signal TRG_(0,0) from the row selection unit 210. Transmission transistor 404 transfers charge from photoelectric conversion element 412 to FD 321 according to the transmission signal TRG_(0,1) from the row selection unit 210. Transmission transistor 405 transfers charge from photoelectric conversion element 413 to FD 321 according to the transmission signal TRG_(1,0) from the row selection unit 210. Transmission transistor 406 transfers charge from photoelectric conversion element 414 to FD 321 according to the transmission signal TRG_(1,1) from the row selection unit 210.

[0103] Transmission transistor 407 transfers charge from photoelectric conversion element 415 to FD 321 according to the transmission signal TRG_(2,0) from line selection unit 210. Transmission transistor 408 transfers charge from photoelectric conversion element 416 to FD 321 according to the transmission signal TRG_(2,1) from line selection unit 210. Transmission transistor 409 transfers charge from photoelectric conversion element 417 to FD 321 according to the transmission signal TRG_(3,0) from line selection unit 210. Transmission transistor 410 transfers charge from photoelectric conversion element 418 to FD 321 according to the transmission signal TRG_(3,1) from line selection unit 210.

[0104] Photoelectric conversion elements 411 to 418 generate charge through photoelectric conversion. FD 321 accumulates the transmitted charge and generates a voltage based on the amount of charge. Amplifying transistor 419 amplifies the voltage signal from FD 321. Selecting transistor 420 outputs the amplified analog signal to analog-to-digital converter 240 via vertical signal line 309-1 based on the selection signal SEL_b0 from the self-selection unit 210.

[0105] The transmission transistors 403 to 410, the photoelectric conversion elements 411 to 418, and the shared transistors (such as the reset transistor 401) work together. Figure 4 The function of pixel 311 is shown.

[0106] Figure 6 This is a circuit diagram illustrating a construction example of the lower left FD common block 330 in pixel block 310 of the first embodiment of the present technology.

[0107] The FD common block 330 includes a connection transistor 421, a reset transistor 422, transmission transistors 423 to 430, photoelectric conversion elements 431 to 438, and an FD 331. Furthermore, the FD common block 330 also includes an amplification transistor 439 and a selection transistor 440.

[0108] The connection structure of each element in the FD common block 330 is similar to the connection structure in the FD common block 320. In addition, the row selection unit 210 provides the FD common block 330 with the control signal FDG_b1, the reset signal RST_b1, the transmission signal for eight pixels such as the transmission signal TRG_(4,0), and the selection signal SEL_b1.

[0109] Figure 7 This is a circuit diagram illustrating a construction example of the upper right FD common block 340 in pixel block 310 of the first embodiment of the present technology.

[0110] The FD common block 340 includes a connection transistor 441, a reset transistor 442, transmission transistors 443 to 450, photoelectric conversion elements 451 to 458, and an FD 341. Furthermore, the FD common block 340 also includes an amplification transistor 459 and a selection transistor 460.

[0111] The connection structure of each element in the FD common block 340 is similar to the connection structure in the FD common block 320. In addition, the row selection unit 210 provides the FD common block 340 with the control signal FDG_b2, the reset signal RST_b2, the transmission signal for eight pixels such as TRG_(0,2), and the selection signal SEL_b2.

[0112] Figure 8 This is a circuit diagram illustrating a construction example of the lower right FD common block 350 in pixel block 310 of the first embodiment of the present technology.

[0113] The FD common block 350 includes a connection transistor 461, a reset transistor 462, transmission transistors 463 to 470, photoelectric conversion elements 471 to 478, and an FD 351. Furthermore, the FD common block 350 also includes an amplification transistor 479 and a selection transistor 480.

[0114] The connection structure of each element in the FD common block 350 is similar to the connection structure in the FD common block 320. In addition, the row selection unit 210 provides the FD common block 350 with the control signal FDG_b3, the reset signal RST_b3, the transmission signal for eight pixels such as the transmission signal TRG_(4,2), and the selection signal SEL_b3.

[0115] like Figures 5 to 8 As shown, the row selection unit 210 can individually control the connection transistors 401, 421, 441, and 461 to individually connect FDs 321, 331, 341, and 351 to FD wiring 308. Therefore, the row selection unit 210 can connect two FDs arranged in the horizontal or vertical direction, and it can also connect two FDs arranged diagonally. Therefore, the row selection unit 210 can perform pixel addition on two pixels arranged in the horizontal or vertical direction, and it can also perform pixel addition on two pixels arranged diagonally. Therefore, the row selection unit 210 can improve the flexibility of the arrangement direction of the addition objects.

[0116] [Example of Analog-to-Digital Converter Construction]

[0117] Figure 9This is a block diagram illustrating a construction example of the analog-to-digital converter 240 in the first embodiment of the present invention. In the analog-to-digital converter 240, an analog-to-digital converter (ADC) 241 and a latch circuit 244 are arranged for each vertical signal line.

[0118] The ADC 241 converts analog pixel signals into digital signals. The ADC 241 includes a comparator 242 and a counter 243. This type of ADC 241 is called a single-slope ADC.

[0119] Comparator 242 compares the reference signal from DAC 220 with the corresponding pixel signal from the vertical signal line. Comparator 242 provides the comparison result to counter 243.

[0120] In response to the control of the timing control circuit 230, the counter 243 counts the count value until the comparison result is inverted. The counter 243 outputs a signal representing the count value as a digital signal to the latch circuit 244.

[0121] The latch circuit 244 holds the digital signal. The latch circuit 244 outputs the digital signal to the signal processing unit 260 in sync with the synchronization signal from the horizontal transmission scanning unit 250.

[0122] Note that ADCs other than single-slope ADCs can be used. For example, successive approximation register analog-to-digital converters (SARADCs), delta-sigma ADCs, pipelined ADCs, or dual-slope ADCs can be used.

[0123] [Operational Example of a Solid-State Camera Component]

[0124] Figure 10 This diagram illustrates an example of the control method in the normal mode and the conversion efficiency change mode of the first embodiment of this technology. Here, the mode of the solid-state imaging element 200 is set to one of several modes, including the normal mode, the conversion efficiency change mode, and the pixel addition mode. The normal mode is a mode in which the pixel array unit 300 outputs pixel signals to the analog-to-digital converter unit 240 without performing pixel addition or conversion efficiency change. Figure 10 The following assumptions are made when focusing on FD 321 corresponding to the control signal FDG_b0 and when the conversion efficiency of FD 321 is changed.

[0125] The conversion efficiency changing mode is as follows: The pixel array unit 300 generates a pixel signal by changing the conversion efficiency used to convert charge into voltage without performing pixel addition, and outputs the pixel signal to the analog-to-digital converter 240. Furthermore, the pixel addition mode is as follows: The pixel array unit 300 adds multiple pixel signals without changing the conversion efficiency, and outputs the addition result to the analog-to-digital converter 240.

[0126] In normal mode, the row selection unit 210 uses control signals FDG_b0, FDG_b1, FDG_b2 and FDG_b3 to turn off all connected transistors 401, 421, 441 and 461.

[0127] Furthermore, the row selection unit 210 selects a row of the FD shared blocks, selects one pixel within each FD shared block in that row, and sets the selected pixel as the readout target. Assuming the readout target is the pixel in the nth row and mth column (m and n are integers), the row selection unit 210 provides a transmission signal TRG_(m,n) to that pixel. Additionally, the row selection unit 210 provides a reset signal or a selection signal to the FD shared blocks that include the pixel as the readout target. The analog-to-digital conversion unit 240 performs analog-to-digital (AD) conversion on the pixel signal for each column of the FD shared blocks. The row selection unit 210 sequentially selects each pixel in the FD shared blocks and sequentially selects each row of the FD shared blocks, thereby outputting each image signal in the pixel array unit 300.

[0128] On the other hand, in the conversion efficiency changing mode, the conversion efficiency is set to one of C1 to C4. When the conversion efficiency is set to C1, the line selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on only the connection transistor 401. When the conversion efficiency is set to C2, the line selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on only the connection transistors 401 and 421. Furthermore, when the conversion efficiency is set to C3, the line selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on the connection transistors 401, 421, and 441 and turns off the remaining connection transistor 461. When the conversion efficiency is set to C4, the line selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on all the connection transistors 401 and 421, 441, and 461.

[0129] In the conversion efficiency change mode, the transmission signal, reset signal, and selection signal to be provided are similar to those in the normal mode.

[0130] As described above, by turning on or off the connecting transistors 401, 421, 441, and 461, any number of FDs 321, 331, 341, and 351 can be connected to the FD wiring 308. Depending on the number of connections, the total capacitance of the FD or FD wiring used for charge accumulation will change. Therefore, as... Figure 10 As shown, the conversion efficiency of converting charge to voltage can be changed by controlling the number of connection transistors 401, 421, 441, and 461 to be turned on. Note that the conversion efficiency of each FD can also be controlled when focusing on FDs 331, 341, and 351 corresponding to control signals FDG_b1, FDG_b2, and FDG_b3. For example, when focusing on FD331, only connection transistor 421 associated with control signal FDG_b1 needs to be turned on and the conversion efficiency set to C1. When focusing on FD341, only connection transistor 441 associated with control signal FDG_b2 needs to be turned on and the conversion efficiency set to C1, or only two connection transistors, including connection transistor 441, need to be turned on and the conversion efficiency set to C2. When focusing on FD351, only connection transistor 461 associated with control signal FDG_b3 needs to be turned on and the conversion efficiency set to C1. In addition, in this case, it is possible to turn on only two connection transistors, including connection transistor 461, and set the conversion efficiency to C2, or it is possible to turn on only three connection transistors, including connection transistor 441, and set the conversion efficiency to C3.

[0131] Figure 11 This diagram illustrates an example of a control method in a pixel addition mode according to a first embodiment of the present invention. In the pixel addition mode, the number of pixels that can be added in pixel block 310 is set to any one of 8 pixels, 16 pixels, 24 pixels, and 32 pixels.

[0132] When the pixel count is set to 8 pixels, the row selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn off all connection transistors 401, 421, 441, and 461. Furthermore, the row selection unit 210 provides the transmission signal TRG to all pixels in the FD common block 320. Figure 11 In the diagram, FD shared block #0 represents FD shared block 320.

[0133] When the pixel count is set to 16 pixels, the row selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on only connection transistors 401 and 421. Furthermore, the row selection unit 210 provides the transmission signal TRG to all pixels in the FD common blocks 320 and 330. Figure 11In the diagram, FD shared block #1 represents FD shared block 330.

[0134] When the pixel count is set to 24 pixels, the row selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on connection transistors 401, 421, and 441 and turn off the remaining connection transistor 461. Furthermore, the row selection unit 210 provides the transmission signal TRG to all pixels in the FD common blocks 320, 330, and 340. Figure 11 In the text, FD shared block #2 represents FD shared block 340.

[0135] With the pixel count set to 32 pixels, the row selection unit 210 uses control signals FDG_b0 to FDG_b3 to turn on all connection transistors 401, 421, 441, and 461. Furthermore, the row selection unit 210 provides the transmission signal TRG to all pixels in the FD common blocks 320, 330, 340, and 350. Figure 11 In the text, FD shared block #3 represents FD shared block 350.

[0136] As described above, by turning on or off connecting transistors 401, 421, 441, and 461, any two or more of FDs 321, 331, 341, and 351 can be connected via FD wiring 308. Therefore, as Figure 11 As shown, by controlling the number of connection transistors 401, 421, 441 and 461 to be turned on, the number of pixels that are to be added can be changed.

[0137] Note that although the number of pixels being added was switched in units of 8 pixels, it is also possible to switch in units of 1 pixel by changing the number of pixels to be provided with the transmission signal.

[0138] Figure 12 This is a plan view showing an example of the layout of the elements and wiring of the pixel array section 300 in the first embodiment of the present technology. Figure 12 This is a plan view when viewed from the optical axis. In the FD common block 320, photoelectric conversion elements 411 to 418 are arranged in four rows and two columns.

[0139] Transmission transistors 403 to 406 are arranged around the central nodes of photoelectric conversion elements 411 to 414. Transmission transistors 407 to 410 are arranged around the central nodes of photoelectric conversion elements 415 to 418. Both nodes are connected to FD321.

[0140] Furthermore, amplifying transistor 419 and selecting transistor 420 are arranged horizontally and located between photoelectric conversion elements 411 to 414 and photoelectric conversion elements 415 to 418. Figure 12 In the diagram, "AMP" represents amplifying transistor 419, and "SEL" represents selecting transistor 420.

[0141] Reset transistor 402 and connection transistor 401 are arranged horizontally and between photoelectric conversion elements 415 to 418 and the FD shared block 330. Reset transistor 402 is arranged on the left side, and connection transistor 401 is arranged on the right side. Figure 12 In the diagram, "RST" represents reset transistor 402, and "FDG" represents connection transistor 401.

[0142] Furthermore, power line 307 is mounted on the left side of FD common block 320, and vertical signal line 309-1 is mounted on the right side of FD common block 320. The layouts of FD common blocks 330, 340, and 350 are similar to that of FD common block 320. Additionally, the connection transistors of each FD common block are connected via FD wiring 308. Since FD wiring 308 affects pixel characteristics, it may need to be shielded in some cases.

[0143] like Figure 12 As shown, in the horizontal direction, the reset transistor (RST) is arranged between the connection transistors (FDG) of FD common block 320 and FD common block 340. Furthermore, in the vertical direction, the select transistor (SEL) is arranged between the connection transistors (FDG) of FD common block 320 and FD common block 330.

[0144] Figure 13 This is a plan view illustrating an example of the Bayer array in a first embodiment of the present technology. Green filters are disposed above photoelectric conversion elements 411, 414, 415, and 418. Figure 13 The "G (green)" indicates a green filter. Blue filters are applied to photoelectric conversion elements 412 and 416. Figure 13 The "B (blue)" indicates the blue filter. The red filter is set on the photoelectric conversion elements 413 and 417. Figure 13 In this context, "R (red)" indicates the red filter. The arrangement of color filters in other FD common blocks, except for FD common block 320, is similar to that in FD common block 320. Figure 13 The arrangement of the color filters shown constitutes a Bayer array. Note that the colors of the color filters are not limited to R, G, and B, and can be complementary colors.

[0145] Even in such Figure 13 The Bayer array shown may also require flexible operations such as oblique addition. For example, in structures where the conversion factor (FD) is not shared, there are strong constraints on pixel addition when improving conversion efficiency or when the pixel size is large. However, Figures 5 to 8 The circuit shown enables flexible pixel addition.

[0146] In addition, other arrangements besides the Bayer array can be used. For example, such as Figure 14 As shown, 2 rows × 2 columns of G pixel blocks can also be arranged diagonally, and 2 rows × 2 columns of B pixel blocks and 2 rows × 2 columns of R pixel blocks can be arranged in other areas. Furthermore, as... Figure 15 As shown, IR pixels equipped with near-infrared light filters can be further arranged. For example... Figure 15 As shown, since IR pixels are sometimes arranged diagonally, they have the advantage of being able to perform pixel addition, especially in the diagonal direction.

[0147] Figure 16 This is a circuit diagram illustrating a construction example of pixel block 310 in a first embodiment of the present invention. When focusing on FD, FD 321 and FD 331 are arranged in the vertical direction. Furthermore, FD 341 and FD 351 are arranged in the vertical direction and located adjacent to FD 321 and FD 331 in the horizontal direction. Note that FD 321 and FD 331 are an example of a pair of first floating diffusion layers as described in the claims, and FD 341 and FD 351 are an example of a pair of second floating diffusion layers as described in the claims.

[0148] Furthermore, connection transistor 401 connects FD 321 to FD wiring 308 according to control signal FDG_b0. Connection transistor 421 connects FD 331 to FD wiring 308 according to control signal FDG_b1. Connection transistor 441 connects FD 341 to FD wiring 308 according to control signal FDG_b2. Connection transistor 461 connects FD 351 to FD wiring 308 according to control signal FDG_b3.

[0149] Note that connection transistor 401 is an example of the first connection transistor described in the claim, and connection transistor 421 is an example of the second connection transistor described in the claim. Additionally, connection transistor 441 is an example of the third connection transistor described in the claim, and connection transistor 461 is an example of the fourth connection transistor described in the claim.

[0150] Note that, as mentioned earlier, the number of pixels in the shared block of each FD is not limited to 8 pixels; it can also be 2 pixels, etc. Furthermore, each of FDs 321, FD 331, FD 341, and FD 351 is shared by multiple pixels, but a structure in which FDs are not shared can also be used. In this case, only one set of photoelectric conversion elements and transmission transistors is provided for each of FDs 321, FD 331, FD 341, and FD 351. Moreover, when FDs are not shared, the number of pixels in pixel block 310 is 4 pixels in a 2x2 grid.

[0151] Figure 17 This is a simplified circuit diagram of pixel block 310 in the first embodiment of this technology. Connection circuit 490, including connection transistors 401 and 421, selects at least one of FD 321 and FD 331 according to control signals FDG_b0 and FDG_b1 and connects the selected FD to FD wiring 308.

[0152] Connection circuit 491, including connecting transistors 441 and 461, selects at least one of FD 341 and FD 351 according to control signals FDG_b2 and FDG_b3 and connects the selected FD to FD wiring 308. Furthermore, output circuit 492, including amplifying transistors 419, 439, 459, and 479 and selecting transistors 420, 440, 460, and 480, outputs an output signal corresponding to the charge amount of at least one of FDs 321, 331, 341, and 351.

[0153] Figure 18 This diagram illustrates the readout method in the normal mode of the first embodiment of this technology. In the normal mode, the row selection unit 210 shuts down all connection transistors (FDGs) in the respective FD common blocks 320, 330, 340, and 350.

[0154] Furthermore, the row selection unit 210 selects a row of FD shared blocks, and selects one pixel (such as the top-left pixel) within each FD shared block in that row, and sets the selected pixel as the readout target. The row selection unit 210 provides a transmission signal TRG to that pixel. Through this operation, the pixel signal is output from the vertical signal line 309-1 or 309-2.

[0155] Figure 19 This is a diagram illustrating the readout method in the pixel addition mode of 16 pixels in the first embodiment of this technology.

[0156] For example, the row selection unit 210 only turns on the connection transistors (FDG) in the upper left FD shared block 320 and the lower right FD shared block 350. Furthermore, the row selection unit 210 provides the transmission signal TRG to all pixels in the FD shared blocks 320 and 350. Through this operation, for example, a summed signal of 16 pixels is output from the vertical signal line 309-2. Pixel summation improves readout speed and shortens the vertical blanking period. At this time, the selection transistor of the FD shared block 350 is turned on. Additionally, the FD shared block 360 (see [link to FD shared block 360]) that does not share an FD with adjacent FD shared blocks 320 to 350 can be selected. Figure 23 The selection transistor is turned on. In this case, the signal of the FD common block 360 can be read from the vertical signal line 309-1 simultaneously. This operation allows unused vertical signal lines to be utilized and improves readout speed.

[0157] Thus, according to the first embodiment of this technology, since the four FD transistors connect the corresponding four FDs to the FD wiring 308 respectively, in addition to pixels arranged in the horizontal and vertical directions being set as add-in objects, two pixels arranged in the diagonal direction can also be set as add-in objects. Therefore, the row selection unit 210 can improve the flexibility of the arrangement direction of add-in objects.

[0158] <First Variation>

[0159] In the first embodiment described above, the reset transistor is arranged between two connecting transistors in a horizontal direction. In this layout, FD wiring 308 needs to be installed for each column of the FD common block. The solid-state camera element 200 in the first variation of the first embodiment differs from the solid-state camera element 200 of the first embodiment in that the horizontal arrangement of the transistors is changed and the number of wirings is reduced.

[0160] Figure 20This is a plan view illustrating an example layout of the components and wiring of the pixel array section 300 in a first variation of the first embodiment of the present invention. The layout of the first variation of the first embodiment differs from that of the first embodiment in that the columns of the right-side block in the first embodiment are flipped horizontally. In the pixel array section 300 obtained after this horizontal flipping, two connecting transistors (FDGs) are arranged adjacent to each other in the horizontal direction. With this structure, in the vertical direction, two columns of the FD common block can share a single FD wiring 308 mounted between these two columns. Therefore, the number of wirings in the vertical direction can be less than in the first embodiment, where FD wiring 308 is mounted for each column. Thus, by reducing the number of wirings, the shielding area can be reduced and the conversion efficiency can be improved. Note that since high conversion efficiency is not always required, an optimal value can be set during the design phase.

[0161] Thus, in a first variation of the first embodiment of this technology, since the two connecting transistors are arranged adjacent to each other in the horizontal direction, the two columns can share a single FD wiring 308. This structure reduces the number of wirings in the vertical direction.

[0162] <Second Variation>

[0163] In the first embodiment described above, the selection transistor is arranged between two connecting transistors in the vertical direction. This arrangement makes it difficult to reduce the wiring distance of the FD wiring 308. The solid-state imaging element 200 in the second variation of the first embodiment differs from the solid-state imaging element 200 of the first embodiment in that the arrangement of the transistors in the vertical direction is changed, and the wiring distance is reduced.

[0164] Figure 21 This is a plan view illustrating an example layout of elements and wiring in a pixel array section 300 according to a second variation of the first embodiment of the present invention. The layout of the second variation of the first embodiment differs from that of the first embodiment in that the rows of the lower blocks in the first embodiment are flipped vertically. In the pixel array section 300 obtained after this vertical flipping, two connection transistors (FDGs) are arranged adjacent to each other in the vertical direction. This structure reduces the vertical wiring distance of the FD wiring 308.

[0165] Thus, in the second variation of the first embodiment of this technology, since the two connecting transistors are arranged adjacent to each other in the vertical direction, the wiring distance of the FD wiring 308 in the vertical direction can be reduced.

[0166] <Third Variation>

[0167] In the second variation of the first embodiment described above, the reset transistor is arranged between two connecting transistors in the horizontal direction. This arrangement makes it difficult to reduce the wiring distance of the FD wiring 308. The solid-state imaging element 200 in the third variation of the first embodiment differs from the solid-state imaging element 200 in the second variation of the first embodiment in that the arrangement of the transistors in the horizontal direction is changed, and the wiring distance is reduced.

[0168] Figure 22 This is a plan view illustrating an example layout of the elements and wiring in the pixel array section 300 of the third variation of the first embodiment of the present invention. The layout of the third variation of the first embodiment differs from that of the second variation of the first embodiment in that the columns of the right-hand blocks in the second variation of the first embodiment are flipped horizontally. In the pixel array section 300 obtained after this horizontal flipping, two connecting transistors (FDGs) are arranged adjacent to each other in the horizontal direction. This structure further reduces the horizontal wiring distance of the FD wiring 308.

[0169] Thus, in the third variation of the first embodiment of this technology, since the two connecting transistors are arranged adjacent to each other in the horizontal direction, the wiring distance of FD wiring 308 in the horizontal direction can be reduced.

[0170] <2. Second Implementation Plan>

[0171] In the first embodiment described above, pixel addition is performed on a maximum of 32 pixels. However, in some cases, more pixels may need to be added. The solid-state camera element 200 of the second embodiment differs from that of the solid-state camera element 200 of the first embodiment in that the number of pixels that can be added is increased by adding a connecting transistor.

[0172] Figure 23 This is a circuit diagram illustrating a construction example of the pixel array section 300 in the second embodiment of the present technology. It is assumed that FD common blocks 360, 370, 380 and 390 are arranged below FD common blocks 320, 330, 340 and 350.

[0173] The structure of the left-side FD common blocks 320 and 330 in the second embodiment is similar to that in the first embodiment. However, the right-side FD common blocks 340 and 350 in the second embodiment differ from those in the first embodiment in that connection transistors 494 and 495 are used instead of reset transistors 442 and 462.

[0174] In addition, FD common block 340 and the FD common block above FD common block 340 (not shown) are connected to FD wiring 308-1. FD common blocks 320, 330, 340, and 350 are connected to FD wiring 308-2. FD common blocks 350 and FD common block 370 are connected to FD wiring 308-3. FD common blocks 360, 370, 380, and 390 are connected to FD wiring 308-4. FD common block 390 and the FD common block below FD common block 390 (not shown) are connected to FD wiring 308-5.

[0175] Connection transistor 494 connects FD 341 to FD wiring 308-1 according to the control signal FDG_b2v from the row selection unit 210. Furthermore, control signal FDG_b2h is provided to connection transistor 441 in the second embodiment. Note that connection transistor 494 is an example of the fifth connection transistor described in the claims.

[0176] Connection transistor 495 connects FD351 to FD wiring 308-3 according to the control signal FDG_b3v from the row selection unit 210. Furthermore, the control signal FDG_b3h is provided to connection transistor 461 in the second embodiment. Note that connection transistor 495 is an example of the sixth connection transistor described in the claims.

[0177] Note that reset transistor 402 is shared by FD common blocks 320 and 340. Reset transistor 422 is shared by FD common blocks 330 and 350.

[0178] The structures of FD shared blocks 360, 370, 380 and 390 are similar to those of FD shared blocks 320, 330, 340 and 350.

[0179] By turning on the connection transistor 494, pixels in FD shared block 340 and pixels in FD shared blocks above FD shared block 340 can be added. Furthermore, by turning on the connection transistor 495, pixels in FD shared block 350 and pixels in FD shared block 370 below FD shared block 350 can be added. This structure allows the addition of more than 32 pixels. For example, all pixels (64 pixels) in FD shared blocks 320, 330, 340, 350, 360, 370, 380, and 390 can be added. Moreover, since pixels from four blocks such as FD shared blocks 360, 370, 380, and 390 can be added to pixels outside these four blocks, the flexibility of pixel addition can be further improved.

[0180] Figure 24This is a plan view illustrating an example layout of the elements and wiring in the pixel array section 300 according to a second embodiment of the present technology.

[0181] like Figure 24 As shown, in the vertical direction, multiple FD wirings, such as FD wirings 308-2, 308-3, and 308-4, are mounted in a zigzag pattern. In the column containing the FD common block to the right of FD wiring 308-2, connection transistors 441 and 495 (FDG) are arranged horizontally. Note that connection transistor 494 (not shown) is arranged above connection transistor 495. Furthermore, in the horizontal direction, the reset transistor (RST) in the block adjacent to the added connection transistor 494 (FDG) is arranged to the right of connection transistor 494 (FDG).

[0182] Thus, according to the second embodiment of this technology, since a connection transistor 494 connected to FD line 308-1 and a connection transistor 495 connected to FD line 308-3 are provided, the number of pixels that can be added can be increased.

[0183] <Variation Example>

[0184] In the second embodiment described above, the reset transistor is arranged on the right side of the horizontal direction of the connecting transistor 494. This arrangement makes it difficult to reduce the number of wires in the vertical direction. The solid-state imaging element 200 in the variation of the second embodiment differs from the solid-state imaging element 200 of the second embodiment in that the arrangement of the transistors in the horizontal direction is changed, and the number of wires is reduced.

[0185] Figure 25 This is a plan view illustrating an example layout of elements and wiring in a pixel array section 300 according to a modified embodiment of the present invention. The layout of the modified embodiment differs from that of the second embodiment in that the two columns of the right-side block in the second embodiment are flipped horizontally. In the pixel array section 300 obtained after this horizontal flipping, the connection transistors 495 added to the left-side FD shared block and the right-side FD shared block are arranged adjacent to each other in the horizontal direction. With this structure, FD wiring 308-3 can be shared between the left and right sides. Other FD wirings besides FD wiring 308-3 can also be shared in the same way. Figure 25 As shown, since two adjacent columns can share a single FD wiring, the number of wirings in the vertical direction can be reduced.

[0186] Thus, according to a variation of the second embodiment of this technology, since the connection transistors 495 in the left FD common block and the right FD common block are arranged adjacent to each other in the horizontal direction, the FD wiring 308-3 can be shared between the left and right sides. This structure reduces the number of wirings in the vertical direction.

[0187] <3. Third Implementation Plan>

[0188] In the second embodiment described above, the reset transistor is used to connect the power supply node to the corresponding FD. According to this structure, the circuit is asymmetrical when the left FD common block is initialized and when the right FD common block is initialized. For example, when the right side is initialized, unlike when the left side is initialized, the power supply node requires two connection transistors in addition to the reset transistor. The solid-state imaging element 200 of the third embodiment differs from the solid-state imaging element 200 of the second embodiment in that circuit symmetry is provided by changing the connection destination of the reset transistor.

[0189] Figure 26 This is a circuit diagram illustrating a construction example of the pixel array section 300 in the third embodiment of the present technology. In the third embodiment, reset transistor 402 connects the power supply node to FD wiring 308-2 according to the reset signal RST_b0. Furthermore, reset transistor 422 connects the power supply node to FD wiring 308-2 according to the reset signal RST_b1. Through this connection, the number of transistors passing through the power supply node is the same whether the left FD common block is initialized or the right FD common block is initialized, thus maintaining circuit symmetry.

[0190] Note that variations of the second implementation scheme can be applied to the third implementation scheme.

[0191] Thus, according to the third embodiment of this technology, since the reset transistor 402 connects the power node to the FD wiring 308-2, the number of transistors passing through the power node can be the same when initializing the left FD common block and when initializing the right FD common block.

[0192] <4. Fourth Implementation Plan>

[0193] In the first embodiment described above, pixel addition is performed on a maximum of 32 pixels. However, in some cases, more pixels may need to be added. The solid-state camera element 200 of the fourth embodiment differs from that of the solid-state camera element 200 of the first embodiment in that the number of blocks connected to the FD wiring 308 is increased, and the number of pixels that can be added is increased.

[0194] Figure 27This is a circuit diagram illustrating a construction example of the pixel array section 300 in the fourth embodiment of the present technology. It is assumed that in the pixel block 310 of the fourth embodiment, FD common blocks 360, 370, 380 and 390 are further arranged below FD common blocks 320, 330, 340 and 350.

[0195] The structures of FD common blocks 360, 370, 380, and 390 are similar to those of FD common blocks 320, 330, 340, and 350. Furthermore, FD common blocks 360, 370, 380, and 390, along with FD common blocks 320, 330, 340, and 350, are all connected to FD wiring 308.

[0196] Note that the FD in blocks 360 and 380 is an example of a pair of third floating diffusion layers as described in the claims, and the FD in blocks 370 and 390 is an example of a pair of fourth floating diffusion layers as described in the claims.

[0197] like Figure 27 As shown, since 8 FD shared blocks are connected to FD wiring 308, the number of pixels that can be added can be greater than that in the first embodiment where 4 FD shared blocks are connected.

[0198] Note that although the number of blocks connected to FD wiring 308 has been described as increasing vertically, the number of blocks can also be increased horizontally. In this case, FD common blocks 360, 370, 380, and 390 can be arranged to the right or left of FD common blocks 320, 330, 340, and 350. The number of blocks connected to FD wiring 308 can be increased in both the vertical and horizontal directions. Furthermore, although the case of eight FD common blocks connected to FD wiring 308 has been described, more FD common blocks can be connected. By increasing the number of blocks in the vertical or horizontal direction, it is possible to connect up to all the FD common blocks.

[0199] Thus, according to the fourth embodiment of this technology, since the number of blocks connected to FD wiring 308 has increased, the number of pixels that can be added can be increased.

[0200] <5. Fifth Implementation Plan>

[0201] In the first embodiment described above, the solid-state camera element 200 generates image data by performing pixel addition. However, with this structure, it is difficult to measure the distance to an object. The electronic device of the fifth embodiment differs from the electronic device of the first embodiment in that it measures the distance to an object using a time-of-flight (ToF) method.

[0202] Figure 28 This is a block diagram illustrating a construction example of an electronic device 101 according to a fifth embodiment of the present technology. The electronic device 101 is a device that can measure the distance to an object using the Time-of-Flight (ToF) method, and the electronic device 101 includes a light-emitting unit 191, a solid-state imaging element 200, and a control unit 192.

[0203] The light-emitting unit 191 emits intermittent light in sync with a synchronization signal having a frequency set by the control unit 192. For example, near-infrared light can be used as the emitted light. Furthermore, a rectangular wave clock signal can be used as the synchronization signal. Note that a sine wave signal can also be used as the synchronization signal.

[0204] The solid-state imaging element 200 of the fifth embodiment receives the reflected light from the intermittent light and generates image data. The solid-state imaging element 200 generates image data synchronously with the vertical synchronization signal Vsync and provides the image data to the control unit 192. For example, the frequency of the vertical synchronization signal Vsync is 30Hz. Note that an optical unit is provided upstream of the solid-state imaging element 200 to collect and guide the reflected light to the solid-state imaging element 200; however, for ease of explanation, [the optical unit is not explicitly stated in the original text]. Figure 28 The optical component is omitted in the text.

[0205] The control unit 192 controls the light-emitting unit 191 and the solid-state imaging element 200. The control unit 192 provides synchronization signals to the light-emitting unit 191. Furthermore, the control unit 192 also transmits synchronization signals to the solid-state imaging element 200. These synchronization signals have frequencies higher than the vertical synchronization signal, where the vertical synchronization signal frequency is, for example, 10MHz to 20MHz.

[0206] Then, the control unit 192 receives image data from the solid-state camera element 200. Based on the image data, the control unit 192 measures the distance to the object and generates and outputs depth data to represent the measured value.

[0207] Figure 29 This is a circuit diagram illustrating a construction example of the left two pixels in pixel block 310 according to a fifth embodiment of the present invention. In the fifth embodiment, pixels 510, 530, 550, and 570 are arranged in 2 rows × 2 columns in each pixel block 310. Furthermore, FD wirings 508 and 509 are installed in pixel block 310, and two vertical signal lines are installed for each column of pixels. For example, vertical signal lines 309-1 and 309-2 are installed on both sides of the left column, and vertical signal lines 309-3 and 309-4 are installed on both sides of the right column.

[0208] Pixel 510 includes connection transistors 511 and 512, reset transistors 513 and 514, amplification transistors 515 and 516, and transmission transistors 517 and 518. Additionally, pixel 510 also includes selection transistors 519 and 520, FD transistors 521 and 522, and a photoelectric conversion element 523.

[0209] Connection transistor 511 connects FD 521 to FD wiring 508 according to the control signal FDGA_0 from the row selection unit 210. Connection transistor 512 connects FD 522 to FD wiring 509 according to the control signal FDGB_0 from the row selection unit 210.

[0210] Reset transistor 513 initializes the charge of FD 521 according to the reset signal RSTA_0 from the row selection unit 210. Reset transistor 514 initializes the charge of FD 522 according to the reset signal RSTB_0 from the row selection unit 210.

[0211] Amplifying transistor 515 amplifies the voltage signal from FD 521. Amplifying transistor 516 amplifies the voltage signal from FD 522.

[0212] Transmission transistor 517 transfers charge from photoelectric conversion element 523 to FD 521 according to transmission signal TGA_0 from row selection unit 210. Transmission transistor 518 transfers charge from photoelectric conversion element 523 to FD 522 according to transmission signal TGB_0 from row selection unit 210.

[0213] Selector transistor 519 outputs the amplified analog signal to analog-to-digital converter 240 via vertical signal line 309-1 based on the selection signal SELA_0 from the horizontal selection unit 210. Selector transistor 520 outputs the amplified analog signal to analog-to-digital converter 240 via vertical signal line 309-2 based on the selection signal SELB_0 from the horizontal selection unit 210.

[0214] FD 521 and FD 522 accumulate the transferred charge and generate a voltage corresponding to the amount of charge. Photoelectric conversion element 523 generates charge through photoelectric conversion.

[0215] Pixel 530 includes connection transistors 531 and 532, reset transistors 533 and 534, amplification transistors 535 and 536, and transmission transistors 537 and 538. Additionally, pixel 530 also includes selection transistors 539 and 540, FD transistors 541 and 542, and a photoelectric conversion element 543. The connection structure of these elements is similar to that in pixel 510.

[0216] In addition, the row selection unit 210 provides the pixel 530 with control signals FDGA_1 and FDGB_1, reset signals RSTA_1 and RSTB_1, transmission signals TGA_1 and TGB_1, and selection signals SELA_1 and SELB_1.

[0217] Note that FD 521 and FD 541 are examples of a pair of first floating diffusion layers as described in the claims, and FD 522 and FD 542 are examples of a pair of third floating diffusion layers as described in the claims.

[0218] Figure 30 This is a circuit diagram illustrating a construction example of the two right-hand pixels in pixel block 310 according to the fifth embodiment of the present invention. Pixel 550 includes connection transistors 551 and 552, reset transistors 553 and 554, amplification transistors 555 and 556, and transmission transistors 557 and 558. Furthermore, pixel 550 also includes selection transistors 559 and 560, FD transistors 561 and 562, and a photoelectric conversion element 563. The connection structure of these elements is similar to that in pixel 510.

[0219] In addition, the row selection unit 210 provides the pixel 550 with control signals FDGA_2 and FDGB_2, reset signals RSTA_2 and RSTB_2, transmission signals TGA_2 and TGB_2, and selection signals SELA_2 and SELB_2.

[0220] Pixel 570 includes connection transistors 571 and 572, reset transistors 573 and 574, amplification transistors 575 and 576, and transmission transistors 577 and 578. Additionally, pixel 570 also includes selection transistors 579 and 580, FD transistors 581 and 582, and a photoelectric conversion element 583. The connection structure of these elements is similar to that in pixel 510.

[0221] In addition, the row selection unit 210 provides the pixel 570 with control signals FDGA_3 and FDGB_3, reset signals RSTA_3 and RSTB_3, transmission signals TGA_3 and TGB_3, and selection signals SELA_3 and SELB_3.

[0222] Note that FD 561 and 581 are examples of a pair of second floating diffusion layers as described in the claims, and FD 562 and 582 are examples of a pair of fourth floating diffusion layers as described in the claims.

[0223] Figure 31This is a timing diagram illustrating an example of the operation of the electronic device 101 according to the fifth embodiment of the present technology. The control unit 192 provides a synchronization signal to the light-emitting unit 191 to cause it to emit light. For example, the light-emitting unit 191 emits light during the period from time T0 to time T1, and turns off the light during the period from time T1 to time T2.

[0224] Furthermore, the line selection unit 210 also provides a transmission signal TGA with a 0-degree phase difference relative to the aforementioned synchronization signal and a transmission signal TGB with a 180-degree phase difference relative to the aforementioned synchronization signal. Through this operation, a charge corresponding to the amount of reflected light received during the period from time T0 to time T1 is transferred to FD 521, and a charge corresponding to the amount of reflected light received during the period from time T1 to time T2 is transferred to FD 522. The control unit 192 performs distance measurement processing corresponding to the time of flight of light based on the signal output from the solid-state imaging element 200. Note that circuitry in the solid-state imaging element 200 (such as the signal processing unit 260) can replace the control unit 192 in measuring the distance.

[0225] Furthermore, by controlling the connection transistor 511, signals with a 0-degree phase difference and signals with a 180-degree phase difference can be added separately.

[0226] Thus, according to the fifth embodiment of this technology, since signals with different phase differences relative to the synchronization signal are transmitted to each FD 521 and 522, the distance to the object can be measured by the ToF method based on these signals.

[0227] <First Variation>

[0228] In the fifth embodiment described above, two FD lines 508 and 509 have been installed for each pixel block 310. However, with this structure, it is difficult to reduce the number of lines. The solid-state imaging element 200 of the first variation of the fifth embodiment differs from the solid-state imaging element 200 of the fifth embodiment in that four pixels share one FD line, thus reducing the number of lines.

[0229] Figure 32 This is a circuit diagram illustrating a construction example of the left two pixels in pixel block 310 of the first variation of the fifth embodiment of the present invention. The pixel block 310 of the first variation of the fifth embodiment differs from that of the pixel block 310 of the fifth embodiment in that the FD wiring 509 is not installed. Furthermore, connecting transistors 512 and 532 are connected to FD wiring 508 instead of FD wiring 509. Pixels 550 and 570 are constructed similarly. With this structure, FD wiring 509 can be eliminated.

[0230] Thus, in the first variation of the fifth embodiment of this technology, since the connection transistors of each of the four pixels are all connected to the FD wiring 508, the FD wiring 509 can be removed.

[0231] <Second Variation>

[0232] In the fifth embodiment described above, transfer transistors 517 and 518 transfer charge to FDs 521 and 522 arranged in the horizontal direction, respectively. The arrangement direction of the transfer destination FD can also be vertical. The difference between the solid-state imaging element 200 of the second variation of the fifth embodiment and the solid-state imaging element 200 of the fifth embodiment is that charge is transferred to FDs 521 and 522 arranged in the vertical direction.

[0233] Figure 33 This is a circuit diagram illustrating a construction example of pixel block 310 in a second variation of the fifth embodiment of the present invention. The difference between pixel block 310 in the second variation of the fifth embodiment and pixel block 310 in the fifth embodiment is that only two pixels 510 and 530 are arranged.

[0234] Furthermore, FD 521 and 522 are arranged in the vertical direction, and FD 541 and 542 are arranged in the vertical direction.

[0235] Note that FD 521 and 522 are examples of a pair of first floating diffusion layers as described in the claims, and FD 541 and 542 are examples of a pair of second floating diffusion layers as described in the claims.

[0236] In addition, FD wiring 509 is removed, and connecting transistors 512 and 532 are connected to FD wiring 508.

[0237] The row selection unit 210 turns on or off connecting transistors 511, 512, 531, and 532, and connects FDs 521, FD 522, FD 541, and FD 542 in the horizontal, vertical, or diagonal directions. This structure allows signals with different phase differences to be added in pixels 510 and 530, and signals with the same phase difference to be added. For example, a signal with a 0-degree phase difference in pixel 510 can be added to a signal with a 180-degree phase difference in pixel 530. Alternatively, a signal with a 0-degree phase difference in pixel 510 can be added to a signal with a 0-degree phase difference in pixel 530.

[0238] Thus, in the second variation of the fifth embodiment of this technology, since FD 521 and 522 are arranged in the vertical direction and FD 541 and 542 are arranged in the vertical direction, any one of the signals with different phase differences and signals with the same phase difference can be arbitrarily selected and added.

[0239] <6. Sixth Implementation Plan>

[0240] In the first embodiment described above, a maximum of 2×2 FD shared blocks are connected together, and the FDs are shared by these blocks. However, the FD sharing range can be arbitrarily changed. The solid-state camera element 200 of the sixth embodiment differs from the solid-state camera element 200 of the first embodiment in that the FD sharing range is variable.

[0241] Figure 34 This is a circuit diagram illustrating a construction example of the upper FD common blocks 320, 330, 340, and 350 in the sixth embodiment of this technology. The components arranged in each FD common block are similar to... Figure 26 The components are shown. However, the upper right FD common block 340 and the FD common block 350 below it are connected via FD wiring 308-3, and the FD common block 350 and the FD common block 370 below it are connected via FD wiring 308-5. Furthermore, FD wiring 308-2 is not installed to reach the FD common block below it, and FD wiring 308-4 is installed between FD common blocks 330 and 350.

[0242] Furthermore, FD wiring 308-2 is connected to FD wiring 308-3, and FD wiring 308-4 is also connected to FD wiring 308-5. Connecting transistor 494 connects FD wiring 308-1 to FD wiring 308-3 according to the control signal FDG_b2v. Connecting transistor 495 connects FD wiring 308-3 to FD wiring 308-5 according to the control signal FDG_b3v.

[0243] By putting Figure 34When connecting transistors 401, 421, and 495 are turned on, left-side FDs 321 and 331 can be connected to FD line 308-3 via FD lines 308-2 and 308-4. Furthermore, by turning on connecting transistor 441, right-side FD 341 can be connected to FD line 308-3 via FD line 308-2. Note that the circuit including connecting transistors 401, 421, and 495 is an example of the first connection circuit described in the claims, and the circuit including connecting transistor 441 is an example of the second connection circuit described in the claims. Connecting transistors 401, 421, and 495 are examples of the first, second, and third connecting transistors described in the claims, and connecting transistor 441 is an example of the fourth connecting transistor described in the claims. FD line 308-3 is an example of the first wiring described in the claims. FD line 308-2 is an example of the second wiring described in the claims. FD line 308-4 is an example of the third wiring described in the claims.

[0244] Figure 35 This is a circuit diagram illustrating a construction example of the lower FD common blocks 360, 370, 380, and 390 in the sixth embodiment of this technology. The structure of these FD common blocks is similar to that of the upper FD common blocks 320, 330, 340, and 350. However, the upper right FD common block 370 and the FD common block 390 below it are connected via FD wiring 309-7. Furthermore, FD wiring 309-6 is installed between FD common blocks 360 and 370, and FD wiring 309-8 is installed between FD common blocks 380 and 390. Additionally, FD wiring 309-6 is connected to FD wiring 309-7.

[0245] pass Figure 34 and Figure 35 As shown in the structure, the solid-state imaging element 200 can easily change the FD sharing range. For example, all 2×4 FD sharing blocks (FD sharing blocks 320 to 390) can be connected together, and the FD can be shared by these FD sharing blocks. The upper four FD sharing blocks can be further connected via FD wiring 308-1, and 4×4 FD sharing blocks can share the FD. More FD sharing blocks can also be connected together, and 4×N (N is an integer) FD sharing blocks can share the FD.

[0246] Thus, according to the sixth embodiment of this technology, since connecting transistors 494 and 495 are provided, and the FD common block is connected in the vertical direction through connecting transistors 494 and 495, the FD common range can be arbitrarily changed.

[0247] <7. Examples of applications of moving objects>

[0248] The technology according to various embodiments of this disclosure (the technology) can be applied to a variety of products. For example, the technology according to various embodiments of this disclosure can be implemented as a device installed on any type of mobile body, including automobiles, electric vehicles, hybrid vehicles, autonomous two-wheelers, bicycles, personal motor vehicles, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0249] Figure 36 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology of various embodiments of this disclosure is applicable.

[0250] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 36 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0251] The drive system control unit 12010 controls the operation of equipment related to the vehicle drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as: a drive force generating device for generating vehicle driving force, such as an internal combustion engine or drive motor; a drive force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0252] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for various devices such as: keyless entry system; smart key system; power windows; or various vehicle lights including headlights, reversing lights, brake lights, turn signals, or fog lights. In this case, radio waves sent from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locking devices, power windows, or vehicle lights, etc.

[0253] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, text on the road surface, etc., based on the received images.

[0254] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0255] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 may include a camera that captures images of the driver. The in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off, based on the detection information input from the driver state detection unit 12041.

[0256] Based on information about the vehicle's interior or exterior acquired by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can calculate target control values ​​for the drive force generating device, steering mechanism, or braking device, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance, impact mitigation, distance-based following, cruise control, collision warning, and lane departure warning.

[0257] Furthermore, based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control, such as controlling the drive force generating device, steering mechanism, or braking device, to achieve autonomous driving that enables the vehicle to drive itself without relying on the driver's operation.

[0258] Furthermore, based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, based on the position of the vehicle in front or oncoming vehicle detected by the exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control aimed at achieving anti-glare effects by controlling the headlights and switching from high beam to low beam.

[0259] The sound and image output unit 12052 sends an output signal of at least one of sound and image to an output device that can visually or audibly notify vehicle passengers or external devices. Figure 36 In the example shown, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an onboard display and a head-up display.

[0260] Figure 37 This is a diagram showing an example of the mounting location of the camera unit 12031.

[0261] exist Figure 37 In the middle, as a camera unit 12031, camera units 12101, 12102, 12103, 12104 and 12105 are provided.

[0262] For example, camera units 12101, 12102, 12103, 12104, and 12105 are installed in locations on the vehicle 12100 such as the front nose, side mirrors, rear bumper, trunk lid, and the upper part of the interior windshield. Camera unit 12101 at the front nose and camera unit 12105 at the upper part of the interior windshield primarily acquire images of the front of the vehicle 12100. Camera units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Camera unit 12104 at the rear bumper or trunk lid primarily acquires images of the rear of the vehicle 12100. Camera unit 12105 at the upper part of the interior windshield is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, or lanes ahead.

[0263] Notice, Figure 37An example of the imaging range of camera units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of camera unit 12101 located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of camera units 12102 and 12103 located at the side mirrors, respectively. Imaging range 12114 represents the imaging range of camera unit 12104 located at the rear bumper or trunk lid. For example, image data captured by camera units 12101 to 12104 are superimposed to obtain a top-view image of vehicle 12100.

[0264] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple imaging elements, or an imaging element having pixels for phase difference detection.

[0265] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within the camera range 12111 to 12114 and how that distance changes over time (relative speed to vehicle 12100). Specifically, it can extract three-dimensional objects as the nearest objects on the vehicle 12100's travel path, and objects traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a pre-determined inter-vehicle distance with respect to the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. In this way, coordinated control aimed at achieving autonomous driving, etc., that enables the vehicle to drive autonomously without relying on driver operation, can be executed.

[0266] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and extract the classified three-dimensional object data, and can use the data for automatic obstacle avoidance. For example, microcomputer 12051 distinguishes obstacles around vehicle 12100 into obstacles that can be visually identified by the driver of vehicle 12100 and obstacles that are difficult to visually identify. Then, microcomputer 12051 determines the collision risk, which represents the degree of danger of colliding with each obstacle. If the collision risk is equal to or greater than a set value and a collision is likely to occur, microcomputer 12051 can provide driving assistance for collision avoidance by issuing a warning to the driver via audio speaker 12061 or display unit 12062, or by forcibly decelerating or evasive steering via drive system control unit 12010.

[0267] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 identifies a pedestrian by determining that a pedestrian exists in the images captured by the camera units 12101 to 12104, the audio-visual output unit 12052 controls the display unit 12062 to overlay a square outline for emphasis on the identified pedestrian. Furthermore, the audio-visual output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0268] An example of a vehicle control system to which the technology according to various embodiments of the present disclosure is applicable has been described above. The technology according to various embodiments of the present disclosure can be applied, for example, to the camera unit 12031 in the above-described configuration. Specifically, for example, Figure 1 The camera device 100 can be applied to the camera unit 12031. By applying the technology of each embodiment of the present disclosure to the camera unit 12031, highly flexible pixel addition can be performed, and the captured image can be obtained that is easier to view, thereby reducing driver fatigue.

[0269] Note that the above embodiments illustrate one example for implementing this technology. The matters in the embodiments and the matters defining the invention in the claims are related. Similarly, the matters defining the invention in the claims are related to the matters with the same names in the embodiments of this technology. However, this technology is not limited to the embodiments and can be implemented through various modifications to the embodiments without departing from the spirit of the invention.

[0270] Note that the effects described in this specification are illustrative and not limiting, and may produce other effects.

[0271] Note that this technology can also have the following configurations.

[0272] (1) A solid-state imaging element, comprising:

[0273] A pair of first floating diffusion layers are arranged in a vertical direction perpendicular to a predetermined direction;

[0274] A pair of second floating diffusion layers are arranged in the vertical direction and are adjacent to the pair of first floating diffusion layers in the predetermined direction;

[0275] A first connection circuit is configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring.

[0276] A second connection circuit is configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring; and

[0277] The output circuit is configured to output an output signal corresponding to the charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers.

[0278] (2) The solid-state camera element according to (1), wherein

[0279] The first connection circuit includes:

[0280] A first connection transistor is configured to connect one of the pair of first floating diffusion layers to the first wiring according to a first control signal; and

[0281] The second connection transistor is configured to connect the other of the pair of first floating diffusion layers to the first wiring according to a second control signal, and

[0282] The second connection circuit includes:

[0283] A third connection transistor is configured to connect one of the pair of second floating diffusion layers to the first wiring according to a third control signal; and

[0284] A fourth connection transistor is configured to connect the other of the pair of second floating diffusion layers to the first wiring according to a fourth control signal.

[0285] (3) The solid-state camera element according to (2), wherein

[0286] A reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction, and

[0287] A selection transistor is disposed between the first connection transistor and the second connection transistor in the vertical direction.

[0288] (4) The solid-state camera element according to (2), wherein

[0289] The first connection transistor and the third connection transistor are configured to be adjacent to each other in the predetermined direction, and

[0290] A selection transistor is disposed between the first connection transistor and the second connection transistor in the vertical direction.

[0291] (5) The solid-state camera element according to (2), wherein

[0292] A reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction, and

[0293] The first connection transistor and the second connection transistor are configured to be adjacent to each other in the vertical direction.

[0294] (6) The solid-state camera element according to (2), wherein

[0295] The first connection transistor and the third connection transistor are configured to be adjacent to each other in the predetermined direction, and

[0296] The first connection transistor and the second connection transistor are configured to be adjacent to each other in the vertical direction.

[0297] (7) The solid-state camera element according to (2), wherein

[0298] The second connection circuit also includes:

[0299] A fifth connection transistor is configured to connect one of the pair of second floating diffusion layers to a predetermined second wiring according to a fifth control signal; and

[0300] A sixth connection transistor is configured to connect the other of the pair of second floating diffusion layers to a predetermined third wiring according to a sixth control signal.

[0301] (8) The solid-state imaging element according to (7), wherein

[0302] A reset transistor is disposed adjacent to the fifth connecting transistor in the predetermined direction.

[0303] (9) The solid-state imaging element according to (7), wherein

[0304] A predetermined number of the fifth connection transistors are arranged adjacent to each other in the predetermined direction.

[0305] (10) The solid-state imaging element according to (7) or (8), wherein

[0306] The output circuit also includes:

[0307] A first reset transistor is configured to connect a predetermined power node to the first wiring according to a first reset signal; and

[0308] The second reset transistor is configured to connect a predetermined power node to the first wiring according to a second reset signal.

[0309] (11) The solid-state imaging element according to (1) further includes:

[0310] A pair of third floating diffusion layers are arranged in the vertical direction;

[0311] A pair of fourth floating diffusion layers are arranged in the vertical direction and are adjacent to the pair of third floating diffusion layers in the predetermined direction;

[0312] A third connection circuit is configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and

[0313] A fourth connection circuit is configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring.

[0314] (12) The solid-state imaging element according to (1) further includes:

[0315] The signal processing unit is configured to perform distance measurement processing corresponding to the time of flight of light based on the output signal.

[0316] (13) The solid-state camera element according to (12) further includes:

[0317] A pair of third floating diffusion layers are arranged in the vertical direction;

[0318] A pair of fourth floating diffusion layers are arranged in the vertical direction;

[0319] A third connection circuit is configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to a predetermined second wiring; and

[0320] A fourth connection circuit is configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the second wiring.

[0321] The output circuit outputs an output signal corresponding to the charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers, and an output signal corresponding to the charge amount of at least one of the pair of third floating diffusion layers and the pair of fourth floating diffusion layers.

[0322] (14) The solid-state imaging element according to (12) further includes:

[0323] A pair of third floating diffusion layers are arranged in the vertical direction;

[0324] A pair of fourth floating diffusion layers are arranged in the vertical direction;

[0325] A third connection circuit is configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and

[0326] A fourth connection circuit is configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring.

[0327] The output circuit outputs an output signal corresponding to the charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers, and an output signal corresponding to the charge amount of at least one of the pair of third floating diffusion layers and the pair of fourth floating diffusion layers.

[0328] (15) The solid-state imaging element according to (12) further includes:

[0329] A first transfer transistor is configured to transfer charge from a first photoelectric conversion element to one of the pair of first floating diffusion layers;

[0330] The second transfer transistor is configured to transfer charge from the first photoelectric conversion element to the other of the pair of first floating diffusion layers;

[0331] A third transfer transistor is configured to transfer charge from the second photoconversion element to one of the pair of second floating diffusion layers; and

[0332] A fourth transfer transistor is configured to transfer charge from the second photoelectric conversion element to the other of the pair of second floating diffusion layers.

[0333] (16) The solid-state imaging element according to (1), wherein

[0334] The first connection circuit includes:

[0335] A first connection transistor is configured to connect one of the pair of first floating diffusion layers to a second wiring connected to the first wiring according to a first control signal;

[0336] A second connection transistor is configured to connect the other of the pair of first floating diffusion layers to a third wiring according to a second control signal; and

[0337] A third connection transistor is configured to connect the first wiring to the third wiring according to a third control signal.

[0338] And the second connection circuit includes:

[0339] A fourth connection transistor connects one of the pair of second floating diffusion layers to the second wiring according to a fourth control signal.

[0340] (17) An electronic device comprising:

[0341] A pair of first floating diffusion layers are arranged in a vertical direction perpendicular to a predetermined direction;

[0342] A pair of second floating diffusion layers are arranged in the vertical direction and are adjacent to the pair of first floating diffusion layers in the predetermined direction;

[0343] A first connection circuit is configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring.

[0344] A second connection circuit is configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring.

[0345] An output circuit configured to output an output signal corresponding to the charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers; and

[0346] An analog-to-digital converter is configured to perform analog-to-digital conversion processing on the output signal.

[0347] Those skilled in the art should understand that various modifications, combinations, sub-combinations and variations can be made according to design requirements and other factors, as long as they fall within the protection scope of the appended claims or their equivalents.

[0348] [List of reference numerals]

[0349] 100: Camera device

[0350] 101: Electronic Equipment

[0351] 110: Optics Department

[0352] 120: DSP circuit

[0353] 130: Display Section

[0354] 140: Operations Department

[0355] 150: Bus

[0356] 160: Frame Memory

[0357] 170: Storage Department

[0358] 180: Power Supply Section

[0359] 191: Light-emitting part

[0360] 192: Control Department

[0361] 200: Solid-state camera element

[0362] 201: Pixel chip

[0363] 202: Circuit Chip

[0364] 210: Row Selection Department

[0365] 220: Digital-to-Analog Converter (DAC)

[0366] 230: Timing control circuit

[0367] 240: Analog-to-Digital Conversion Unit

[0368] 241: Analog-to-Digital Converter (ADC)

[0369] 242: Comparator

[0370] 243: Counter

[0371] 244: Latch circuit

[0372] 250: Horizontal transmission scanning unit

[0373] 260: Signal Processing Department

[0374] 300: Pixel array section

[0375] 307: Power cord

[0376] 308, 508, 509: FD wiring

[0377] 309: Vertical signal line

[0378] 310: Pixel Block

[0379] 311, 510, 530, 550, 570: pixels

[0380] 320, 330, 340, 350, 360, 370, 380, 390: FD shared blocks

[0381] 321, 331, 341, 351, 521, 522, 541, 542, 561, 562, 581, 582: FD

[0382] 401, 421, 441, 461, 494, 495, 511, 512, 531, 532, 551, 552, 571, 572: Connecting transistors

[0383] 402, 422, 442, 462, 513, 514, 533, 534, 553, 554, 573, 574: Reset transistors

[0384] 403 to 410, 423 to 430, 443 to 450, 463 to 470, 517, 518, 537, 538, 557, 558, 577, 578: Transmission transistors

[0385] 411 to 418, 431 to 438, 451 to 458, 471 to 478, 523, 543, 563, 583: Photoelectric conversion elements

[0386] 419, 439, 459, 479, 515, 516, 535, 536, 555, 556, 575, 576: Amplifying transistors

[0387] 420, 440, 460, 480, 519, 520, 539, 540, 559, 560, 579, 580: Select transistors

[0388] 490, 491: Connection circuit

[0389] 492: Output Circuit

[0390] 12031: Camera Department

Claims

1. A solid-state imaging device comprising: a pair of first floating diffusion layers arranged in a vertical direction perpendicular to a predetermined direction; a pair of second floating diffusion layers arranged in the vertical direction and adjacent to the pair of first floating diffusion layers in the predetermined direction; a first connection circuit configured to select at least one of the pair of first floating diffusion layers and connect the selected first floating diffusion layer to a predetermined first wiring; a second connection circuit configured to select at least one of the pair of second floating diffusion layers and connect the selected second floating diffusion layer to the first wiring; and an output circuit configured to output an output signal corresponding to a charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers, wherein the first connection circuit includes: a first connection transistor configured to connect one of the pair of first floating diffusion layers to a second wiring connected to the first wiring in accordance with a first control signal; a second connection transistor configured to connect the other of the pair of first floating diffusion layers to a third wiring in accordance with a second control signal; and a third connection transistor configured to connect the first wiring to the third wiring in accordance with a third control signal, and the second connection circuit includes: a fourth connection transistor configured to connect one of the pair of second floating diffusion layers to the second wiring in accordance with a fourth control signal.

2. The solid-state imaging device according to claim 1, wherein a reset transistor is provided between the first connection transistor and the third connection transistor in the predetermined direction, and a selection transistor is provided between the first connection transistor and the second connection transistor in the vertical direction.

3. The solid-state imaging device according to claim 1, wherein the first connection transistor and the third connection transistor are provided to be adjacent to each other in the predetermined direction, and a selection transistor is provided between the first connection transistor and the second connection transistor in the vertical direction.

4. The solid-state imaging device according to claim 1, wherein a reset transistor is provided between the first connection transistor and the third connection transistor in the predetermined direction, and the first connection transistor and the second connection transistor are provided to be adjacent to each other in the vertical direction.

5. The solid-state imaging device according to claim 1, wherein the first connection transistor and the third connection transistor are provided to be adjacent to each other in the predetermined direction, and the first connection transistor and the second connection transistor are provided to be adjacent to each other in the vertical direction.

6. The solid-state imaging device according to claim 1, wherein the second connection circuit further includes: a fifth connection transistor configured to connect one of the pair of second floating diffusion layers to a predetermined second wiring in accordance with a fifth control signal; and a sixth connection transistor configured to connect the other of the pair of second floating diffusion layers to a predetermined third wiring in accordance with a sixth control signal. ​ 7. The solid-state image pickup element according to claim 6, wherein a reset transistor is provided adjacently to the fifth connection transistor in the predetermined direction.

8. The solid-state image pickup element according to claim 6, wherein a predetermined number of the fifth connection transistors are arranged adjacently to each other in the predetermined direction.

9. The solid-state image pickup element according to claim 6, wherein the output circuit further includes: a first reset transistor configured to connect a predetermined power supply node to the first wiring in accordance with a first reset signal; and a second reset transistor configured to connect a predetermined power supply node to the first wiring in accordance with a second reset signal.

10. The solid-state image pickup element according to claim 1, further comprising: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction and adjacent to the pair of third floating diffusion layers in the predetermined direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring.

11. The solid-state image pickup element according to claim 1, further comprising: a signal processing section configured to perform a distance measurement process corresponding to a time of flight of light based on the output signal.

12. The solid-state image pickup element according to claim 11, further comprising: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to a predetermined second wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the second wiring, wherein the output circuit outputs an output signal corresponding to a charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers and an output signal corresponding to a charge amount of at least one of the pair of third floating diffusion layers and the pair of fourth floating diffusion layers.

13. The solid-state image pickup element according to claim 11, further comprising: a pair of third floating diffusion layers arranged in the vertical direction; a pair of fourth floating diffusion layers arranged in the vertical direction; a third connection circuit configured to select at least one of the pair of third floating diffusion layers and connect the selected third floating diffusion layer to the first wiring; and a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and connect the selected fourth floating diffusion layer to the first wiring, wherein the output circuit outputs an output signal corresponding to a charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers and an output signal corresponding to a charge amount of at least one of the pair of third floating diffusion layers and the pair of fourth floating diffusion layers. ​ ​ The output circuit outputs an output signal corresponding to a charge amount of at least one of the pair of first floating diffusion layers and the pair of second floating diffusion layers and an output signal corresponding to a charge amount of at least one of the pair of third floating diffusion layers and the pair of fourth floating diffusion layers.

14. The solid-state image pickup element according to claim 11, further comprising: a first transfer transistor configured to transfer a charge from the first photoelectric conversion element to one of the pair of first floating diffusion layers; a second transfer transistor configured to transfer a charge from the first photoelectric conversion element to the other of the pair of first floating diffusion layers; a third transfer transistor configured to transfer a charge from the second photoelectric conversion element to one of the pair of second floating diffusion layers; and a fourth transfer transistor configured to transfer a charge from the second photoelectric conversion element to the other of the pair of second floating diffusion layers.

15. An electronic apparatus comprising: the solid-state image pickup element according to any one of claims 1 to 14; and an analog-digital conversion section configured to perform an analog-digital conversion process on the output signal. ​ ​

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