High bandwidth signal processing systems, devices, methods, and storage media

Abstract

The application discloses a high-bandwidth signal processing system, device, method and storage medium, and relates to the field of signal processing.The high-bandwidth signal processing system comprises a camera, an image blocking module, a motion sensor, an image processing accelerator, a multi-core task processor and a storage module; the camera is used for shooting an image and generating corresponding two-dimensional image information; the image blocking module is used for blocking the two-dimensional image information to form multi-channel serial data; the motion sensor is used for acquiring position information and motion state information of the high-bandwidth signal processing system; the multi-core task processor performs task distribution and scheduling on the image processing accelerator, so that the image processing accelerator performs data processing in a parallel multi-stage pipeline mode to realize recognition tracking and positioning of a target object.The high-bandwidth signal processing system, device, method and storage medium according to the embodiment of the application can improve the speed and accuracy of signal processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and in particular to a high-bandwidth signal processing system, device, method and storage medium. BACKGROUND

[0002] With the rapid development of flight recorders, the demand for high-resolution cameras is also gradually increasing, and therefore new demands are placed on image processing capabilities. The amount of data transmitted by high-resolution cameras in real-time detection is very large, and therefore a high-bandwidth signal processing system that can be adapted to high-resolution cameras and that realizes real-time data processing is needed, which guarantees the accuracy of signal processing and improves processing speed as much as possible. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes a high-bandwidth signal processing system, device, method and storage medium, which can improve the speed and accuracy of signal processing.

[0004] In one aspect, the high-bandwidth signal processing system according to an embodiment of the present application comprises: a camera configured to capture images and generate corresponding two-dimensional image information; an image blocking module configured to block the two-dimensional image information to form multi-channel serial data; a motion sensor configured to obtain position information and motion state information of the high-bandwidth signal processing system; an image processing accelerator configured to obtain data transmitted by the image blocking module and the motion sensor and perform data processing in a parallel multi-stage pipeline manner to realize identification and positioning of a target object; a multi-core task processor configured to perform task allocation and scheduling for a data processing process of the image processing accelerator and obtain a data processing result of the image processing accelerator; and a storage module configured to provide a data caching function for the image processing accelerator and provide a training set for the image processing accelerator.

[0005] According to some embodiments of the present application, a communication interface is further included, which is electrically connected to the multi-core task processor.

[0006] According to some embodiments of the present application, the image processing accelerator comprises: a data interface, configured to restore the multi-channel serial data into the two-dimensional image information; an image segmentation module, configured to perform image segmentation on the two-dimensional image information to obtain an image block containing the target object; a target data processing module, configured to perform first preprocessing on the image block to obtain first image data; an image resolution truncation module, configured to perform resolution truncation on the two-dimensional image information to obtain image information containing only background data; a background data processing module, configured to perform second preprocessing on the image information to obtain second image data; an image encoding compression module, configured to perform encoding compression on the first image data and the second image data to obtain third image data; a visual processing module, configured to perform data processing in a parallel multi-stage pipeline manner according to the third image data to realize recognition and positioning of the target object; and a feedback module, configured to send the data processing result of the visual processing module as feedback information to the image segmentation module and the image resolution truncation module.

[0007] According to some embodiments of the present application, the image processing accelerator and the storage module are directly connected on a PCB.

[0008] According to some embodiments of the present application, the image processing accelerator and the multi-core task processor are of a heterogeneous structure.

[0009] In another aspect, an electronic device according to an embodiment of the present application comprises the high-bandwidth signal processing system as described above.

[0010] In another aspect, a signal processing method according to an embodiment of the present application comprises: obtaining two-dimensional image information containing a target object; obtaining position information and motion state information of a high-bandwidth signal processing system; and performing data processing in a parallel multi-stage pipeline manner according to the two-dimensional image information, the position information and the motion state information to realize recognition and positioning of the target object.

[0011] According to some embodiments of the present application, after the step of obtaining the two-dimensional image information, the method further comprises the following steps: performing blocking on the two-dimensional image information to form multi-channel serial data; and performing serial-parallel conversion on the serial data to restore the two-dimensional image information.

[0012] According to some embodiments of the present application, the data processing is performed in parallel multi-stage pipeline manner according to the two-dimensional image information, the position information and the motion state information to realize the identification and positioning of the target object, which comprises the following steps: image segmentation is performed on the two-dimensional image information to obtain an image block containing the target object; first preprocessing is performed on the image block to obtain first image data; resolution truncation is performed on the two-dimensional image information to obtain image information containing only background data; second preprocessing is performed on the image information to obtain second image data; the first image data and the second image data are encoded and compressed to obtain third image data; and the third image data, the position information and the motion state information are processed in parallel multi-stage pipeline manner to realize the identification and positioning of the target object.

[0013] In another aspect, the computer readable storage medium according to the embodiments of the present application stores a program, and the program is executed by a processor to realize the signal processing method as described above.

[0014] The high-bandwidth signal processing system, device, method and storage medium according to the embodiments of the present application have at least the following beneficial effects: through the cooperation of the camera and the motion sensor, the result of signal processing can be properly calibrated from different dimensions in signal processing to improve the detection accuracy; through the cooperation of the image processing accelerator and the multi-core task processor, the data processing can be completed in parallel multi-stage pipeline manner, the speed of signal processing is improved, and the accurate identification and positioning of the target object can be realized.

[0015] Additional aspects and advantages of the present application will be given in part in the following description, will become apparent in part from the following description, or will be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 FIG. 1 is a structural schematic diagram of a high-bandwidth signal processing system according to an embodiment of the present application;

[0018] Figure 2 FIG. 2 is a structural schematic diagram of an image processing accelerator according to an embodiment of the present application;

[0019] Figure 3 FIG. 3 is a schematic diagram of the working principle of an image segmentation module according to an embodiment of the present application;

[0020] Figure 4 FIG. 4 is a schematic diagram of the pipeline processing structure of the image processing accelerator according to an embodiment of the present application;

[0021] Figure 5 Flow chart of steps of signal processing method of embodiments of the present application;

[0022] Reference signs:

[0023] Camera 100, image block module 200, motion sensor 300, image processing accelerator 400, data interface 410, image segmentation module 420, target data processing module 430, image resolution truncation module 440, background data processing module 450, image encoding compression module 460, visual processing module 470, feedback module 480, multi-core task processor 500, storage module 600, communication interface 700, image block 800. DETAILED DESCRIPTION

[0024] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the drawings, the role of the drawings is to supplement the description of the text part with graphics, so that people can intuitively and visually understand each technical feature and the overall technical solution of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0025] In the description of the present application, the meaning of several is one or more, the meaning of multiple is more than two, greater than, less than, more than, etc. are understood as not including the number, above, below, within, etc. are understood as including the number. If it is described as first, second, it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0026] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be understood broadly, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0027] On the one hand, as Figure 1As shown, the high-bandwidth signal processing system according to the embodiment of the application comprises a camera 100, an image block module 200, a motion sensor 300, an image processing accelerator 400, a multi-core task processor 500 and a storage module 600. The image block module 200 is electrically connected with the camera 100, the image processing accelerator 400 is electrically connected with the image block module 200 and the motion sensor 300 respectively, and the multi-core task processor 500 and the storage module 600 are electrically connected with the image processing accelerator 400 respectively. The camera 100 is configured to capture images and generate corresponding two-dimensional image information. The image block module 200 is configured to block the two-dimensional image information to form multi-channel serial data and send the multi-channel serial data to the image processing accelerator 400. The motion sensor 300 is configured to acquire position information and motion state information of the high-bandwidth signal processing system and send the position information and the motion state information to the image processing accelerator 400. The multi-core task processor 500 is configured to perform task allocation and scheduling on the image processing accelerator 400, so that the image processing accelerator 400 performs data processing in a parallel multi-stage pipeline manner to realize recognition tracking and positioning of a target object, and sends a data processing result to the multi-core task processor 500. The storage module 600 is configured to provide a data buffering function for the image processing accelerator 400 and provide a training set for the image processing accelerator 400.

[0028] Specifically, in some embodiments, the camera 100 adopts a high-precision and high-resolution high-speed camera with a resolution of 1080p or above. After the camera 100 captures images, the camera 100 outputs data to the image block module 200 in the form of two-dimensional image information storage and high-speed serial. The image block module 200 blocks the two-dimensional image information sent by the camera 100 and sends serial data to the image processing accelerator 400 in a multi-channel parallel transmission mode, thereby reducing the data transmission amount of a single channel at a time. The image processing accelerator 400 is based on the parallel processing operation capability of the FPGA (Field Programmable Gate Array) architecture and is adapted to the multi-core task processor 500, so that data is processed in the form of a parallel multi-core multi-stage pipeline in the image processing accelerator 400, thereby completing recognition tracking and positioning of a target object. The multi-core task processor 500 can adopt an ARM architecture and is configured to schedule and allocate pipeline tasks of the image processing accelerator 400, thereby realizing high-speed transmission and processing of data and avoiding data congestion. The storage module 600 comprises multiple high-bandwidth memories and has functions of data buffering and PINGPONG data interaction. Meanwhile, the storage module 600 is configured to provide a basic image training set for the image processing accelerator 400, so that the image processing accelerator 400 performs training to form an accurate operation parameter model.

[0029] The high-bandwidth signal processing system according to the embodiment of the present application can calibrate the signal processing result from different dimensions to improve the detection accuracy through the cooperation of the camera 100 and the motion sensor 300; the data processing can be completed in the form of parallel multi-stage pipeline through the cooperation of the image processing accelerator 400 and the multi-core task processor 500, the speed of the signal processing is improved, and the accurate identification and positioning of the target object can be realized.

[0030] As shown in Figure 1 some embodiments, the high-bandwidth signal processing system further comprises a communication interface 700, which is electrically connected with the multi-core task processor 500. The communication interface 700 is a wireless communication interface, which is used to complete the frame packaging function and the transmission of data content. After the multi-core task processor 500 obtains the real-time processing result of the data, the result can be sent to the server or the client through the communication interface 700.

[0031] As shown in Figure 2 some embodiments, the image processing accelerator 400 comprises a data interface 410, an image segmentation module 420, a target data processing module 430, an image resolution truncation module 440, a background data processing module 450, an image encoding compression module 460, a visual processing module 470, and a feedback module 480. The data interface 410 is used to restore the multi-channel serial data into two-dimensional image information; the image segmentation module 420 is used to perform image segmentation on the two-dimensional image information to obtain an image block containing a target object; the target data processing module 430 is used to perform first preprocessing on the image block to obtain first image data; the image resolution truncation module 440 is used to perform resolution truncation on the two-dimensional image information to obtain image information containing only background data; the background data processing module 450 is used to perform second preprocessing on the image information to obtain second image data; the image encoding compression module 460 is used to perform encoding compression on the first image data and the second image data to obtain third image data; the visual processing module 470 is used to perform data processing in the form of parallel multi-stage pipeline according to the third image data to realize the identification and positioning of the target object; and the feedback module 480 is used to send the data processing result of the visual processing module 470 as feedback information to the image segmentation module 420 and the image resolution truncation module 440.

[0032] Specifically, the data interface 410 restores the multi-channel serial data sent by the image block module 200 into original two-dimensional image information based on a serial-parallel conversion structure, and sends the two-dimensional image information to the image segmentation module 420 and the image resolution truncation module 440 respectively.

[0033] The image segmentation module 420 converts the actual position of the target object into the corresponding block address in the two-dimensional image information and segments the image to only keep the image block 800 containing the target object according to the actual position of the target object. The image segmentation module 420 segments at a high resolution. As shown in Figure 3 The image block 800 containing the target object only occupies a small part of the actual image obtained by the camera 100, so the image segmentation module 420 is needed to segment this part of the image to reduce the data amount of image processing. Subsequently, the image segmentation module 420 sends the image block 800 to the target data processing module 430 for first preprocessing, which includes but is not limited to linear corresponding operations such as filtering, scaling, translation, rotation, etc. on the image; and sends the first image data obtained after the first preprocessing to the image encoding and compression module 460.

[0034] The image resolution truncation module 440 only keeps the image information containing the background data (i.e. not including the target object) after obtaining the two-dimensional image information and performs resolution truncation on the image information, taking only 8 bits of the original RGB image as the background image information, so as to input the low-resolution image to the background data processing module 450, thereby reducing the amount of data to be actually transmitted by reducing the resolution. The background data processing module 450 performs second preprocessing on the image information, which includes but is not limited to linear corresponding operations such as filtering, scaling, translation, rotation, etc. on the image, and sends the second image data obtained after the second preprocessing to the image encoding and compression module 460.

[0035] The image encoding and compression module 460 obtains the first image data and the second image data, adopts an image compression algorithm, and compresses the image data from a bit stream into a JPEG format in a parallel manner, thereby reducing the data operation amount, and inputs the compressed image to the visual processing module 470 to complete the processing of the image.

[0036] The visual processing module 470 processes the data in a parallel multi-stage pipeline manner under the control of the multi-core task processor 500, the input data of which is the compressed JPEG image, and obtains a suitable operation parameter model after local training, and the output information of which includes the position information of the target object and the spatial position information, motion state information, etc. of the current system. As shown in Figure 4The pipeline processing structure of the visual processing module 470 is shown, taking three processing tasks as an example, and using the advantages of the multi-core to complete the tasks that need to be cached in the pipeline; in the pipeline processing, the storage scheduling is performed by the CPU in the multi-core task processor 500 to meet the cache requirement in the pipeline task and ensure that the data processing is not blocked. At the same time, the data processing result of the visual processing module 470 is also used as feedback information and is input to the image segmentation module 420 and the image resolution truncation module 430 through the feedback module 480, so that the position of the target is located when the next data information is acquired, and is provided as a parameter to the image segmentation module 420 and the image resolution truncation module 430, thereby improving the accuracy of the operation.

[0037] In some embodiments, the multi-core task processor 500 and the image processing accelerator 400 are in a heterogeneous structure, which can reduce the hardware interconnection between chips and effectively reduce the development difficulty of the design.

[0038] In some embodiments, the image processing accelerator 400 and the storage module 600 are directly connected on a PCB, thereby providing a high-speed connection mode at the system PCB level and effectively improving the operation speed.

[0039] According to the high-bandwidth signal processing system in the embodiment of the present application, the camera 100 serves as an image sensor to generate a high-resolution data stream, and the data stream generated by the motion sensor 300 serves as a frame signal input to the image processing accelerator 400. The image data is transmitted to the image coding and compression module 460 after image segmentation preprocessing and image resolution truncation preprocessing to complete data compression, and then is transmitted to the visual processing module 470 in the pipeline structure to complete data operation and processing. In the embodiment of the present application, the heterogeneous system of FPGA+AMR is adopted to reduce the interconnection structure, and the multi-core scheduling task mechanism is adopted to complete the pipeline task by segmentation and task allocation, thereby improving the operation speed.

[0040] On the other hand, the present application also provides an electronic device including the high-bandwidth signal processing system described above. The electronic device can be a flight recorder or other common electronic device.

[0041] On the other hand, as shown in Figure 5 The present application also provides a signal processing method, which is adapted to the high-bandwidth signal processing system described above and includes the following steps:

[0042] Step S100: acquiring two-dimensional image information containing a target object.

[0043] Specifically, a high-precision, high-resolution high-speed camera can be used to shoot images, thereby generating corresponding two-dimensional image information. The camera 100 has a resolution of 1080p or above. After the camera 100 shoots the images, the data is output to the image blocking module 200 in the storage format of two-dimensional image information and in a high-speed serial manner. The image blocking module 200 blocks the two-dimensional image information sent by the camera 100 and sends serial data to the image processing accelerator 400 in a multi-channel parallel transmission mode. The image processing accelerator 400 restores the multi-channel serial data to the original two-dimensional image information by means of the data interface 410.

[0044] Step S200: Obtain position information and motion state information of the high-bandwidth signal processing system.

[0045] Specifically, the motion sensor 300 is used to obtain the position information and motion state information of the high-bandwidth signal processing system, and send them to the image processing accelerator 400.

[0046] Step S300: Perform data processing in a parallel multi-stage pipeline manner according to the two-dimensional image information, the position information and the motion state information, to realize recognition and positioning of the target object.

[0047] Specifically, after the image processing accelerator 400 obtains the two-dimensional image information sent by the image blocking module 200 and the position information and motion state information sent by the motion sensor 300, it performs data processing in a multi-core multi-stage pipeline manner with the assistance of the multi-core task processor 500 and the storage module 600, to complete recognition and positioning of the target object.

[0048] The specific data processing process of the image processing accelerator 400 includes the following steps:

[0049] Step S401: Perform image segmentation on the two-dimensional image information to obtain an image block containing the target object;

[0050] Step S402: Perform first preprocessing on the image block to obtain first image data;

[0051] Step S403: Perform resolution truncation on the two-dimensional image information to obtain image information containing only background data;

[0052] Step S404: Perform second preprocessing on the image information to obtain second image data;

[0053] Step S405: Perform encoding compression on the first image data and the second image data to obtain third image data;

[0054] Step S406: In a parallel multi-stage pipeline manner, the third image data, the position information and the motion state information are processed to realize the recognition and positioning of the target object.

[0055] Specifically, the data interface 410 restores the multi-channel serial data sent by the image block module 200 into original two-dimensional image information based on a serial-parallel conversion structure, and sends the two-dimensional image information to the image segmentation module 420 and the image resolution truncation module 440 respectively.

[0056] The image segmentation module 420 converts the actual position of the target object into a corresponding block address in the two-dimensional image information, and segments the image to only keep the image block 800 containing the target object. The image segmentation module 420 segments at a high resolution, and the segmentation size is generally 8 times or more. As shown in the figure, the image block 800 containing the target object only occupies a small part of the actual image obtained by the camera 100, so the image segmentation module 420 is needed to segment this part of the image to reduce the data amount of image processing. Subsequently, the image segmentation module 420 sends the image block 800 to the target data processing module 430 for first preprocessing, and the first preprocessing includes but is not limited to linear corresponding operations such as filtering, scaling, translation, rotation, etc. on the image; the image segmentation module 420 sends the first image data obtained after the first preprocessing to the image encoding and compression module 460. Figure 3 The image resolution truncation module 440 only keeps the image information containing the background data (i.e. not including the target object) after obtaining the two-dimensional image information, and performs resolution truncation on the image information. The original RGB image is only taken as 8 bits as background image information, so that the low-resolution image is input to the background data processing module 450, and the data amount of actual transmission is reduced by reducing the resolution. The background data processing module 450 performs second preprocessing on the image information, and the second preprocessing includes but is not limited to linear corresponding operations such as filtering, scaling, translation, rotation, etc. on the image, and sends the second image data obtained after the second preprocessing to the image encoding and compression module 460.

[0057] The image encoding and compression module 460 obtains the first image data and the second image data, adopts an image compression algorithm, and compresses the image data from a bit stream form into a JPEG format in a parallel manner, so as to reduce the data operation amount, and inputs the compressed image to the visual processing module 470 to complete the processing of the image.

[0058]

[0059] ​The visual processing module 470 processes data in a parallel multi-stage pipeline manner under the control of the multi-core task processor 500, the input data of which is the compressed JPEG image, and after the local training, the appropriate operation parameter model is obtained, and the output information includes the position information of the target object and the spatial position information, motion state information, etc. of the current system. As shown in Figure 4 The pipeline processing structure of the visual processing module 470 is shown, and three processing tasks are taken as an example to complete the cache task in the pipeline task by using the advantages of the multi-core; in the pipeline processing, the storage scheduling is performed by the CPU in the multi-core task processor 500 to meet the cache requirement in the pipeline task and ensure the non-jamming of data processing. At the same time, the data processing result of the visual processing module 470 is also used as feedback information and is input to the image segmentation module 420 and the image resolution truncation module 430 through the feedback module 480, so that the position positioning of the target is completed when the next data information is acquired, and is provided as a parameter to the image segmentation module 420 and the image resolution truncation module 430, thereby improving the operation accuracy.

[0060] According to the signal processing method of the embodiment of the present application, through the cooperation of the camera 100 and the motion sensor 300, the result of signal processing can be appropriately calibrated from different dimensions in signal processing to improve the detection accuracy; through the cooperation of the image processing accelerator 400 and the multi-core task processor 500, the data processing can be completed in the form of a parallel multi-stage pipeline, the speed of signal processing is improved, and accurate recognition and positioning of the target object can be realized.

[0061] On the other hand, the present application also provides a computer readable storage medium, which stores a program, and the program is executed by a processor to realize the above-mentioned signal processing method.

[0062] Although specific embodiments are described herein, one of ordinary skill in the art will recognize that many other modifications or alternative embodiments can be within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Additionally, while various example implementations and architectures have been described in accordance with embodiments of the present disclosure, one of ordinary skill in the art will recognize that many other modifications to the example implementations and architectures described herein are within the scope of the present disclosure.

[0063] Certain aspects of the disclosure are described above with reference to block and flow diagrams of systems, methods, system and / or computer program products according to exemplary embodiments. It will be understood that one or more of the blocks of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and flow diagrams, can be implemented by

[0064] Accordingly, the blocks in the block diagrams and flow diagrams support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and flow diagrams, can be implemented by dedicated hardware-based computer systems which perform the specified functions or combinations of special-purpose hardware and computer instructions.

[0065] The program modules, applications, and the like described herein can include one or more software components, including, for example, software objects, methods, data structures, and the like. Each such software component can include computer-executable instructions that, in response to execution by a computer, cause at least a portion of the functionality described herein (e.g., one or more operations of the example methods described herein) to be performed.

[0066] Software components can be coded in any of a variety of programming languages. One illustrative programming language can be a low-level programming language, such as an assembly language associated with a particular hardware architecture and / or operating system platform. Software components including assembly language instructions can need to be translated via an assembler before execution by the hardware architecture and / or platform. Another illustrative programming language can be a higher-level programming language that can be portable across multiple architectures. Software components including a higher-level programming language can need to be translated via an interpreter or compiler before execution. Other examples of programming languages include, but are not limited to, a macro-language, a shell or command language, a job control language, a script language, a database query or search language, or a report writing language. In one or more example embodiments, a software component including instructions in one of the above-described examples of programming languages can be executed directly by an operating system or other software component without first being converted to another form.

[0067] Software components can be stored as files or other data storage constructs. Software components of a similar type or related function can be stored together in a particular directory, folder, or library, for example. Software components can be static (e.g., pre-set or fixed) or dynamic (e.g., created or modified at execution time).

[0068] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.

Claims

1. A high-bandwidth signal processing system, characterized in that, include: A camera is used to capture images and generate corresponding two-dimensional image information. The image segmentation module is used to segment the two-dimensional image information into blocks to form multi-channel serial data; A motion sensor is used to acquire the position and motion state information of the high-bandwidth signal processing system. An image processing accelerator is used to acquire data sent by the image segmentation module and the motion sensor, and to process the data in a parallel multi-stage pipeline manner to achieve the identification and localization of the target object. A multi-core task processor is used to allocate and schedule tasks for the data processing process of the image processing accelerator, and to obtain the data processing results of the image processing accelerator. A storage module is used to provide data caching functionality for the image processing accelerator and to provide a training set for the image processing accelerator; The image processing accelerator includes: A data interface is used to restore the multi-channel serial data into the two-dimensional image information; The image segmentation module is used to segment the two-dimensional image information to obtain image blocks containing the target object; The target data processing module is used to perform a first preprocessing on the image block to obtain first image data; An image resolution truncation module is used to truncate the resolution of the two-dimensional image information to obtain image information containing only background data. The background data processing module is used to perform a second preprocessing on the image information to obtain second image data; An image encoding and compression module is used to encode and compress the first image data and the second image data to obtain the third image data; The vision processing module is used to process the third image data in a parallel multi-stage pipeline manner to achieve the identification and localization of the target object. The feedback module is used to send the data processing results of the vision processing module as feedback information to the image segmentation module and the image resolution truncation module.

2. The high-bandwidth signal processing system according to claim 1, characterized in that, It also includes a communication interface, which is electrically connected to the multi-core task processor.

3. The high-bandwidth signal processing system according to claim 1, characterized in that, The image processing accelerator and the storage module are directly connected on a single PCB.

4. The high-bandwidth signal processing system according to claim 1, characterized in that, The image processing accelerator and the multi-core task processor are heterogeneous structures.

5. An electronic device, characterized in that, Includes the high-bandwidth signal processing system as described in any one of claims 1 to 4.

6. A signal processing method, characterized in that, include: Obtain two-dimensional image information containing the target object; The two-dimensional image information is divided into blocks to form multi-channel serial data; The serial data is converted from serial to parallel to restore the two-dimensional image information; Acquire position and motion status information of a high-bandwidth signal processing system; Based on the two-dimensional image information, the position information, and the motion state information, data processing is performed in a parallel multi-stage pipeline manner to achieve the identification and localization of the target object; The step of processing data in a parallel, multi-stage pipeline manner based on the two-dimensional image information, the position information, and the motion state information to achieve the identification and localization of the target object includes the following steps: The two-dimensional image information is segmented to obtain image blocks containing the target object; The image block is subjected to a first preprocessing step to obtain first image data; The resolution of the two-dimensional image information is truncated to obtain image information containing only background data; The image information is subjected to a second preprocessing step to obtain second image data; The first image data and the second image data are encoded and compressed to obtain the third image data; The third image data, the position information, and the motion state information are processed in a parallel, multi-stage pipeline manner to achieve the identification and localization of the target object.

7. A computer-readable storage medium storing a program, characterized in that, When the program is executed by the processor, it implements the signal processing method of claim 6.

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