Storage device and control method of storage device

Abstract

Embodiments provide a storage device and a control method of a storage device that improve the quality of the storage device. The storage device of the embodiments includes: first and second stacked bodies (700) arranged in a second direction parallel to a surface of a substrate (80) and each including a first semiconductor layer (70) arranged in a first direction perpendicular to the surface of the substrate (80); a word line (50) covering the stacked bodies (700); second and third semiconductor layers (300a) each disposed above the first and second stacked bodies (700) in the first direction; a memory cell (MC) disposed between the first semiconductor layer (70) and the word line (50); a first transistor (TRn) on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacked bodies (700) are arranged in the second direction at a first pitch (Da), the first and second semiconductor layers (300a) are arranged in the second direction at a second pitch (D1), and the second pitch (D1) is equal to the first pitch (Da).

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2021-015252 (Filing date: February 2, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a storage device. BACKGROUND

[0004] A storage device having an array of storage cells in a three-dimensional structure is known.

[0005] The structure of a storage device and the operation characteristics of a storage device are being improved. SUMMARY

[0006] The problem to be solved by the present application is to provide a storage device and a control method of a storage device that improve the quality of a storage device.

[0007] The storage device of an embodiment includes: a substrate; first and second laminated bodies arranged in a second direction parallel to a surface of the substrate and each including a plurality of first semiconductor layers arranged in a first direction perpendicular to the surface of the substrate; a plurality of word lines covering the first and second laminated bodies; a second semiconductor layer disposed above the first laminated body in the first direction; a third semiconductor layer disposed above the second laminated body in the first direction; a plurality of storage cells each disposed between the plurality of first semiconductor layers and the plurality of word lines; a first transistor disposed on the second semiconductor layer; and a second transistor disposed on the third semiconductor layer; the first and second laminated bodies are arranged at a first pitch in the second direction, the first and second semiconductor layers are arranged at a second pitch in the second direction, and the second pitch is equal to the first pitch. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a storage system including the storage device of the first embodiment.

[0009] Figure 2 is a bird's-eye view of an array of storage cells of the storage device of the first embodiment.

[0010] Figure 3 is a plan view of an array of storage cells of the storage device of the first embodiment.

[0011] Figure 4 and Figure 5 is a cross-sectional view of an array of storage cells of the storage device of the first embodiment.

[0012] Figure 6 is a circuit diagram of the memory cell array of the memory device of Embodiment 1.

[0013] Figure 7 and Figure 8 is a schematic diagram showing a configuration example of the memory device of Embodiment 1.

[0014] Figure 9 is a top view showing a configuration example of the memory device of Embodiment 1.

[0015] Figure 10 and Figure 11 is a sectional view showing a configuration example of the memory device of Embodiment 1.

[0016] Figure 12 is a circuit diagram showing a first example of the configuration of the memory device of Embodiment 1.

[0017] Figure 13 is a top view showing a first example of the configuration of the memory device of Embodiment 1.

[0018] Figure 14 is a sectional view showing a first example of the configuration of the memory device of Embodiment 1.

[0019] Figure 15 is a sectional view showing a second example of the configuration of the memory device of Embodiment 1.

[0020] Figure 16 is a circuit diagram showing a third example of the configuration of the memory device of Embodiment 1.

[0021] Figure 17 and Figure 18 is a sectional view showing a third example of the configuration of the memory device of Embodiment 1.

[0022] Figure 19 is a sectional view showing a modification example of the configuration of the memory device of Embodiment 1.

[0023] Figure 20 is a sectional view showing a modification example of the configuration of the memory device of Embodiment 1.

[0024] Figure 21 is a top view showing one step of the manufacturing method of the memory device of Embodiment 1.

[0025] Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 is a sectional view showing one step of the manufacturing method of the memory device of Embodiment 1.

[0026] Figure 27 is a plan view showing one step of the manufacturing method of the storage device of the first embodiment.

[0027] Figure 28 Figure 29 Figure 30 Figure 31 is a sectional view showing one step of the manufacturing method of the storage device of the first embodiment.

[0028] Figure 32 is a graph showing an example of the relationship between the threshold voltage of the storage unit and data.

[0029] Figure 33 is a graph showing a configuration example of the storage device of the second embodiment.

[0030] Figure 34 is a flowchart showing an example of the operation of the storage device of the second embodiment.

[0031] Figure 35 Figure 36 (a), Figure 36 (b), Figure 37 (a) to Figure 37 (c), Figure 38 and Figure 39 are graphs for explaining an example of the operation of the storage device of the second embodiment.

[0032] Figure 40 is a flowchart showing an example of the operation of the storage device of the second embodiment.

[0033] Figure 41 is a graph for explaining an example of the operation of the storage device of the second embodiment.

[0034] Figure 42 is a flowchart showing an example of the operation of the storage device of the second embodiment.

[0035] Figure 43 and Figure 44 (a) to Figure 44 (d) are graphs for explaining an example of the operation of the storage device of the second embodiment.

[0036] Figure 45 is a flowchart showing an example of the operation of the storage device of the second embodiment.

[0037] Figure 46 (a), Figure 46 (b), and Figure 47 are graphs for explaining an example of the operation of the storage device of the second embodiment.

[0038] Figure 48 ​​​​is a flowchart showing an example of an operation of the storage device of the second embodiment.

[0039] Figure 49 (a) and (b) are diagrams for explaining an example of an operation of the storage device of the second embodiment. DETAILED DESCRIPTION

[0040] Reference Figures 1 to 49 The storage device of the embodiment will be described.

[0041] The present embodiment will be described in detail below with reference to the drawings. In the following description, the same reference numerals are assigned to elements having the same function and configuration.

[0042] In addition, in each of the following embodiments, elements (for example, circuits, wiring, various voltages and signals, and the like) to which reference symbols with numerals / letters at the end are assigned to be distinguished from each other are written using reference symbols from which the numerals / letters at the end are omitted, in a case where they do not need to be distinguished from each other.

[0043] [Embodiment]

[0044] (1) First Embodiment

[0045] Reference Figures 1 to 31 The storage device of the first embodiment will be described.

[0046] (a1) Configuration Example

[0047] Reference Figures 1 to 20 The configuration example of the storage device of the first embodiment will be described.

[0048] Figure 1 is a block diagram for explaining the configuration example of the storage device of the present embodiment.

[0049] As shown in Figure 1 , the storage device 1 of the present embodiment is electrically combined with a storage controller 2.

[0050] The storage controller 2 transmits an instruction CMD, an address ADD, and a plurality of control signals to the storage device 1 of the present embodiment.

[0051] The storage device 1 receives the instruction CMD, the address ADD, and the plurality of control signals. Data DAT is transmitted between the storage device 1 and the storage controller 2. Hereinafter, data DAT transmitted from the storage controller 2 to the storage device 1 at the time of execution of a write operation is referred to as write data. The write data DAT is written into the storage device 1. Data DAT transmitted from the storage device 1 to the storage controller 2 at the time of execution of a read operation is referred to as read data. The read data DAT is read from the storage device 1.

[0052] The storage device 1 of the present embodiment includes, for example, a memory cell array 100, an instruction register 110, an address register 120, a row control circuit 140, a sense amplifier 150, a drive circuit 160, and a sequencer 190.

[0053] The memory cell array 100 stores data. The memory cell array 100 is provided with a plurality of bit lines and a plurality of word lines therein. The memory cell array 100 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is a collection of a plurality of memory cells. Each memory cell is associated with one bit line and one word line. The memory cell array 100 includes a plurality of selection gate lines for selecting a control unit in the memory cell array 100.

[0054] The memory cell array 100 is configured as described below.

[0055] The instruction register 110 holds an instruction CMD from the storage controller 2. The instruction CMD includes, for example, a command for causing the sequencer 190 to perform a readout operation, a write operation, and a deletion operation.

[0056] The address register 120 holds address information (selection address) ADD from the storage controller 2. The address information ADD includes, for example, a block address, a page address, and a column address. The address information ADD, for example, the block address, the page address, and the column address, are used for selection of a block BLK, a word line, a bit line, and a selection gate line, respectively. Hereinafter, a block selected based on the block address is referred to as a selection block. A word line selected based on the page address is referred to as a selection word line.

[0057] The row control circuit 140 controls an operation related to a row of the memory cell array 100. The row control circuit 140 selects one block BLK from the memory cell array 100 based on a block address in the address register 120. The row control circuit 140, for example, transmits a voltage applied to a wire corresponding to the selection word line to the selection word line in the selection block BLK. The row control circuit 140 controls selection and non-selection of the selection gate line based on the address information ADD.

[0058] The row control circuit 140 includes a word line decoder 141 and a selection gate line decoder 142, and the like.

[0059] The sense amplifier 150 controls an operation related to a column of the memory cell array 100. The sense amplifier 150 applies a voltage to each bit line BL provided in the memory cell array 100 according to write data DAT from the storage controller 2 in a write operation. The sense amplifier 150 determines data stored in a memory cell MC based on a potential of the bit line BL (or presence or absence of a current) in a readout operation. The sense amplifier 150 transmits data based on the determination result to the storage controller 2 as readout data.

[0060] The sense amplifier 150 includes a bit line selection circuit 151 and / or an amplification circuit 152, etc.

[0061] The drive circuit 160 outputs a voltage to be used in a read operation, a write operation, an erase operation, etc. of the memory cell array 100. The drive circuit 160 applies a specified voltage to a wiring corresponding to a word line, a bit line, etc. based on an address in the address register 120.

[0062] The sequencer 190 controls the operation of the entire memory device 1. For example, the sequencer 190 controls each circuit based on a command CMD in the command register 110.

[0063] For example, the memory device 1 of the present embodiment is a NAND flash memory. The communication between the NAND flash memory (hereinafter, simply referred to as a flash memory) 1 and the memory controller 2 conforms to a NAND interface standard. A command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal IO, etc. are used for the communication between the flash memory 1 and the memory controller 2.

[0064] The command latch enable signal CLE is a signal indicating that the input / output signal IO received by the flash memory 1 is a command CMD. The address latch enable signal ALE is a signal indicating that the signal IO received by the flash memory 1 is address information ADD. The write enable signal WEn is a signal instructing the flash memory 1 to perform the input of the input / output signal IO. The read enable signal REn is a signal instructing the flash memory 1 to perform the output of the input / output signal IO.

[0065] The ready / busy signal RBn is a signal notifying the memory controller 2 of whether the flash memory 1 is in a ready state in which the command (an instruction or a request) from the memory controller 2 can be accepted, or in a busy state in which the command cannot be accepted.

[0066] The input / output signal IO is, for example, a signal of 8 bits in width. The input / output signal IO can include a command CMD, address information ADD, data DAT, etc.

[0067] The flash memory 1 can also include an input / output circuit (not shown) and a voltage generation circuit (not shown), etc. The input / output circuit functions as an interface circuit on the flash memory 1 side between the flash memory 1 and the memory controller 2. The voltage generation circuit generates a plurality of voltages to be used in various operations of the flash memory 1.

[0068] Hereinafter, each of the plurality of circuits 110, 120, 140, 150, 160, 190 in the flash memory 1 other than the memory cell array 100, or a set (a circuit group) of them is referred to as a peripheral circuit (or a control circuit).

[0069] <Memory Cell Array>

[0070] Reference Figures 2 to 5 Here, an example of the structure of the storage cell array of the flash memory in this embodiment will be described.

[0071] Figures 2 to 5 The image shows a portion of the memory cell array of the flash memory according to this embodiment.

[0072] Figure 2 This is a bird's-eye view showing an example of the structure of the memory cell array of the flash memory in this embodiment. Figure 3 This is a top view showing a structural example of the storage cell array of the flash memory in this embodiment. Figure 4 and Figure 5 This is a cross-sectional view showing a structural example of the storage cell array of the flash memory in this embodiment. Figure 4 It is along Figure 3 A cross-sectional view along line AA. Figure 5 It is along Figure 3 A cross-sectional view of the BB line.

[0073] In the flash memory 1 of this embodiment, the storage cell array 100 has a three-dimensional structure.

[0074] like Figures 2 to 5 As shown, a memory cell array 100 is disposed above a substrate 80. Multiple memory cells MC are arranged in a three-dimensional configuration within the memory cell array 100. The multiple memory cells MC are arranged along directions parallel to the upper surface of the substrate 80 (X and Y directions). The multiple memory cells MC are also arranged along a direction perpendicular to the upper surface of the substrate 80 (Z direction).

[0075] The memory cell array 100 includes a plurality of stacked layers 700. The plurality of stacked layers 700 are disposed on an insulating layer 81 covering the substrate 80.

[0076] Each stack 700 comprises a plurality of semiconductor layers 70 and a plurality of insulating layers 71. Each semiconductor layer 70 has a columnar (e.g., prismatic) structure extending along the Y direction. Each insulating layer 71 has a columnar (e.g., prismatic) structure extending along the Y direction.

[0077] Within the laminate 700, multiple semiconductor layers 70 and multiple insulating layers 71 are alternately laminated in the Z direction. Each semiconductor layer 70 is disposed between two insulating layers 71 in the Z direction. Within each laminate 700, the multiple semiconductor layers 70 are arranged along the Z direction.

[0078] The plurality of conductive layers 50, 50D, 50S are provided on the plurality of stacks 700. The plurality of conductive layers 50, 50D, 50S cover the side surfaces (surfaces intersecting the X direction) of the respective stacks 700 and the upper surfaces (surfaces intersecting the Z direction) of the respective stacks 700.

[0079] The plurality of conductive layers 50, 50D, 50S face the side surfaces of the stacks 700 in the X direction. The plurality of conductive layers 50, 50D, 50S are provided between the stacks 700 adjacent in the X direction. Each of the conductive layers 50, 50D, 50S extends in the X direction and the Z direction.

[0080] The conductive layer 50D is provided on the one end side in the Y direction of the stack 700. The conductive layer 50D functions as a drain side select gate line SGD.

[0081] The conductive layer 50S is provided on the other end side in the Y direction of the stack 700. The conductive layer 50S functions as a source side select gate line SGS.

[0082] The plurality of conductive layers 50 are provided in the region between the conductive layer 50D and the conductive layer 50S. Each of the conductive layers 50 functions as a word line WL.

[0083] The plurality of storage layers 51 are each provided between each of the conductive layers 50, 50D, 50D and each of the stacks 700. The plurality of storage layers 51 are provided on the side surfaces of the stacks 700 and on the upper surfaces of the stacks 700. Each of the storage layers 51 faces the side surfaces of the stacks 700. Each of the storage layers 51 extends in the X direction and the Z direction.

[0084] The storage layer 51 includes an insulating layer 511, a charge storage layer 512, and an insulating layer 513.

[0085] The charge storage layer 512 is provided between the two insulating layers 511, 513. The charge storage layer 512 is capable of storing charges in the layer. For example, the charge storage layer 512 is a layer having a charge trap energy level. An example of the material of the charge storage layer 512 is silicon nitride.

[0086] The insulating layer 511 is provided between the stack 700 and the charge storage layer 512. The insulating layer 511 functions as a tunnel film between the semiconductor layer 70 and the charge storage layer 512. Hereinafter, the insulating layer 511 is referred to as a tunnel insulating film.

[0087] The insulating layer 513 is provided between the conductive layer 50, 50D, 50S and the charge storage layer 512. The insulating layer 513 blocks the movement of charges between the charge storage layer 512 and the conductive layer 50. Hereinafter, the insulating layer 513 is referred to as a blocking insulating film.

[0088] The portion between the semiconductor layer 70 and the conductive layer 50 sandwiching the storage layer 51 functions as a storage cell MC.

[0089] In addition, the memory layer may also have a floating gate structure formed by conductors broken along the Z direction. The material of the memory layer in the floating gate structure is silicon, metal, or silicide, etc.

[0090] Thus, the memory cell MC is disposed in the portion (region) between the semiconductor layer 70 and the conductive layer 50.

[0091] The portion between the semiconductor layer 70 and the conductive layer 50D functions as the drain-side selection transistor ST1.

[0092] The portion between the semiconductor layer 70 and the conductive layer 50S functions as the source-side selection transistor ST2.

[0093] like Figure 3 As shown, the laminate 710 is disposed on the substrate 80 at one end of the laminate 700 in the Y direction.

[0094] The stack 710 is connected to one end of the stack 700. The stack 710 includes a plurality of semiconductor layers 70A and a plurality of insulating layers 71A. The semiconductor layers 70A have a columnar (e.g., prismatic) structure extending along the X direction. The insulating layers 71A have a columnar (e.g., prismatic) structure extending along the X direction.

[0095] Multiple semiconductor layers 70A and multiple insulating layers 71A are alternately deposited in the Z direction. Within the stacked body 710, the multiple semiconductor layers 70A are arranged along the Z direction.

[0096] Semiconductor layer 70A is continuous with semiconductor layer 70. Insulating layer 71A is continuous with insulating layer 71.

[0097] The laminate 710 extends along the X direction. One end of the laminate 710 in the X direction has a stepped structure. Hereinafter, the laminate 710 is referred to as the stepped structure.

[0098] At one end of the stepped structure 710 in the X direction, the upper surface of the lower semiconductor layer 70A is exposed and is not covered by the upper semiconductor layer 70A.

[0099] Multiple bit lines BL are configured above the stack bodies 700 and 710 in the Z direction. Each bit line BL extends along the Y direction.

[0100] Bit line BL is connected to semiconductor layers 70 and 70A via bit line contact CB.

[0101] One of the plurality of bit line contacts CB is provided on an upper surface of the corresponding one of the plurality of semiconductor layers 70A exposed in the stepped structure 710.

[0102] Each bit line BL is connected to the corresponding one of the plurality of bit line contacts CB. Thus, each bit line BL is connected to the corresponding one of the plurality of semiconductor layers 70 in the stacked body 700.

[0103] The plurality of conductive layers 55 is provided on the stacked body 700 in a region between the stepped structure 710 and the conductive layer 50D. The plurality of conductive layers 55 is each provided on the corresponding one of the stacked bodies 700. The plurality of conductive layers 55 is each independent in each stacked body 700.

[0104] Each conductive layer 55 covers the side surface and the upper surface of the corresponding stacked body 700.

[0105] For example, the layer 51A is provided between the conductive layer 55 and the stacked body 700. The layer 51A includes the same components 511, 512, 513 as the storage layer 51.

[0106] The portion between the conductive layer 55 and the semiconductor layer 70 functions as a transistor (hereinafter, referred to as an access transistor) AT.

[0107] The conductive layer 55 functions as a wiring (hereinafter, referred to as a string selection line) SSL for controlling connection between the stacked body 700 and the stepped structure.

[0108] The access transistor AT is turned on or off by potential control of the string selection line SSL. Thus, any one of the plurality of stacked bodies 700 is electrically connected to the stepped structure 710.

[0109] Figure 6 is a circuit diagram showing a circuit configuration of a memory cell array of a flash memory according to the present embodiment.

[0110] Figures 2 to 5 The memory cell array 100 described in the above has Figure 6 a circuit configuration of the above. In a NAND type flash memory, the memory cell array 100 includes a plurality of NAND strings NS.

[0111] Each NAND string NS includes a plurality of memory cells MC and selection transistors ST1, ST2. The memory cells MC are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

[0112] The memory cell MC can nonvolatilely store data. The memory cell (hereinafter, also referred to as a memory cell transistor) MC is a field effect transistor having a control gate and a charge storage layer.

[0113] In Figures 2 to 5 In the structure, 1 NAND string NS includes a plurality of memory cells MC and a plurality of selection transistors ST1, ST2 formed using 1 semiconductor layer.

[0114] In the plurality of control units within the block BLK, the gates of the respective selection transistors ST1 are connected to corresponding selection gate lines SGD (SGD0,..., SGDn-1), respectively. Similarly, in the plurality of control units (selection units) within the block BLK, the gates of the respective selection transistors ST2 are commonly connected to selection gate lines SGS (SGS0,..., SGSn-1), for example.

[0115] The control gates of the memory cells MC belonging to the same block BLK are connected to corresponding word lines WL, respectively.

[0116] The drains of the selection transistors ST1 of each NAND string NS are connected to corresponding 1 bit line BL via an access transistor AT. The bit lines BL are commonly connected to the NAND strings NS belonging to the same column among the plurality of blocks BLK.

[0117] The sources of the plurality of selection transistors ST2 are commonly connected to a source line SL.

[0118] A string selection line SSL is provided within the memory cell array in each control unit. Hereinafter, the control unit selected by the string selection line SSL is referred to as a string unit.

[0119] The gate of the access transistor AT is connected to corresponding 1 string selection line SSL among the plurality of string selection lines SSL. One of the source / drain of the access transistor AT is connected to the drain of the selection transistor ST1 of the corresponding NAND string NS. The other of the source / drain of the access transistor AT is connected to the drain of the selection transistor ST1 of the corresponding NAND string NS.

[0120] Hereinafter, within the block BLK, the control unit selected by the drain side selection gate line SGD is also referred to as a sub-block SB.

[0121] The writing of data and the reading of data are performed uniformly for the plurality of memory cells connected to the common word line within 1 string unit SU belonging to 1 sub-block SB in the block BLK based on the address information. The unit of the plurality of selection units selected at the time of writing and reading data is referred to as a unit group CU.

[0122] The number of blocks within the memory cell array 100, the number of string units within the block BLK, and the number of NAND strings within the string unit SU are arbitrary.

[0123] In the flash memory 1 of the present embodiment, the peripheral circuit is provided above the memory cell array 100 in the Z direction.

[0124] Figure 7 is a schematic view showing a region of the flash memory of the present embodiment in which a peripheral circuit is provided.

[0125] As shown in Figure 7 , a region in which elements constituting a peripheral circuit (hereinafter, referred to as a peripheral circuit region) 200 is provided above the memory cell array 100 in the Z direction.

[0126] The peripheral circuit region 200 contains a plurality of transistors TR.

[0127] The plurality of transistors TR are arranged above the memory cell array 100 in the Z direction. The peripheral circuit contains the plurality of transistors TR. The transistors TR in the peripheral circuit region 200 are used for a selection circuit (for example, a selection gate line decoder) 142 and the like of a wiring in the memory cell array 100.

[0128] The transistors TR in the peripheral circuit region 200 are thin film transistors (TFTs). Hereinafter, the peripheral circuit region 200 is also referred to as a TFT region.

[0129] The structure of the transistor TR is described below.

[0130] An element (for example, a transistor) TRx of the peripheral circuit can also be provided in a semiconductor region of the substrate (semiconductor substrate) 80.

[0131] For example, the peripheral circuit region 800 is provided in a region adjacent to the memory cell array 100 in the X direction and / or the Y direction.

[0132] The transistor TRx is provided in the peripheral circuit region 800. The semiconductor region in which the transistor TRx is arranged is surrounded by an element separation layer (insulating layer) 89.

[0133] The gate electrode 85 of the transistor TRx is provided on the upper surface of the substrate 80 with the gate insulating layer (not shown) interposed. The two source / drain electrodes 82, 83 of the transistor TRx are provided inside the substrate 80.

[0134] The transistor TRx that operates using a relatively high voltage (for example, 8 V or more) as in the word line decoder 141 and the transistor in the drive circuit 160 is provided in the peripheral circuit region 800. Thus, the transistor TRx can ensure a relatively high gate withstand voltage. For example, the voltage applied to the transistor TRx is higher than the voltage applied to the transistor TR.

[0135] Thus, a circuit that operates using a relatively high voltage than the circuit in the TFT region 200 is arranged on the semiconductor region in the substrate 80. Thus, the flash memory 1 of the present embodiment can perform a desired operation without causing deterioration of the operation characteristics.

[0136] Figure 8 is a modification example of Figure 7

[0137] The memory cell array 100 is sometimes arranged in the trench 88 of the substrate 80. In this case, the position of the peripheral circuit region 800 in the Z direction is higher than the position of the memory cell array 100 in the Z direction. For example, the position of the upper surface f2 of the substrate (semiconductor region) of the peripheral circuit region 800 in the Z direction is higher than the position of the upper surface fl of the substrate of the region in which the memory cell array 100 is arranged.

[0138] For example, the peripheral circuit region 800 is arranged in a region adjacent to the TFT region 200 in the X direction and / or the Y direction.

[0139] Further, the peripheral circuit region 800 can not be arranged in the semiconductor region of the substrate 80, and all the elements that constitute the peripheral circuit can be arranged in the TFT region 200.

[0140] (b1) Configuration Example

[0141] Referring to Figures 9 to 11 , a configuration example of the flash memory of the present embodiment will be described.

[0142] Figures 9 to 11 is a view for explaining a basic configuration of a configuration example of an element in the peripheral circuit region above the memory cell array in the flash memory of the present embodiment.

[0143] Figure 9 is a plan view showing a configuration example of a transistor in the peripheral circuit region (TFT region) in the flash memory of the present embodiment. Figure 10 is a cross-sectional view of the flash memory of the present embodiment along the A-A line of Figure 9 . Figure 11 is a cross-sectional view of the flash memory of the present embodiment along the B-B line of Figure 9 .

[0144] As shown in Figures 9 to 11 , a plurality of semiconductor layers 300 (300a, 300b) are arranged above the memory cell array 100 in the Z direction. The plurality of semiconductor layers 300 are arranged in the Y direction and the X direction above the memory cell array 100. Each semiconductor layer 300 extends in the Y direction. Each semiconductor layer 300 has a planar structure that is a quadrangle when viewed in the Z direction. ​

[0145] For example, each semiconductor layer 300 is disposed at a position overlapping the stack 700 in the Z direction in the X-Y plane.

[0146] A plurality of field effect transistors TRn, TRp are provided on each semiconductor layer 300a, 300b. The semiconductor layer 300a is, for example, an n-type semiconductor layer. The semiconductor layer 300b is, for example, a p-type semiconductor layer. The semiconductor layers 300a, 300b can also be semiconductor layers to which no dopant is added by ion implantation.

[0147] The n-channel transistor TRn is provided on the semiconductor layer (semiconductor region) 300a. The p-channel transistor TRp is provided on the semiconductor layer (semiconductor region) 300b.

[0148] Each of the transistors TRn, TRp is a thin film transistor (TFT).

[0149] Each transistor TR (TRn, TRp) includes a gate electrode 35 (35a, 35b), a gate insulating layer 34 (34a, 34b), and two source / drain layers 30 (30a, 30b), 31 (31a, 31b).

[0150] In each transistor TR, two source / drain layers 30, 31 adjacent in the Y direction are provided in the semiconductor layer 300. The region 32 (32a, 32b) between the two source / drain layers in the semiconductor layer 300 becomes a channel region of the transistor.

[0151] For example, in the n-channel transistor TRn, the n-type source / drain layers 30a, 31a are provided in the semiconductor layer 300a. For example, in the p-channel transistor TRp, the p-type source / drain layers 30b, 31b are provided in the semiconductor layer 300b.

[0152] The gate electrode 35 is provided above the channel region 32 of the semiconductor layer 300. The gate insulating layer 34 is provided between the gate electrode 35 and the semiconductor layer 300.

[0153] Hereinafter, the stack including the gate electrode 35 and the gate insulating layer 34 is also referred to as a gate stack.

[0154] The conductive layer 40 is provided below the semiconductor layer 300 in the Z direction. The conductive layer 40 is disposed in a region between the semiconductor layer 300 in the Z direction and the memory cell array 100.

[0155] For example, in each of the transistors TRn, TRp, the source / drain layer 31 is connected to the conductive layer 40 via a contact plug 41 (41a, 41b). The contact plug 41 is in contact with a lower surface of the semiconductor layer 300 in the Z direction (a surface opposite to the surface on which the gate electrode is provided in the Z direction).

[0156] The conductive layers 46 (46a, 46b), 48 (48a, 48b) are provided above the semiconductor layer 300 in the Z direction.

[0157] For example, in each of the transistors TRn, TRp, the source / drain layer 30 is connected to the conductive layer 46 (46a, 46b) via a contact plug 47 (47a, 47b). The contact plug 47 is in contact with an upper surface of the semiconductor layer 300 in the Z direction (the surface on which the gate electrode is provided in the Z direction).

[0158] Further, both of the source / drain layers 30, 31 of each of the transistors TR can be connected to a contact plug in contact with the upper surface of the semiconductor layer 300. Also, both of the source / drain layers 30, 31 of each of the transistors TR can be connected to a contact plug in contact with the lower surface of the semiconductor layer 300. Also, the source / drain layer 30 can be connected to a contact plug in contact with the lower surface of the semiconductor layer 300, and the source / drain layer 31 can be connected to a contact plug in contact with the upper surface of the semiconductor layer 300.

[0159] For example, in each of the transistors TRn, TRp, the gate electrode 35 is connected to the conductive layer 48 via a contact plug 49 (49a, 49b).

[0160] For example, if two transistors TR adjacent in the Y direction on the common semiconductor layer 300 are transistors of the same conductivity type, the two transistors TR adjacent in the Y direction can share one source / drain layer between the two transistors.

[0161] By thus sharing the source / drain layer between the two transistors TR, it is possible to suppress an increase in the size (area) of the transistors TR (and circuits) above the memory cell array 100.

[0162] For example, the material of the semiconductor layer 300 is selected from silicon, germanium, silicon germanium, an oxide semiconductor, a nitride semiconductor, and an oxynitride semiconductor.

[0163] The material of the gate electrode 35 is selected from silicon, germanium, silicon germanium, a silicon compound, a germanium compound, a metal, and a conductive compound.

[0164] The material of the gate insulating layer 34 is selected from silicon oxide, silicon oxynitride, germanium oxide, germanium oxynitride, silicon germanium oxide, silicon germanium oxynitride, and an insulating high dielectric material.

[0165] In this embodiment, the pitch Dl of the plurality of semiconductor layers 300a in the TFT region 200 is substantially equal to the pitch Da of the plurality of laminated bodies 700 in the memory cell array 100.

[0166] The interval D2 between the two semiconductor layers 300 in the X direction is, for example, equal to the interval Db between the two laminated bodies 700 in the X direction.

[0167] The size of the semiconductor layer 300 in the X direction has, for example, a certain size D3. The size D3 is, for example, equal to the size Dc of the laminated body 700 in the X direction.

[0168] The pitch Dl of the semiconductor layers 300a corresponds to the size between one end (left end) of one semiconductor layer 300a in the X direction and one end (left end) of the other semiconductor layer 300a in the X direction among the two semiconductor layers 300a arranged in the X direction. Figure 11 Figure 11 The pitch Dl is equal to the sum of the interval D2 and the size D3.

[0169] The pitch Da of the laminated bodies 700 corresponds to the size between one end (left end) of one laminated body 700 in the X direction and one end (left end) of the other laminated body 700 in the X direction among the two laminated bodies 700 arranged in the X direction. Figure 11 Figure 11 The pitch Da is equal to the sum of the interval Db and the size Dc.

[0170] If the film thickness of the memory layer 51 on the side surface of the laminated body 700 is represented by "ta", the size Db is greater than 2 x ta. If the size of the conductive layer 50 between the memory layers 51 opposite to each other in the X direction is represented by "tb", the size Db is equal to 2 x ta + tb.

[0171] The pitch Da is equal to the sum of the interval Db and the size Dc.

[0172] In addition, sometimes the laminated body 700 has a tapered cross-sectional shape depending on the number of laminations of the semiconductor layer 70 (height of the laminated body 700 in the Z direction) in the laminated body 700. In this case, the pitch Da of the laminated body 700, the interval Db between the laminated bodies 700, and the size Dc of the laminated body 700 are set based on the size of the upper end side of the laminated body 700 in the Z direction. However, the pitch Da and the interval Db can be set based on the size of the lower end side of the laminated body 700 in the Z direction.

[0173] The processing (etching) of the semiconductor layer 300 is common to the processing (etching) of the gate stack (gate electrode 35 and gate insulating layer 34).

[0174] ​​By commonalization of the manufacturing process, the position of the end portion of the semiconductor layer 300 in the X direction is aligned with the position of the end portion of the gate electrode 35 in the X direction (gate end in the gate width direction). For example, the size D3 of the semiconductor layer 300 in the X direction is equal to the size D3a of the gate electrode 35 in the X direction.

[0175] The position of the end portion of the gate insulating layer 34 in the X direction is aligned with the position of the end portion of the semiconductor layer 300 in the X direction and the position of the end portion of the gate electrode 35 in the X direction. The size of the gate insulating layer 34 in the X direction is equal to the size D3 of the semiconductor layer 300a and the size D3a of the gate electrode 35a.

[0176] For example, when the semiconductor layer 300 is processed, the end portion of the contact plug 41 below the semiconductor layer 300 in the X direction is sometimes etched according to the pattern of the semiconductor layer 300.

[0177] In this case, the position of the end portion of the contact plug 41 in the X direction is aligned with the position of the end portion of the semiconductor layer 300 in the X direction. In addition, the position of the end portion of the contact plug 41 in the X direction is aligned with the position of the end portion of the gate insulating layer 34 in the X direction and the position of the end portion of the gate electrode 35 in the X direction. Furthermore, only the position of one end of the contact plug 41 in the X direction can be aligned with the position of one end of the semiconductor layer 300 in the X direction.

[0178] For example, the contact plug 41a includes a portion 411a having a size D3z in the X direction. For example, the contact plug 41a includes two portions 411a and 412a. The portion 411a is provided between the semiconductor layer 300 and the portion 412a. The portion 412a is provided between the portion 411a and the conductive layer 40.

[0179] The size D3z of the portion 411a in the X direction is smaller than the maximum size D3x of the portion 412a in the X direction. Furthermore, the portion 412a has the maximum size on the upper side (the portion 411a side) in the Z direction and has the minimum size on the lower side (the conductive layer 40 side) in the Z direction.

[0180] Furthermore, illustrated here is the size relationship of the semiconductor layer 300a and the laminate 700. The size relationship of the semiconductor layer 300b and the laminate 700 is substantially the same as the size relationship of the semiconductor layer 300a and the laminate 700.

[0181] Here, the size relationship of the semiconductor layer 300a and the gate electrode 35a of the n-channel transistor is merely an example. The size relationship of the semiconductor layer 300b and the gate electrode 35b of the p-channel transistor is substantially the same as the size relationship of the semiconductor layer 300a and the gate electrode 35a.

[0182] Above the memory cell array 100 in the Z direction, a peripheral circuit using a plurality of transistors TR having the above-described structure as a basic structure is provided.

[0183] Next, a configuration example of the peripheral circuit above the memory cell array 100 will be described.

[0184] Example 1: Select Gate Line Decoder

[0185] Reference Figures 12 to 14 Example 1 of the peripheral circuit above the memory cell array in the flash memory of the present embodiment will be described.

[0186] In this example, the select gate decoder 142 is provided in the TFT region 200 above the memory cell array 100.

[0187] (Circuit Example)

[0188] Figure 12 is a schematic circuit diagram showing the configuration of the select gate line decoder of the flash memory of the present embodiment.

[0189] In the present embodiment, the select gate line decoder (hereinafter, also referred to as the SG decoder) 142 includes a plurality of field effect transistors TRn, TRp in the TFT region 200 above the memory cell array 100 in the Z direction.

[0190] The SG decoder 142 sets the drain side and source side select gate lines SGD, SGS among the plurality of select gate lines SGD, SGS in the memory cell array 100 based on address information (select address) to a selected state (activated state). The SG decoder 142 sets the select gate lines SGD, SGS other than the selected select gate lines SGD, SGS to a non-selected state (deactivated state). Hereinafter, a group of a pair of the drain side select gate line SGD and the source side select gate line SGS is also referred to as a select gate line group SG. In this example, the number of the select gate line groups SG is four.

[0191] The SG decoder 142 includes an address decoding circuit 60 and a selection circuit 61.

[0192] The address decoding circuit 60 includes a plurality of decoding units DU (DU0, DU1, DU2, DU3). Each decoding unit DU is associated with one group of the plurality of select gate line groups SG.

[0193] For example, the number of the decoding units DU is the same as the number of the select gate line groups SG in the block BLK. In this example, an example in which four decoding units DU are provided in the address decoding circuit 60 is shown. However, the number of the decoding units DU is changed according to the number of the select gate line groups in the memory cell array 100.

[0194] A plurality of decoding units DU decode the selection gate line address ADD-SG by different calculation processing (decoding processing) of supplied address information.

[0195] For example, in a case where a certain block BLK (or a certain sub-block or string unit) has four selection gate line groups SG, the selection gate lines of the certain block are represented by two-bit signals A0, Al.

[0196] In this case, each decoding unit DU (DUO, DUl, DU2, DU3) includes two n-channel transistors TRnO, TRnl and two p-channel transistors TRpO, TRpl.

[0197] In each decoding unit DU, one of the source / drain electrodes of the transistor TRnl (TRnl a, TRnl b, TRnl c, TRnl d) is connected to a terminal to which a ground voltage Vss is applied (hereinafter, referred to as a ground terminal Vss). The other of the source / drain electrodes of the transistor TRnl is connected to one of the source / drain electrodes of the transistor TRnO (TRnOa, TRnOb, TRnOc, TRnOd). The other of the source / drain electrodes of the transistor TRnO is connected to the corresponding decoding signal line DEC (DECO, DEC 1, DEC2, DEC3).

[0198] Thus, in the decoding unit DU, with respect to the plurality of transistors TRn, the current paths of the transistors TRn are connected in series between the ground terminal Vss and the decoding signal line DEC.

[0199] In each decoding unit DU, one of the source / drain electrodes of the transistor TRpO (TRpOa, TRpOb, TRpOc, TRpOd) is connected to a terminal to which a voltage Vdd is applied (hereinafter, referred to as a power supply terminal Vdd). The other of the source / drain electrodes of the transistor TRpO is connected to the corresponding decoding signal line DEC. One of the source / drain electrodes of the transistor TRpl (TRpl a, TRpl b, TRpl c, TRpl d) is connected to the power supply terminal Vdd. The other of the source / drain electrodes of the transistor TRpl is connected to the corresponding decoding signal line DEC.

[0200] Thus, in the decoding unit DU, with respect to the plurality of transistors TRp, the current paths of the transistors TRn are connected in parallel between the power supply terminal Vdd and the decoding signal line DEC.

[0201] The select gate line address ADD-SG includes a plurality of signals (hereinafter, also referred to as address bit signals) A0, A1. Either of the signal A0 or the signal bA0 is supplied to the gate of the transistor TRn0 according to the decoding unit DU. Either of the signal A1 or the signal bA1 is supplied to the gate of the transistor TRn1 according to the decoding unit DU. The signal bA0 is an inverted signal of the signal A0. The signal bA1 is an inverted signal of the signal A1.

[0202] Either of the signal A0 or the signal bA0 is supplied to the gate of the transistor TRp0 according to the decoding unit DU. Either of the signal A1 or the signal bA1 is supplied to the gate of the transistor TRp1 according to the decoding unit DU.

[0203] The selection circuit 61 includes a plurality of drain side select gate line selectors (hereinafter, also referred to as drain side SG selectors) SUD (SUD0, SUD1, SUD2, SUD3) and a plurality of source side select gate line selectors (hereinafter, also referred to as source side SG selectors) SUS (SUS0, SUS1, SUS2, SUS3).

[0204] The drain side SG selector SUD is associated with a corresponding one of the plurality of drain side select gate lines SGD. The source side SG selector SUS is associated with a corresponding one of the plurality of source side select gate lines SGS.

[0205] Each of the SG selectors SUD includes an n-channel transistor TRn2 (TRn2a, TRn2b, TRn2c, TRn2d) and a p-channel transistor TRp2 (TRp2a, TRp2b, TRp2c, TRp2d).

[0206] In each of the SG selectors SUD, one of the source / drain of the transistor TRn2 is connected to a ground terminal Vss, and the other of the source / drain of the transistor TRn2 is connected to a node NDd (NDd0, NDd1, NDd2, NDd3). In each of the SG selectors SUD, one of the source / drain of the transistor TRp2 is connected to a terminal to which a voltage Vsgd is applied (hereinafter, also referred to as a power supply terminal Vsgd). The other of the source / drain of the transistor TRp2 is connected to the node NDd.

[0207] The node NDd of each of the SG selectors SUD is connected to a corresponding one of the plurality of drain side select gate lines SGD.

[0208] In each drain side SG selector SUD, the gate of the transistor TRn2 and the gate of the transistor TRp2 are connected to a corresponding one of a plurality of decoding signal lines DEC. In each SG selector SUD, either of the transistor TRn2 and the transistor TRp2 is turned on in accordance with the potential of the decoding signal line DEC (signal level of the decoding signal).

[0209] Each SG selector SUS includes an n-channel transistor TRn3 (TRn3a, TRn3b, TRn3c, TRn3d) and a p-channel transistor TRp3 (TRp3a, TRp3b, TRp3c, TRp3d).

[0210] In each SG selector SUS, one of the source / drain of the transistor TRn3 is connected to a ground terminal Vss, and the other of the source / drain of the transistor TRn3 is connected to a node NDs (NDs0, NDs1, NDs2, NDs3). In each SG selector SUS, one of the source / drain of the transistor TRp3 is connected to a terminal to which a voltage Vsgs is applied (hereinafter, also referred to as a power supply terminal Vsgs). The other of the source / drain of the transistor TRp3 is connected to the node NDs.

[0211] The node NDs of each SG selector SUS is connected to a corresponding one of a plurality of source side selection gate lines SGS.

[0212] In each source side SG selector SUS, the gate of the transistor TRn3 and the gate of the transistor TRp3 are connected to a corresponding one of a plurality of decoding signal lines DEC. In each SG selector SUS, either of the transistor TRn3 and the transistor TRp3 is turned on in accordance with the potential of the decoding signal line DEC.

[0213] The SG decoder 142 includes a plurality of inverters INV0, INV1.

[0214] Each address bit signal A0, A1 is supplied to a corresponding inverter INV0, INV1. The inverter INV0 outputs an inverted signal of the address bit signal A0 (hereinafter, referred to as an inverted address bit signal) bA0. The inverter INV1 outputs an inverted address bit signal bA1 of the address bit signal A1.

[0215] The SG decoder 142 uses the address bit signals A0, A1 and the inverted signals bA0, bA1 thereof to control the selection state and the non-selection state of the selection gate lines SGD, SGS.

[0216] (Action Example)

[0217] The SG decoder 142 selects one of the plurality of select gate line groups based on the address information ADD.

[0218] In the SG decoder 142, the plurality of decoding units DU each receive a select gate line address.

[0219] Each decoding unit DU decodes the select gate line address. Each decoding unit DU outputs a signal (hereinafter, referred to as a decoding signal) indicating the decoding result to the corresponding drain side and source side SG selectors SUD, SUS.

[0220] The decoding unit DU corresponding to the select gate line address outputs a decoding signal indicating a selection state. The other decoding units DU output a decoding signal indicating a non-selection state.

[0221] In the selection circuit, each SG selector SUD, SUS receives a decoding signal from the corresponding decoding unit DU.

[0222] In a case where the SG selector SUD, SUS receives a decoding signal indicating a selection state, the SG selector SUD, SUS brings the corresponding select gate line group SG into a selection state. In a case where the SG selector receives a decoding signal indicating a non-selection state, the SG selector sets the corresponding select gate line group SG to a non-selection state.

[0223] Thus, one of the plurality of select gate line groups within the memory cell array is selected.

[0224] As shown in FIG. 2, an example in which the select gate line address ADD-SG is expressed by 2 bits is illustrated, and the operation example of the SG decoder 142 is described in more detail. Figure 12 The 2-bit select gate line address ADD-SG includes 2 address bit signals A0, Al.

[0225] In the 2-bit address ADD-SG, the address signal A0 corresponds to the lower bit, and the address signal Al corresponds to the upper bit.

[0226] In a case where the addresses of the select gate lines SGD, SGS are expressed by 2 bits, one memory cell array 100 includes 4 drain side select gate lines SGD (SGD0, SGD1, SGD2, SGD3) and 4 source side select gate lines SGS (SGS0, SGS1, SGS2, SGS3).

[0227]

[0228] The SG decoder 142 of FIG. 2 selects one of the 4 select gate line groups based on the select gate line address ADD-SG. Figure 12

[0229] ​Further, the unit selected by selecting the gate line address ADD-SG differs depending on the configuration within the memory cell array 100. For example, selecting the gate line address ADD-SG corresponds to the address of a block of the memory cell array 100, or the address of a selection unit (e.g., a sub-block or a string unit) smaller than the allocated block within the block.

[0230] Each address bit signal A0, A1 of the selected gate line address ADD-SG is supplied to the corresponding inverter INV0, INV1. The inverter INV0 outputs an inverted signal bA0 of the address bit signal A0. The inverter INV1 outputs an inverted signal bA1 of the address bit signal A1.

[0231] In the address decoding circuit 60, the decoding units DU receive the address bit signals A0, bA1 and / or the inverted signals bA0, bA1 in accordance with the corresponding selected gate line group.

[0232] Each decoding unit DU generates a decoding signal based on the address bit signals A0, A1 and / or the inverted signals bA0, bA1.

[0233] For example, in the case where the value of the selected gate line address ADD-SG is "00", the decoding unit DU0 receives a "1" signal bA0 and a "1" signal bA1.

[0234] In this case, the other decoding units DU1, DU2, DU3 receive the address bit signals as described below, respectively.

[0235] The decoding unit DU1 receives a "0" signal A0 and a "1" signal bA1. The decoding unit DU2 receives a "1" signal bA0 and a "0" signal A1. The decoding unit DU3 receives a "0" signal A0 and a "0" signal A1.

[0236] Further, the "0" signal is associated with a signal of an "L" level. The "1" signal is associated with a signal of an "H" level. For example, the voltage value of a signal representing the "H" level (e.g., a power supply voltage) is higher than the voltage value of a signal representing the "L" level (e.g., a ground voltage Vss).

[0237] In the decoding unit DU0, a signal of an "H" (= "1") level is supplied to the gates of the transistors TRn0, TRn1 and the gates of the transistors TRp0, TRp1.

[0238] By the "H" level signal bA0, bA1, in the decoding unit DU0, the n-channel type transistors TRn0, TRn1 are all turned on. The ground terminal Vss is connected to the decoding signal line DEC0 via the turned-on transistor nTR. By the "H" level signal bA0, bA1, the p-channel type transistors TRp0, TRp1 of the decoding unit DU0 are all turned off. The power supply terminal Vdd is electrically separated from the decoding signal line DEC0 by the turned-off transistors TRp0, TRp1.

[0239] As a result, the decoding unit DU0 outputs the "L" level decoding signal to the decoding signal line DEC0.

[0240] In the decoding unit DU1, by the "0" signal A0, the transistor TRn0b is turned off and the transistor TRp1b is turned on. The ground terminal Vss is electrically separated from the decoding signal line DEC1 by the turned-off transistor TRn0b. The power supply terminal Vdd is electrically connected to the decoding signal line DEC1 by the turned-on transistor TRp1b.

[0241] Thus, the decoding unit DU1 outputs the voltage Vdd to the decoding signal line DEC1.

[0242] In the decoding unit DU2, by the "0" signal A1, the transistor TRn1c is turned off and the transistor TRp0c is turned on. The ground terminal Vss is electrically separated from the decoding signal line DEC2 by the turned-off transistor TRn1c. The power supply terminal Vdd is electrically connected to the decoding signal line DEC2 by the turned-on transistor TRp0c.

[0243] Thus, the decoding unit DU2 outputs the voltage Vdd to the decoding signal line DEC2.

[0244] In the decoding unit DU3, by the "0" signals A0, A1, the transistors TRn0d, TRn1d are turned off and the transistors TRp0d, TRp1d are turned on. The ground terminal Vss is electrically separated from the decoding signal line DEC3 by the turned-off transistors TRn0d, TRn1d. The power supply terminal Vdd is electrically connected to the decoding signal line DEC3 by the turned-on transistors TRp0d, TRp1d.

[0245] Thus, the decoding unit DU3 outputs the voltage Vdd to the decoding signal line DEC3.

[0246] Thus, according to the signal levels of the signals A0, A1, bA0, bA1 of the selected gate line address ADD-SG, one decoding unit DU selected from the plurality of decoding units DU outputs the "L" level decoding signal. The other plurality of decoding units DU which are not selected output the "H" level decoding signal.

[0247] Each SG selector SU receives a decoded signal from the corresponding decoding unit DU.

[0248] The SG selector SUO, SUSO receives a decoded signal of "L" level from the decoding unit DUO.

[0249] The other SG selectors SUDl, SUD2, SUD3, SUSl, SUS2, SUS3 receive decoded signals of "H" level from the decoding units DUl, DU2, DU3, respectively.

[0250] In the SG selector SUO, the n-channel transistor TRn2a is turned off by the decoded signal of "L" level. The ground terminal Vss is electrically separated from the node NDdO through the transistor TRn2a in the off state. The p-channel transistor TRp2a is turned on by the decoded signal of "L" level. The power supply terminal Vsgd is electrically connected to the node NDdO through the transistor TRp2a in the on state.

[0251] In the SG selector SUSO, the n-channel transistor TRn3a is turned off by the decoded signal of "L" level. The ground terminal Vss is electrically separated from the node NDsO through the transistor TRn3a in the off state. The p-channel transistor TRp3a is turned on by the decoded signal of "L" level. The power supply terminal Vsgs is electrically connected to the node NDsO through the transistor TRp3a in the on state.

[0252] As a result, the voltage Vsgd is applied to the drain side select gate line SGD0. The voltage Vsgs is applied to the source side select gate line GSO.

[0253] Thus, the select gate lines SGD0, GSO become the selection state. The select transistor STl connected to the select gate line SGD0 is turned on by the applied voltage Vsgd. The select transistor ST2 connected to the select gate line GSO is turned on by the applied voltage Vsgs.

[0254] In the other drain side SG selectors SUDl, SUD2, SUD3, the transistors TRn2 are turned on and the transistors TRp2 are turned off by the decoded signals of "H" level. Thus, the ground voltage Vss is applied to the drain side select gate lines SGDl, SGD2, SGD3, respectively.

[0255] As a result, the select transistors STl connected to the drain side select gate lines SGDl, SGD2, SGD3 are turned off, respectively.

[0256] In the other source side SG selectors SUS1, SUS2, SUS3, the transistor TRn3 is turned on and the transistor TRp3 is turned off by the decoding signal of the "H" level. Thus, the source side selection gate lines SGS1, SGS2, SGS3 are applied with the ground voltage Vss, respectively.

[0257] As a result, the selection transistors ST2 connected to the source side selection gate lines SGS1, SGS2, SGS3 are turned off, respectively.

[0258] Thus, the selection gate lines SGD0, SGS0 other than the selected selection gate lines SGD0, SGS0 become the non-selected state.

[0259] In the case where the address bit signals A0, A1 of the selection gate line address are "01", "10", and "11", the decoding unit DU1, DU2, DU3 outputs the decoding signal of the "L" level in any of the decoding units. The SG selector supplied with the decoding signal of the "L" level makes the selection gate lines SGD, SGS into the selected state.

[0260] Thus, in the present embodiment, Figure 12 the SG decoder 142 can select the drain side selection gate line SGD and the source side selection gate line SGS based on the address information ADD.

[0261] (Configuration Example)

[0262] Referring to Figure 13 and Figure 14 , the configuration example of the SG decoder in the flash memory of the present embodiment will be described.

[0263] Figure 13 is a schematic plan view showing the configuration example of the address decoding circuit of the SG decoder in the flash memory of the present embodiment.

[0264] Figure 14 is a schematic sectional view showing the configuration example of the SG decoder in the flash memory of the present embodiment. Figure 14 shows the section along the A1-A1 line of Figure 13 .

[0265] Further, Figure 14 the section along the X direction of Figure 11 is substantially the same as the example of

[0266] As Figure 13 and Figure 14As shown, a plurality of semiconductor layers 300a (300a-0, 300a-1, 300a-2, 300a-3) and a plurality of semiconductor layers 300b (300b-0, 300b-1, 300b-2, 300b-3) are provided in the TFT region 200 above the memory cell array 100 in the Z direction. The plurality of semiconductor layers 300a, 300b are provided at the same height from the upper surface of the substrate in the Z direction. Each semiconductor layer 300a, 300b extends in the Y direction.

[0267] A region R60 in which the address decoding circuit 60 is provided is provided above the memory cell array 100.

[0268] In the region R60, n-channel field effect transistors (e.g., TFTs) TRn0a, TRn1a are provided on each semiconductor layer 300a.

[0269] For example, in the decoding unit DU0, 2 transistors TRn0a, TRn1a are provided on the semiconductor layer 300a-0.

[0270] 2 gate electrodes 35a-0a, 35a-1a are provided on the semiconductor layer 300a-0 with the gate insulating layer 34 interposed therebetween. For example, an insulating layer (hereinafter, also referred to as a sidewall insulating layer) 39 is provided on the side surface of the gate electrode 35a.

[0271] A plurality of source / drain layers 30a, 31a, 33a are provided in the semiconductor layer 300a-0. A channel region 32a is provided in the semiconductor layer 300a-0 between the source / drain layers 30a, 31a, 33a.

[0272] On 1 semiconductor layer 300a-0, 2 transistors TRn0a, TRn1a adjacent in the Y direction share the source / drain layer 33a.

[0273] Thus, the current paths of the transistors TRn0a, TRn1a on each semiconductor layer 300a-0 are connected in series.

[0274] One end of the semiconductor layer 300a-0 is electrically connected to a conductive layer (e.g., a metal layer) 40a. The conductive layer 40a extends in the Y direction. The conductive layer 40a is provided between the semiconductor layers 300a-0, 300b-0 and the memory cell array 100 in the Z direction. The position of the conductive layer 40a in the Z direction is lower than the position of the semiconductor layer 300a in the Z direction.

[0275] The contact plug 41a is provided below the lower surface of one end (the source / drain layer 31a) of the semiconductor layer 300a-0 in the Y direction. The contact plug 41a is provided between the semiconductor layer 300a-0 and the conductive layer 40a. The semiconductor layer 300a-0 is connected to the conductive layer 40a via the contact plug 41a.

[0276] The other end (the source / drain layer 30a) of the semiconductor layer 300a-0 is connected to a semiconductor layer 301. The semiconductor layer 301 extends in the X direction. A plurality of semiconductor layers 300a-0 are commonly connected to one semiconductor layer 301. The semiconductor layer 301 is connected to a ground terminal Vss. A ground voltage Vss is supplied from the semiconductor layer 301 to the plurality of semiconductor layers 300a-0.

[0277] For example, the semiconductor layer 300a-0 and the semiconductor layer 301 are continuous one layer.

[0278] The source / drain layers 31a arranged in the X direction are each separated in each decoding unit DU. The source / drain layers 33a arranged in the X direction are each separated in each decoding unit DU.

[0279] A plurality of conductive layers (for example, metal layers) 48a (48a-0, 48a-1, 48a-2, 48a-3) are provided above the gate electrodes 35a-0a, 35a-1a. Each conductive layer 48a extends in the X direction.

[0280] The four conductive layers 48a are arranged above the plurality of gate electrodes 35a arranged in the X direction. The position of the conductive layer 48a in the Z direction is higher than the position of the semiconductor layer 300a in the Z direction.

[0281] Address bit signals are supplied to each conductive layer 48a.

[0282] As described above, in a case where the selection gate line address ADD-SG includes 2-bit address bit signals, the signal A0 is supplied to the conductive layer 48a-0, and the inverted signal bA0 is supplied to the conductive layer 48a-1. The signal A1 is supplied to the conductive layer 48a-2, and the inverted signal bA1 is supplied to the conductive layer 48a-3.

[0283] For example, in the transistors TRn0, TRn1 of the decoding unit DU0, the conductive layer 48a-1 is connected to the gate electrode 35a-0a via a contact plug CP, and the conductive layer 48a-3 is connected to the gate electrode 35a-1a via a contact plug CP.

[0284] In the other decoding units DU1, DU2, DU3, the transistors TRn0, TRn1 on the respective semiconductor layers 300a have substantially the same structure as the structure. But the conductive layers 48a-0, 48a-1, 48a-2, 48a-3 connected to the respective gate electrodes 35a are different in each decoding unit DU.

[0285] The p-channel type field effect transistors (e.g., TFTs) TRp0, TRp1 are provided on the respective semiconductor layers 300b.

[0286] For example, in the decoding unit DU0, 2 transistors TRp0a, TRp1a are provided on the semiconductor layer 300b-0.

[0287] The 2 gate electrodes 35b-0a, 35b-1a are provided on the semiconductor layer 300b-0 with the gate insulating layer 34 interposed. For example, the side wall insulating layer 39 is provided on the side of the gate electrode 35b.

[0288] A plurality of source / drain layers 30b (30ba, 30bb), 31b are provided in the semiconductor layer 300b. A channel region 32b is provided in the semiconductor layer 300b between the source / drain layers 30b, 31b.

[0289] In the plurality of semiconductor layers 300b arranged in the X direction, the source / drain layers 30ba arranged in the X direction are connected via a semiconductor layer 302. The semiconductor layer 302 extends in the X direction. The semiconductor layer 302 is connected to the power supply terminal Vdd. The power supply voltage Vdd is supplied from the semiconductor layer 302 to the plurality of semiconductor layers 300b.

[0290] For example, the semiconductor layer 300b and the semiconductor layer 302 are continuous 1 layer.

[0291] Further, the plurality of source / drain layers 30ba can also be connected via a contact plug and a conductive layer.

[0292] In the plurality of semiconductor layers 300b arranged in the X direction, the source / drain layers 30bb arranged in the X direction are connected via a semiconductor layer 303. The semiconductor layer 303 is connected to the power supply terminal Vdd. The power supply voltage Vdd is supplied from the semiconductor layer 303 to the plurality of semiconductor layers 300b.

[0293] For example, the semiconductor layer 300b and the semiconductor layer 303 are continuous 1 layer.

[0294] Further, the plurality of source / drain layers 30bb can also be connected via a contact plug and a conductive layer.

[0295] On one semiconductor layer 300b, the 2 transistors TRp0a, TRn1a adjacent in the Y direction share the source / drain layer 31b.

[0296] The source / drain layer 31b is electrically connected to the conductive layer 40a below the semiconductor layer 300b in the Z direction via the contact plug 41b.

[0297] The contact plug 41b overlaps the source / drain layer 31b in the Z direction. The source / drain layers 31b arranged in the Y direction are separated from each other.

[0298] A plurality of conductive layers (e.g., metal layers) 48b are provided above the gate electrodes 35b-0a, 35b-1a. Each conductive layer 48b extends in the X direction.

[0299] The four conductive layers 48b are arranged above the plurality of gate electrodes 35b arranged in the X direction. The conductive layers 48b are positioned higher in the Z direction than the semiconductor layers 300b.

[0300] The address bit signals are supplied to each conductive layer 48b.

[0301] As described above, in the case where the selection gate line address ADD-SG includes 2-bit address bit signals, the signal A0 is supplied to the conductive layer 48b-0 and the inverted signal bA0 is supplied to the conductive layer 48b-1. The signal A1 is supplied to the conductive layer 48b-2 and the inverted signal bA1 is supplied to the conductive layer 48b-3.

[0302] For example, in the transistors TRp0, TRp1 of the decoding unit DU0, the conductive layer 48b-1 is connected to the gate electrode 35b-0a via the contact plug CP and the conductive layer 48b-3 is connected to the gate electrode 35b-1a via the contact plug CP.

[0303] In the other decoding units DU, the transistors TRp0, TRp1 on each semiconductor layer 300b have substantially the same structure as the above-described structure. However, the conductive layers 48b-0, 48b-1, 48b-2, 48b-3 connected to each gate electrode 35b are different in each decoding unit DU.

[0304] The drain side SG selector SUD and the source side SG selector SUS are provided in the regions R61D, R61S above the memory cell array 100 in the Z direction.

[0305] The region R61D in which the drain side SG selector SUD is provided is provided on one end side in the Y direction of the region R60 in which the address decoding circuit 60 is provided. The region R61S in which the source side SG selector SUS is provided is provided on one end side in the Y direction of the region R60 in which the address decoding circuit 60 is provided.

[0306] For example, the drain-side SG selectors SUD and the source-side SG selectors SUS are provided in regions (for example, regions above the corresponding selection gate lines) near the corresponding selection gate line groups SG. Via the plurality of conductive layers and the contact plugs, each of the SG selectors SUD, SUS is connected to the corresponding decoding unit DU.

[0307] In order to connect the decoding units DU and the SG selectors SU (SUD, SUS), the plurality of conductive layers 40a, 48d, 48s included in the decoding signal line DEC and the plurality of contact plugs are routed in the regions between the region R60 and the regions R61D, R61S in the desired layout.

[0308] In the regions R61D, R61S in which each of the SG selectors SU is arranged, the semiconductor layer 300a (300a-d, 300a-s) and the semiconductor layer 300b (300b-d, 300b-s) are provided.

[0309] In the region R61D of the drain-side SG selector SUD, the n-channel transistors TRn2a (TRn2a, TRn2b, TRn2c, TRn2d) are each provided on the semiconductor layer 300a-d.

[0310] The gate electrode 35ad of the transistor TRn2 is provided above the semiconductor layer 300a-d with the gate insulating layer 34 interposed therebetween.

[0311] The two source / drain layers (n-type semiconductor regions) 30ad, 31ad of the transistor TRn2 are provided in the semiconductor layer 300a-d. The channel region 32ad is provided in the semiconductor layer 300a-d between the two source / drain layers 30ad, 31ad.

[0312] The source / drain layer 30ad is connected to the ground terminal Vss. The source / drain layer 31ad is connected to the conductive layer (node NDd) 40d via the contact plug 41nd. The position of the conductive layer 40d in the Z direction is lower than the position of the semiconductor layer 300a-d in the Z direction. The position of the conductive layer 40d in the Z direction is the same as the position of the conductive layer 40a in the Z direction.

[0313] The gate electrode 35ad is connected to the conductive layer 48d via the plug 49ad. The position of the conductive layer 48d in the Z direction is higher than the position of the semiconductor layer 300a-d in the Z direction. The position of the conductive layer 48d in the Z direction is the same as the position of the conductive layer 48a in the Z direction.

[0314] In the region R61D of the drain-side SG selector SUD, the p-channel transistors TRp2 (TRp2a, TRp2b, TRp2c, TRp2d) are provided on the semiconductor layer 300b-d.

[0315] The gate electrode 35bd of the p-channel transistor TRp2 is provided above the semiconductor layer 300b-d with the gate insulating layer 34 interposed therebetween.

[0316] The two source / drain layers (p-type semiconductor regions) 30bd, 31bd of the transistor TRp2 are provided within the semiconductor layer 300b-d. The channel region 32bd is provided within the semiconductor layer 300b-d between the two source / drain layers 30bd, 31bd.

[0317] The source / drain layer 30bd is connected to the power supply terminal Vsgd. The source / drain layer 31bd is connected to the conductive layer 40d (node NDd) via the contact plug 41pd.

[0318] The gate electrode 35bd is connected to the conductive layer 48d via the contact plug 49bd.

[0319] The conductive layer 48d is connected to the conductive layer 40a via the contact plugs 41d, 49d and the conductive layer 309d. The conductive layer 309d is, for example, a semiconductor layer (e.g., an n-type semiconductor layer). The position of the conductive layer 309d in the Z direction is substantially the same as the position of the semiconductor layer 300 in the Z direction.

[0320] Each of the n-channel transistors TRn3 (TRn3a, TRn3b, TRn3c, TRn3d) is provided on the semiconductor layer 300a-s within the region R61S of the source side SG selector SUS.

[0321] The gate electrode 35as of the transistor TRn3 is provided above the semiconductor layer 300a-s with the gate insulating layer 34 interposed therebetween.

[0322] The two source / drain layers (n-type semiconductor regions) 30as, 31as of the transistor TRn3 are provided within the semiconductor layer 300a-s. The channel region 32as is provided within the semiconductor layer 300a-s between the two source / drain layers 30as, 31as.

[0323] The source / drain layer 30as is connected to the ground terminal Vss. The source / drain layer 31as is connected to the conductive layer (node NDs) 40s via the contact plug 41ns. The position of the conductive layer 40s in the Z direction is lower than the position of the semiconductor layer 300a-s in the Z direction. The position of the conductive layer 40s in the Z direction is the same as the position of the conductive layer 40a in the Z direction.

[0324] The gate electrode 35as is connected to the conductive layer 48s via the plug 49as. The position of the conductive layer 48s in the Z direction is higher than the position of the semiconductor layer 300a-s in the Z direction. The position of the conductive layer 48s in the Z direction is the same as the position of the conductive layer 48a in the Z direction.

[0325] In the region R61S of the source side SG selector SUS, a p-channel transistor TRp3 (TRp3a, TRp3b, TRp3c, TRp3d) is provided on the semiconductor layer 300b-s.

[0326] The gate electrode 35bs of the p-channel transistor TRp3 is provided above the semiconductor layer 300b-s with the gate insulating layer 34 interposed therebetween.

[0327] The two source / drain layers (p-type semiconductor regions) 30bs, 31bs of the transistor TRp3 are provided in the semiconductor layer 300b-s. The channel region 32bs is provided in the semiconductor layer 300b-s between the two source / drain layers 30bs, 31bs.

[0328] The source / drain layer 30bs is connected to the power supply terminal Vsgs. The source / drain layer 31bs is connected to the conductive layer 40s (node NDd) via the contact plug 41ps.

[0329] The gate electrode 35bs is connected to the conductive layer 48s via the contact plug 49bs.

[0330] The conductive layer 48s is connected to the conductive layer 40a via the contact plugs 41s, 49s and the conductive layer 309s. The conductive layer 309s is, for example, a semiconductor layer (e.g., an n-type semiconductor layer). The position of the conductive layer 309s in the Z direction is substantially the same as the position of the semiconductor layer 300 in the Z direction.

[0331] The decoding signal line DEC includes the conductive layer 40 provided in a layer (wiring layer) below the semiconductor layer 300, the conductive layer 48 provided in a layer above the semiconductor layer 300, and a plurality of contact plugs connecting between the conductive layers 40, 48. The layer (or wiring layer) is a region (space) provided at a position apart from the surface of the substrate by a certain height in the Z direction.

[0332] Thus, the SG selector SU is connected to the decoding unit DU.

[0333] In this way, one signal line can also be formed using a plurality of conductive layers provided in different layers.

[0334] For example, in the configuration region R60S of the source side SG selector, a dummy portion DM can also be provided in a region between the two semiconductor layers 300a-s, 300b-s.

[0335] The dummy portion DM includes the conductive layer 31x, the insulating layer 34x, and the conductive layer 35x. The conductive layer 35x is provided above the conductive layer 31x in the Z direction via the insulating layer 34x. The conductive layer 31x is, for example, a semiconductor layer. The position of the conductive layer 31x in the Z direction is the same as the position of the semiconductor layer 300 in the Z direction.

[0336] For example, the dummy portion DM indicates the boundary between adjacent blocks in the Y direction.

[0337] The drain side selection gate line SGD of the memory cell array 100 is connected to the conductive layer 40d via the contact plug 57D, 59D, and the conductive layer 58D.

[0338] Thus, the drain side selection gate line SGD is connected to the corresponding drain side SG selector SUD in the SG decoder 142.

[0339] The source side selection gate line SGS of the memory cell array 100 is connected to the conductive layer 40s via the contact plug 57S, 59S, and the conductive layer 58S.

[0340] Thus, the source side selection gate line SGS is connected to the corresponding source side SG selector SUS in the SG decoder 142.

[0341] As described above, in the flash memory 1 of the present embodiment, the SG decoder 142 can be formed using transistors (e.g., thin film transistors) in the region above the memory cell array 100.

[0342] Example 2: Bit line selection circuit

[0343] Reference Figure 15 Example 2 of the peripheral circuit above the memory cell array in the flash memory of the present embodiment will be described.

[0344] The bit line selection circuit 151 can also be provided in the TFT region 200 above the memory cell array 100.

[0345] Figure 15 is a schematic cross-sectional view showing an example of the structure of the bit line selection circuit in the flash memory of the present embodiment.

[0346] The bit line selection circuit 151 includes a plurality of transistors TRnq. For example, the number of the plurality of transistors TRnq in the bit line selection circuit 151 is the same as the number of the plurality of bit lines BL.

[0347] Each transistor TRnq is connected to a corresponding one of the plurality of bit lines BL. Each transistor TRnq is connected to a corresponding one of the plurality of bit line contacts CB. Each transistor TRnq is provided between the corresponding bit line BL and the corresponding bit line contact CB.

[0348] Each transistor TRnq controls electrical connection and electrical disconnection between the bit line BL and the bit line contact CB.

[0349] In the bit line selection circuit 151, each transistor TRnq functions as a bit line selector.

[0350] The transistor TRnq as the bit line selector is an n-channel field effect transistor (e.g., TFT).

[0351] The transistor TRnq includes two source / drain layers 30q, 31q, a channel region 32q, a gate electrode 35q, and a gate insulating layer 34.

[0352] The two source / drain layers 30q, 31q are provided in the semiconductor layer 300a. The source / drain layers 30q, 31q are semiconductor regions.

[0353] The channel region 32q is provided in the semiconductor layer 300a at a portion of the two source / drain layers 30q, 31q. The channel region 32q is a p-type semiconductor region.

[0354] The gate electrode 35q is provided above the channel region 32q in the Z direction with the gate insulating layer 34 interposed therebetween.

[0355] The bit line BL extends in a direction parallel to the surface of the substrate 80 (in the Figure 15 Y direction in the example) in a region above the semiconductor layer 300a in the Z direction.

[0356] The bit line BL is connected to the source / drain layer 30q via a contact plug 47q. The contact plug 47q is provided on an upper surface of the source / drain layer 30q in the Z direction.

[0357] The bit line contact CB is provided below the semiconductor layer 300a in the Z direction.

[0358] Between the bit line contact CB and the semiconductor layer 300a, a contact plug 41q, a conductive layer 40q, and a conductive layer 58q are provided.

[0359] The contact plug 41q is provided below a lower surface of the semiconductor layer 300a in the Z direction. The contact plug 41q is connected to the source / drain layer 31q.

[0360] The conductive layer 40q is provided below the contact plug 41q in the Z direction. The conductive layer 40q is, for example, a metal layer.

[0361] The contact plug 57q is provided below the conductive layer 40q in the Z direction.

[0362] The conductive layer 58q is provided between the contact plug 57q and the bit line contact CB.

[0363] Thus, the bit line contact CB is connected to the source / drain layer 31q via the contact plug 41q, 57q and the conductive layer 40q, 58q.

[0364] The contact plug 49q is provided on the upper surface of the gate electrode 35q in the Z direction.

[0365] The conductive layer 48q is provided above the gate electrode 35q in the Z direction. The conductive layer 48q is connected to the gate electrode 35q via the contact plug 49q. The conductive layer 48q is, for example, a metal layer.

[0366] The selection signal is supplied to the conductive layer 48q.

[0367] The transistor TRnq is turned on or off depending on the signal level of the selection signal BCSEL supplied to the conductive layer 48q.

[0368] The bit line BL is electrically connected to the bit line contact BC through the transistor TRnq in the on state. The bit line BL is electrically separated from the bit line contact BC through the transistor TRnq in the off state.

[0369] The bit line BL is connected to the corresponding semiconductor layer 70 via the transistor TRnq in the on state and the semiconductor layer 70A.

[0370] Thus, in the bit line selection circuit 151, each transistor TRnq as a bit line selector can control the electrical connection between the bit line BL and the NAND string NS.

[0371] As described above, the bit line selection circuit 151 can be formed using transistors (e.g., thin film transistors) in the region above the memory cell array 100.

[0372] Example 3: Amplification Circuit

[0373] Reference Figures 16 to 18 Example 2 of the peripheral circuit above the memory cell array in the flash memory of the present embodiment will be described.

[0374] The amplification circuit 152 can also be provided in the TFT region 200 above the memory cell array 100.

[0375] (Circuit Example)

[0376] Figure 16 is a circuit diagram showing a configuration example of the amplification circuit in the flash memory of the present embodiment.

[0377] As Figure 16 indicated, the amplification circuit (also referred to as a preamplifier) 152 is connected to the bit line BL in the sense amplifier 150.

[0378] The amplification circuit 152 amplifies a signal from the NAND string NS (memory cell MC).

[0379] The amplification circuit 152 includes a plurality of amplification units AMP.

[0380] Each amplification unit AMP is connected to a corresponding one of the plurality of bit lines BL. Each amplification unit AMP is connected to a corresponding one of the plurality of bit line contacts CB.

[0381] The amplification unit AMP amplifies a signal from the corresponding NAND string NS (memory cell MC). The amplification unit AMP supplies the amplified signal to the sense amplifier 150 via the bit line BL.

[0382] For example, the amplification unit AMP is provided between the bit line BL and the bit line contact CB, rather than between the bit line selector and the bit line contact CB.

[0383] Each amplification unit AMP includes a plurality of transistors TRnx1, TRnx2, TRnx3, TRpx1, TRpx2.

[0384] The transistors TRnx1, TRnx2, TRnx3 are n-channel field effect transistors. The transistors TRpx1, TRpx2 are p-channel field effect transistors.

[0385] One of the source / drain electrodes of the transistor TRnx1 is connected to the node NDa. The other of the source / drain electrodes of the transistor TRnx1 is connected to one of the source / drain electrodes of the transistor TRnx2. The other of the source / drain electrodes of the transistor TRnx2 is connected to a ground terminal Vss.

[0386] One of the source / drain electrodes of the transistor TRpx1 is connected to the node NDa. The other of the source / drain electrodes of the transistor TRpx1 is connected to one of the source / drain electrodes of the transistor TRpx2. The other of the source / drain electrodes of the transistor TRpx2 is connected to a terminal to which a voltage VI is applied (hereinafter, also referred to as a power supply terminal VI).

[0387] The gate electrode of the transistor TRnx2 is connected to the node NDb. The gate electrode of the transistor TRx2 is connected to the node NDb.

[0388] The node NDa is connected to the corresponding bit line BL. The node NDb is connected to the corresponding bit line contact CB.

[0389] The transistors TRnx1, TRnx2, TRpx1, TRpx2 function as inverters INV.

[0390] One of the source / drain of the transistor TRnx3 is connected to the corresponding bit line BL. The other of the source / drain of the transistor TRnx3 is connected to the corresponding bit line contact CB.

[0391] A plurality of control signals RD, bRD, WR are supplied to the amplifying unit AMP.

[0392] The signal RD is supplied to the gate of the transistor TRnx1. The signal bRD is supplied to the gate of the transistor TRpx1. The signal bRD is an inverted signal of the signal RD. The signal RD and the signal bRD have a complementary relationship.

[0393] The signal WR is supplied to the gate of the transistor TRnx3.

[0394] The signals RD, bRD are control signals indicating execution of a read operation. When the read operation is executed, the transistors TRnx1, TRpx1 (and the transistors TRnx2, TRpx2) are activated by the signals RD, bRD. When a write operation is executed, the transistors TRnx1, TRpx1 (and the transistors TRnx2, TRpx2) are deactivated by the signals RD, bRD.

[0395] When the read operation is executed, the signal level of the signal RD is set to an "H" level, and the signal level of the signal bRD is set to an "L" level. When the write operation is executed, the signal level of the signal RD is set to an "L" level, and the signal level of the signal bRD is set to an "L" level.

[0396] The signal WR is a control signal indicating execution of a write operation. When the write operation is executed, the transistor TRnx3 is activated by the signal WR. When the read operation is executed, the transistor TRnx3 is deactivated by the signal WR.

[0397] When the write operation is executed, the signal level of the signal WR is set to an "H" level. When the read operation is executed, the signal level of the signal WR is set to an "L" level.

[0398] The voltage value of the voltage VI is controlled in accordance with the operation of the memory cell array 100. When the read operation is executed, the voltage value of the voltage VI has, for example, a value in the range of 2.3 V to 2.5 V. When the write operation is executed, the voltage value of the voltage VI has, for example, a value in the range of 2.5 V to 2.8 V.

[0399] For example, the voltage value of the "H" level of the signal RD is, for example, 2.5 V to 2.8 V. The voltage value of the "L" level of the signal RD is, for example, 0 V.

[0400] The voltage value of the "H" level of the signal WR is, for example, 2.5 V to 4.5 V. The voltage value of the "L" level of the signal WR is, for example, 0 V.

[0401] For example, when the deletion operation is performed, the potential states of the signal RD, WE, and the terminals V1 and Vss can be set to the electrically floating state. However, in order to stabilize the operation, a certain voltage value can be supplied to the terminals V1 and Vss or the gates of the transistors TRn and TRp in the amplifying unit AMP.

[0402] (Operation Example)

[0403] The amplifying unit AMP in the amplifying circuit 152 operates in the following manner.

[0404] When the read operation is performed by the flash memory 1, the signal RD of the "H" level and the signal WR of the "L" level are supplied to each of the amplifying units AMP.

[0405] The transistor TRnx3 is turned off by the signal WR of the "L" level. The signal path of the transistor TRnx between the bit line contact CB and the bit line BL is blocked by the transistor TRnx3 in the off state.

[0406] The transistor TRnx1 and the transistor TRpx1 are turned on by the signal RD of the "H" level and the signal bRD of the "L" level.

[0407] The signal (hereinafter, also referred to as a cell signal) from the NAND string NS is supplied to the gates of the transistors TRnx2 and TRpx2 via the bit line contact CB and the node NDb. Either of the transistors TRnx2 and TRpx2 is turned on depending on the signal level of the cell signal.

[0408] In the case where the signal level of the cell signal is the "H" level, the transistor TRnx2 is turned on and the transistor TRpx2 is turned off. Thus, the ground terminal Vss is electrically connected to the node ND1 via the transistors TRnx1 and TRnx2 in the on state. The voltage Vss is supplied to the bit line BL via the transistors TRnx1 and TRnx2 in the on state and the node NDa.

[0409] In the case where the signal level of the cell signal is the "L" level, the transistor TRnx2 is turned off and the transistor TRpx2 is turned on. Thus, the voltage terminal V1 is electrically connected to the node NDa via the transistors TRpx1 and TRpx2 in the on state. The voltage V1 is supplied to the bit line BL via the transistors TRpx1 and TRpx2 in the on state and the node NDa.

[0410] Thus, when the read operation is performed, the cell signal from the NAND string is the signal level corresponding to the voltage value V1 or the voltage value Vss, and is output to the bit line BL.

[0411] Thus, when the amplification unit AMP performs the readout operation, the cell signal from the NAND string NS is amplified to a voltage value of about V1 or Vss, and thus can be supplied to the sense amplifier 150.

[0412] When the flash memory 1 performs the write operation, the signal RD at the "L" level and the signal WR at the "H" level are supplied to each amplification unit AMP.

[0413] The transistor TRnx1 is turned off by the signal RD at the "L" level, and the transistor TRpx1 is turned off by the signal bRD at the "H" level. By the transistors TRnx1 and TRpx1 in the off state, the signal path between the bit line BL via the nodes NDa and NDb and the bit line contact CB is blocked.

[0414] The transistor TRnx3 is turned on by the signal WR at the "H" level. The bit line BL is connected to the bit line contact CB via the transistor TRnx3 in the on state.

[0415] The signal of one bit of the plurality of bits constituting the write data is supplied to the corresponding bit line BL. The potential (signal level) of the bit line BL has a value corresponding to the signal ("0" or "1") of one bit. The potential of the bit line BL is applied to the bit line contact CB via the transistor TRnx3 in the on state.

[0416] Thus, the signal corresponding to the write data is supplied to the NAND string NS.

[0417] Thus, when the amplification unit AMP performs the write operation, the write data can be supplied to the NAND string NS.

[0418] The transistors TRnx1, TRnx2, TRnx3, TRpx1, and TRpx2 of the amplification unit AMP are provided in the TFT region 200.

[0419] (Structural Example)

[0420] Figure 17 is a cross-sectional view showing a structural example of the amplification unit in the flash memory of the present embodiment.

[0421] As shown in Figure 17 , the plurality of transistors TRnx1, TRnx2, TRnx3, TRpx1, and TRpx2 in the amplification unit AMP are provided on the plurality of semiconductor layers 300 in the TFT region 200.

[0422] The plurality of semiconductor layers 300 (300a-a, 300a-b, 300b) are provided in the region 200 above the memory cell array 100.

[0423] The conductive layer 40x is provided in a region between the memory cell array 100 and the semiconductor layer 300. The position of the semiconductor layer 300 in the Z direction is higher than the position of the conductive layer 40x in the Z direction.

[0424] The transistor TRnx1, TRnx2 is provided on the semiconductor layer 300a-a.

[0425] The 3 source / drain layers 30nx-a, 31nx-a, 33nx-a are provided in the semiconductor layer 300a-a. The conductive type of the source / drain layers 30nx-a, 31nx-a, 33nx-a is n-type.

[0426] The channel region 32nx1 of the transistor TRnx1 is provided in the semiconductor layer 300a-a between the 2 source / drain layers 31nx-a, 33nx-a. The channel region 32nx2 of the transistor TRnx2 is provided in the semiconductor layer 300a-a between the 2 source / drain layers 30nx-a, 33nx-a.

[0427] The 2 transistors TRnx1, TRnx2 share the 1 source / drain layer 33nx-a.

[0428] The source / drain layer 30nx-a is connected to a ground terminal Vss. For example, the source / drain layer 30nx-a extends in the X direction. The ground terminal Vss is connected to an end portion of the source / drain layer 30nx-a in the X direction.

[0429] The contact plug 49x3 is provided on the source / drain layer 31nx-a. The contact plug 49x3 is connected to the conductive layer (node NDa) 48x3.

[0430] The conductive layer (e.g., metal layer) 48x3 is provided above the semiconductor layer 300 in the Z direction. The conductive layer 48x3 is provided above the semiconductor layer 300 in the Z direction across between one end of the semiconductor layer 300a and one end of the semiconductor layer 300b in the Y direction.

[0431] The gate electrode 35nx1 of the transistor TRnx1 is provided above the channel region 32nx1 with the gate insulating layer 34 interposed therebetween. The contact plug 49ra is provided on the upper surface of the gate electrode 35nx2. The gate electrode 35nx1 is connected to the conductive layer 48ra via the contact plug 49ra. A signal RD is supplied to the conductive layer 48ra. For example, the conductive layer 48ra extends in the X direction.

[0432] The gate electrode 35nx2 of the transistor TRnx2 is provided above the channel region 32nx2 with the gate insulating layer 34 interposed therebetween. The contact plug 49x1 is provided on the upper surface of the gate electrode 35nx2. The gate electrode 35nx2 is connected to the conductive layer 48x1 via the contact plug 49x1. The conductive layer 48x1 is connected to the conductive layer 40x below the semiconductor layer 300 via the contact plug 49x2, the semiconductor layers 300a-b (regions 31nx-b), and the contact plug 41x1.

[0433] The transistors TRpx1 and TRpx2 are provided over the semiconductor layer 300b. Three source / drain layers 30px, 31px, and 33px are provided in the semiconductor layer 300b. The source / drain layers 30px, 31px, and 33px are of p-type.

[0434] The channel region 32px1 of the transistor TRpx1 is provided in the semiconductor layer 300b between the two source / drain layers 31px and 33px. The channel region 32px2 of the transistor TRpx2 is provided in the semiconductor layer 300b between the two source / drain layers 30px and 33px.

[0435] The two transistors TRpx1 and TRpx2 share the one source / drain layer 33px.

[0436] The source / drain layer 30px is connected to the power supply terminal V1. For example, the source / drain layer 30px extends in the X direction. The power supply terminal V1 is connected to the end portion of the source / drain layer 30px in the X direction.

[0437] The contact plug 49x4 is provided on the source / drain layer 31px. The contact plug 49x4 is connected to the conductive layer 48x3 (node NDa). Thus, the source / drain layer 31px of the transistor TRpx2 is connected to the source / drain layers 31nx-a of the transistor TRnx2.

[0438] The gate electrode 35px1 of the transistor TRpx1 is provided above the channel region 32px1 with the gate insulating layer 34 interposed therebetween. The contact plug 49rb is provided on the upper surface of the gate electrode 35px1. The gate electrode 35px1 is connected to the conductive layer 48rb via the contact plug 49rb. The signal bRD is supplied to the conductive layer 48rb. For example, the conductive layer 48rb extends in the X direction.

[0439] The gate electrode 35px2 of the transistor TRpx2 is provided over the channel region 32px2 with the gate insulating layer 34 interposed therebetween. The contact plug 49x5 is provided on the upper surface of the gate electrode 35px2. The gate electrode 35px2 is connected to the conductive layer 48x2 via the contact plug 49x5. The conductive layer 48x2 is connected to the conductive layer (node NDb) 40x under the semiconductor layer 300 via the contact plug 49x6, the conductive layer (e.g., the semiconductor layer) 38, and the contact plug 41x2. Thus, the gate electrode 35px2 of the transistor TRpx2 is connected to the gate electrode 35nx2 of the transistor TRnx2 via the conductive layer 40x under the semiconductor layer 300.

[0440] The semiconductor layers 300a-b are adjacent to the semiconductor layer 300a-a in the Y direction.

[0441] The transistor TRnx3 is provided over the semiconductor layer 300a-b.

[0442] The two source / drain layers 30nx-b and 31nx-b of the transistor TRnx3 are provided in the semiconductor layer 300. The conductive type of the source / drain layers 30nx-b and 31nx-b is n-type.

[0443] The channel region 32nx3 of the transistor TRnx3 is provided in the semiconductor layer 300a-b between the two source / drain layers 30nx-b and 31nx-b.

[0444] The gate electrode 35nx3 of the transistor TRnx3 is provided over the channel region 32nx3 with the gate insulating layer 34 interposed therebetween. The contact plug 49w is provided on the upper surface of the gate electrode 35nx3. The gate electrode 35nx3 is connected to the conductive layer 48w via the contact plug 49w. A signal WR is supplied to the conductive layer 48w. For example, the conductive layer 48w extends in the X direction.

[0445] The contact plug 41x1 is provided under the lower surface of the source / drain layer 31nx3 in the Z direction.

[0446] Thus, the source / drain layer 31nx-b of the transistor TRnx is connected to the conductive layer 40x via the contact plug 41x1.

[0447] The contact plug 49x2 is provided on the upper surface of the source / drain layer 31nx-b. The contact plug 49x2 connects the conductive layer 48x1 to the conductive layer 40x via the semiconductor layer 300a-b and the contact plug 41x1.

[0448] The conductive layer 43 is provided over the conductive layers 48 (48x1, 48x2, 48x3, 48ra, 48rb, 48w, 48x4) in the Z direction.

[0449] The conductive layer 43 functions as a bit line BL.

[0450] The bit line BL is connected to the conductive layer 48x3 via the contact plug 45a. Thus, the bit line BL is electrically connected to the source / drain layer 31nx-a of the transistor TRnx1 and the source / drain layer 31px of the transistor TRpx1.

[0451] The bit line BL is connected to the conductive layer 48x4 via the contact plug 45b. Thus, the bit line BL is connected to the source / drain layer 30nx-b of the transistor TRnx3.

[0452] The conductive layer 40x is connected to the bit line contact CB. Thus, the gate electrode 35nx2 of the transistor TRnx2, the gate electrode 35px2 of the transistor TRpx2, and the source / drain layer 31nx-b of the transistor TRnz3 are connected to the corresponding NAND string NS.

[0453] Figure 17 In this case, the transistors TRnx1, TRnx2, TRnx3, TRpx1, TRpx2 of the amplification unit AMP are provided within one layer (hierarchy, wiring layer).

[0454] However, the amplification unit AMP can include a plurality of transistors TRn, TRp within multiple layers.

[0455] Figure 18 is a cross-sectional view showing a structure example of an amplification unit in a flash memory of the present embodiment.

[0456] As shown in Figure 18 , the amplification unit AMP includes a plurality of transistors TRnx (TRnx1, TRnx2, TRnx3) within a layer Ly1 and a plurality of transistors TRpx (TRpx1, TRpx2) within a layer Ly2.

[0457] The plurality of transistors TRnx1, TRnx2, TRnx3 within the layer Ly1 are all n-type transistors.

[0458] The plurality of transistors TRpx1, TRpx2 within the layer Ly2 are all p-type transistors.

[0459] The layer Ly2 is provided below the layer Ly1 in the Z direction.

[0460] The plurality of plugs 41z (41z1, 41z2), 42z (42z1, 42z2, 42z3, 42z4) and the conductive layer 48z (48z1, 48z2, 48z3) are provided within a region between the semiconductor layer 300a within the layer Ly1 and the semiconductor layer 300b within the layer Ly2.

[0461] The source / drain layer 31px-a of the transistor TRpx1 is connected to the source / drain layer 31nx-a of the transistor TRnx1 via the contact plug 42z1, the conductive layer 48z1, and the contact plug 41z1. The source / drain layer 31nx-a is connected to the contact plugs 45a, 49x3, and the conductive layer 48z.

[0462] Thus, the source / drain layer 31px of the transistor TRpx1 is connected to the bit line BL via the source / drain layer 31nx-a of the transistor TRnx1.

[0463] The gate electrode 35px1 of the transistor TRpx1 is connected to the conductive layer 48z2 via the contact plug 42z2. The conductive layer 48z2 extends in the X direction. The signal bRD is supplied to the conductive layer 48z2.

[0464] The gate electrode 35px2 of the transistor TRpx2 is connected to the conductive layer 48z3 via the contact plug 42z3.

[0465] The conductive layer 48z3 is electrically connected to the source / drain layer 31nx-b of the transistor TRnx3 via the contact plug 41z2.

[0466] The conductive layer 48z3 is connected to the conductive layer 40x via the contact plug 42z4, the conductive layer (e.g., semiconductor layer) 39b, and the contact plug 49z.

[0467] Thus, the source / drain layer 31nx-b of the transistor TRnx3, the gate electrode 35nx1 of the transistor TRnx2, and the gate electrode 35px1 of the transistor TRpx2 are connected to the corresponding NAND string NS via the conductive layer 40x.

[0468] Thus, the amplification unit AMP is formed using the plurality of elements TRn, TRp provided in different layers Ly1, Ly2.

[0469] As described above, the amplification circuit 152 can be formed using transistors (e.g., thin film transistors) in the region 200 above the memory cell array 100.

[0470] (c1) Modification Example

[0471] Reference Figure 19 and Figure 20 A modification example of the flash memory of the present embodiment will be described.

[0472] Figure 19 is a cross-sectional view illustrating an example of a modification example of the flash memory of the present embodiment.

[0473] As shown in Figure 19 , the shielding layer 45 can also be provided between the memory cell array 100 and the TFT region 200.

[0474] For example, the shield layer 45 is provided below the lowermost layer (for example, the conductive layer 40) in the TFT region 200 in the Z direction.

[0475] The shield layer 45 is separate from the constituent elements of the TFT region 200 and the constituent elements of the memory cell array 100. For example, the shield layer 45 has an electrically floating state. However, a voltage having a certain voltage value can be applied to the shield layer 45.

[0476] Thus, it is possible to suppress the noise influence between the memory cell array 100 and the TFT region 200.

[0477] Figure 20 is a cross-sectional view showing an example of a variation of the flash memory of the present embodiment.

[0478] As shown in Figure 20 , the SG decoder 142A can also be provided above the memory cell array 100 in the Z direction across two blocks BLKa and BLKb adjacent in the Y direction.

[0479] Furthermore, the connection relationship and the structure of the elements TRp and TRp and the wirings SGD and SGS in this example are substantially the same as those of the example of Figure 14 Here, the difference between the structure of Figure 20 and the structure of Figure 14 will be described.

[0480] The address decoding circuit 60 includes a plurality of transistors TRn and TRp.

[0481] The plurality of transistors TRn (TRn0a, TRn1a) are provided on the semiconductor layer 300 above the block BLKa in the Z direction.

[0482] The plurality of transistors TRp (TRp0a, TRp1a) are provided on the semiconductor layer 300 above the block BLKb in the Z direction.

[0483] Thus, the elements TRn and TRp constituting the address decoding circuit 60 are provided in the TFT region 200 above the memory cell array 100 in a region across the plurality of blocks BLKa and BLKb.

[0484] The drain side SG selector 61D1 is connected to the drain side selection gate line SGD within the block BLKa. The drain side SG selector 61D1 includes an n-type transistor TRnd1 and a p-type transistor TRpd1. Each of the transistors TRnd1 and TRpd1 is provided on the semiconductor layer 300 similarly to the example of Figure 14 .

[0485] The drain-side SG selector 61D2 is connected to the drain-side select gate line SGD within block BLKb. The drain-side SG selector 61D2 includes an n-type transistor TRnd2 and a p-type transistor TRpd2. Each transistor TRnd2 and TRpd2 is connected to... Figure 14 Similarly, the example is set on semiconductor layer 300.

[0486] The source-side SG selector 61S is connected to the source-side select gate line SGS in block BLKa and the source-side select gate line SGS in block BLKb.

[0487] The source-side SG selector 61S spans the boundary between the two blocks BLKa and BLKb, and is positioned above the stack 700 in the Z direction.

[0488] in this way, Figure 20 In the example, the drain-side SG selectors 61D1 and 61D2 are set independently in each of the multiple BLK blocks, while the source-side SG selector 61S is shared by the multiple BLK blocks.

[0489] The SG decoder 142A controls the selection and deselection of multiple select gate lines SGD and SGS of two adjacent blocks BLKa and BLKb.

[0490] As a result, the number of components in the TFT area can be reduced. In addition, the space margin for wiring and routing in the TFT area is increased.

[0491] Furthermore, multiple components of the SG decoder can also be like... Figure 18 The components of the amplification unit are typically arranged in multiple layers along the Z-direction.

[0492] (d1) Manufacturing method

[0493] Reference Figures 21 to 31 The manufacturing method of the flash memory according to this embodiment will be described.

[0494] use Figures 21 to 23 One step of the manufacturing method of the flash memory in this embodiment will be described. Figure 21 This is a top view of one step of the manufacturing method of the flash memory according to this embodiment. Figure 22 and Figure 23 This is a schematic cross-sectional view showing one step of the manufacturing method of the flash memory according to this embodiment. Figure 22 It is along Figure 21 A cross-sectional view along line AA. Figure 23 It is along Figure 23 A cross-sectional view of the BB line.

[0495] like Figures 21 to 23As shown, a plurality of stacks 700 is formed over the substrate 80 by a well-known technique. As described above, the stack 700 includes a plurality of semiconductor layers 70 and a plurality of insulating layers 71. Within the stack 700, the semiconductor layers 70 and the insulating layers 71 are alternately stacked in the Z direction.

[0496] The plurality of stacks 700 is arranged in the X direction, for example, with a pitch of a size Da. The interval between the stacks 700 in the X direction is, for example, a size Db. The stack 700 has a size Dc in the X direction, for example.

[0497] A plurality of storage layers 51 and a plurality of conductive layers 50 is formed over the plurality of stacks 700 by a well-known technique. The storage layers 51 and the conductive layers extend in the X direction. The storage layers 51 and the conductive layers 50 span the plurality of stacks 700. The storage layer 51 is a stacked film including a charge storage layer (e.g., a silicon nitride film), for example.

[0498] The plurality of conductive layers 50 includes word lines WL and select gate lines SGD, SGS, and the like. A string selection line (not shown) is formed in each stack 700 independently, for example.

[0499] A step structure (not shown) is formed over the substrate 80 in a manner connected to the stack 700, for example.

[0500] An insulating layer 90 is formed over the stack 700 and the conductive layer 50.

[0501] A plurality of contact plugs (not shown) is formed in the insulating layer 90 by a well-known technique. The plurality of contact plugs is connected to the semiconductor layer 70 or the conductive layer 50.

[0502] A plurality of conductive layers (wiring) 40 is formed over the insulating layer 90 by a well-known technique.

[0503] An insulating layer 91 is formed over the insulating layer 90, the conductive layer 40, and the contact plug by a well-known technique.

[0504] After a planarization process is performed on the upper surface of the insulating layer 91, a contact plug 41 is formed in the insulating layer 91 by a well-known technique.

[0505] A semiconductor layer 399, an insulating layer 340, and a conductive layer 350 are sequentially formed over the insulating layer 91 (and the contact plug 41).

[0506] In addition, an n-type or p-type dopant can be added to the semiconductor layer 399. The n-type semiconductor layer 399 and the p-type semiconductor layer 399 can be formed over the insulating layer 91 by a well-known technique.

[0507] A plurality of mask layers 92 are formed on the conductive layer 350 in the Z direction by well-known photolithography and etching. The mask layers 92 have a quadrangular pattern extending in the Y direction.

[0508] The plurality of mask layers 92 are arranged in the X direction at a pitch Dlx. For example, the pitch Dlx of the plurality of mask layers 92 is set to be substantially the same size as the pitch Da of the multilayer body 700.

[0509] The interval D2x between the mask layers 93 in the X direction is set to be substantially the same size as the interval Db between the multilayer bodies 700 in the X direction.

[0510] For example, the size D3x of the mask layers in the X direction is set to be substantially the same size as the size Dc of the multilayer bodies 700 in the X direction.

[0511] Using Figure 24 and Figure 25 , one step of the manufacturing method of the flash memory of the present embodiment will be described.

[0512] Figure 24 and Figure 25 are cross-sectional views showing one step of the manufacturing method of the flash memory of the present embodiment. Figure 24 is a cross-sectional view along the Y direction of the cross section of the array of memory cells (Y-Z plane). Figure 25 is a cross-sectional view along the X direction of the cross section of the array of memory cells (X-Z plane).

[0513] As shown in Figure 24 and Figure 25 , the conductive layer, the insulating layer, and the semiconductor layer are etched based on the shape of the mask layer 92.

[0514] Thus, the semiconductor layer 300, the conductive layer 351, and the insulating layer 341 are formed in the TFT region 200 above the array of memory cells 100. The semiconductor layer 300 has a planar shape that is quadrangular when viewed in the Z direction. For example, the semiconductor layer 300 extends in the Y direction.

[0515] Thus, the conductive layer 351, the insulating layer 341, and the semiconductor layer 300 are uniformly processed by a common etching process.

[0516] Thus, the positions of the ends of the etched conductive layer 351 and the insulating layer 341 in the X direction are aligned with the positions of the ends of the etched semiconductor layer 300 in the X direction (and the Y direction).

[0517] The size of the conductive layer 351 and the insulating layer 341 in the X direction is substantially equal to the size D3 of the semiconductor layer 300 in the X direction.

[0518] The spacing D1 of the multiple semiconductor layers 300 is substantially equal to the spacing Da of the stack 700. The spacing D2 between adjacent semiconductor layers 300 in the X direction is substantially equal to the space Db between adjacent stacks 700 in the X direction. The size D3 of the semiconductor layer in the X direction is substantially equal to the size Dc of the stack.

[0519] Because etching occurred during the etching process, the components below the semiconductor layer 300 in the Z direction were etched.

[0520] As a result, the X-direction end of the contact plug 41 is etched. Consequently, the upper portion of the contact plug 41 (the portion of the contact plug 41 on the semiconductor layer 300 side) is etched. In this case, the position of the X-direction end of the upper portion of the contact plug 41 is aligned with the position of the X-direction end of the semiconductor layer 300. The dimension D3z of the upper portion of the contact plug 41 in the X direction is substantially equal to the dimension D3 of the semiconductor layer 300.

[0521] use Figure 26 One step of the manufacturing method of the flash memory in this embodiment will be described.

[0522] Figure 26 This is a schematic cross-sectional view showing one step of the manufacturing method of the flash memory according to this embodiment. Figure 26 It is a cross-sectional view along the Y direction (YZ plane) of the memory cell array.

[0523] like Figure 26 As shown, in the region where the gate electrode of the transistor is formed, a mask layer 92A is formed above the semiconductor layer 300 in the Z direction using well-known techniques.

[0524] Based on the shape of mask 92A, the conductive layer and the insulating layer are etched. As a result, the gate electrode 35 and the gate insulating layer 34 are formed on the semiconductor layer 300.

[0525] use Figures 27 to 29 One step of the manufacturing method of the flash memory in this embodiment will be described.

[0526] Figure 27 This is a top view of one step of the manufacturing method of the flash memory according to this embodiment. Figure 28 and Figure 29 This is a schematic cross-sectional view showing one step of the manufacturing method of the flash memory according to this embodiment. Figure 28 It is along Figure 27 A cross-sectional view along line AA. Figure 29 (a) is along Figure 27 A cross-sectional view of the BB line. Figure 29 (b) is along Figure 27A cross-sectional view of the C-C line of FIG. 10.

[0527] As shown in FIG. 11, the insulating layer is formed on the semiconductor layer 300, the gate insulating layer 34, the gate electrode 35, and the insulating layer 91. Etching back is selectively performed on the formed insulating layer. Figures 27 to 29

[0528] By this, the side wall insulating layer 39 remains on the side surfaces of the gate electrode 35 in the X direction and the Y direction. At this time, the side wall insulating layer 39 remains on the side surfaces of the semiconductor layer 300.

[0529] Using Figure 30 and Figure 31 , one step of the manufacturing method of the flash memory of the present embodiment will be described.

[0530] Figure 30 and Figure 31 is a schematic cross-sectional step view showing one step of the manufacturing method of the flash memory of the present embodiment. Figure 30 is a cross-sectional view of the same region as the A-A line of FIG. 12. Figure 27 (a) of FIG. 13 is a cross-sectional view of the same region as the cross section along the B-B line of FIG. 12. Figure 31 (b) of FIG. 13 is a cross-sectional view of the same region as the cross section along the C-C line of FIG. 12. Figure 27 Figure 31 As shown in FIG. 14, and FIG. 15, the ion implantation is performed on the semiconductor layer 300 using the gate electrode 35 as a mask. Figure 27 For example, when ions of n-type dopant are implanted into the semiconductor layer 300, the semiconductor layer 300 in the region for implantation of p-type dopant is covered with the mask layer 93. In the region for implantation of n-type dopant, the semiconductor layer 300 is exposed. Thus, n-type semiconductor regions (e.g., source / drain layers) 30, 31 are formed in the semiconductor layer 300.

[0531] Figure 30 When ions of p-type dopant are implanted, the semiconductor layer in the region for implantation of n-type dopant is covered with the mask layer. In the region for implantation of p-type dopant, the semiconductor layer 300 is exposed. Figure 31 By this, n-type source / drain layers 30, 31 (and p-type source / drain layers) are formed in the semiconductor layer 300.

[0532] After that, an insulating layer (not shown) is formed on the semiconductor layer 300, the gate insulating layer 34, the gate electrode 35, and the side wall insulating layer 39. By this, the insulating layer (not shown) is embedded into the spaces between the semiconductor layers 300 and the spaces between the gate electrodes 35.

[0533]

[0534]

[0535] After that, an insulating layer (not shown) is formed on the semiconductor layer 300, the gate insulating layer 34, the gate electrode 35, and the side wall insulating layer 39. By this, the insulating layer (not shown) is embedded into the spaces between the semiconductor layers 300 and the spaces between the gate electrodes 35. ​​​​​

[0536] A contact plug (not shown) is formed in the insulating layer formed by a well-known technique. A conductive layer (not shown) is formed on the insulating layer and the contact plug by a well-known technique. The contact plug and the conductive layer formed have a pattern / layout corresponding to the configuration of the peripheral circuit to be formed.

[0537] Through the above manufacturing steps, in the TFT region 200 above the memory cell array 100, a plurality of circuits of the flash memory of the present embodiment are formed.

[0538] (e1) Summary

[0539] As described above, in the flash memory of the present embodiment, a plurality of transistors TRn, TRp are provided above the memory cell array 100 in the Z direction.

[0540] The flash memory 1 of the present embodiment has a peripheral circuit for controlling the operation of the memory cell array 100 in a space above the memory cell array 100.

[0541] Thus, the flash memory 1 of the present embodiment can suppress an increase in chip size compared to a structure in which the peripheral circuit is disposed on a semiconductor region in the substrate.

[0542] In addition, in a case where the flash memory has a memory cell array having a three-dimensional structure, as the number of layers in the memory cell array increases, the number of wirings in the memory cell array tends to increase.

[0543] In the flash memory of the present embodiment, if the peripheral circuit is provided above the memory cell array, the restrictions related to the pitch between wirings, the interval between wirings, the length of wirings, and the width of wirings in a two-dimensional plane parallel to the surface of the substrate can be relaxed.

[0544] In the flash memory of the present embodiment, the area for wiring can be reduced.

[0545] Thus, in the flash memory of the present embodiment, the wiring between the memory cell array and the peripheral circuit can be simplified.

[0546] The flash memory of the present embodiment can suppress an open circuit or a short circuit of the wirings by relaxing the restrictions related to the wirings.

[0547] As a result, the flash memory of the present embodiment can improve the manufacturing yield. Consequently, the flash memory of the present embodiment can suppress an increase in manufacturing cost.

[0548] As described above, the storage device of the present embodiment can improve the quality.

[0549] (2) Second Embodiment

[0550] Referring to Figures 32 to 49 The memory device of Embodiment 2 will be described.

[0551] (a2) Configuration Example

[0552] In a flash memory, each memory cell MC can store one bit or more of data based on a correlation established between the stored data and a plurality of threshold voltages that can be obtained by one memory cell.

[0553] Referring to Figure 32 The relationship between the data stored in the memory cell and the threshold voltage distribution of the memory cell MC will be described.

[0554] Here, a case where one memory cell MC can store 3 bits of data will be described. Hereinafter, the 3 bits of data will be referred to as a lower bit, a middle bit, and an upper bit in order from the lower bit. A set of the lower bits of a plurality of memory cells MC belonging to the same cell group CU will be referred to as a lower page (or lower data), a set of the middle bits thereof will be referred to as a middle page (or middle data), and a set of the upper bits thereof will be referred to as an upper page (or upper data). A memory cell that can store 3 bits of data will be referred to as a TLC (Triple level cell).

[0555] In the case where one memory cell MC can store 3 bits of data, 3 pages are allocated to one word line WL (one cell group CU). A "page" can be defined as a portion of a memory space formed in a cell group CU. Writing and reading of data can be performed one by one in pages or in cell groups CU.

[0556] Figure 32 is a diagram showing data that can be stored in each memory cell MC, a threshold voltage distribution, and a voltage used at the time of reading data.

[0557] As Figure 32 shown, in the case where one memory cell MC can store 3 bits of data, the memory cell MC can obtain 8 states according to the threshold voltage. The 8 states (also referred to as written states) will be referred to as an "Er" state, an "A" state, a "B" state, a "C" state, a "D" state, an "E" state, an "F" state, and a "G" state in order from low to high threshold voltage.

[0558] The threshold voltage of the memory cell MC in the "Er" state is less than the voltage VAR, which corresponds to the deletion state of data. The threshold voltage of the memory cell MC in the "A" state is equal to or more than the voltage VAR and less than the voltage VBR (> VAR). The threshold voltage of the memory cell MC in the "B" state is equal to or more than the voltage VBR and less than the voltage VCR (> VBR). The threshold voltage of the memory cell MC in the "C" state is equal to or more than the voltage VCR and less than the voltage VDR (> VCR). The threshold voltage of the memory cell MC in the "D" state is equal to or more than the voltage VDR and less than the voltage VER (> VDR). The threshold voltage of the memory cell MC in the "E" state is equal to or more than the voltage VER and less than the voltage VFR (> VER). The threshold voltage of the memory cell MC in the "F" state is equal to or more than the voltage VFR and less than the voltage VGR (> VFR). The threshold voltage of the memory cell MC in the "G" state is equal to or more than the voltage VGR and less than the voltage VREAD (> VGR).

[0559] Of the eight states thus distributed, the "G" state is the state having the highest threshold voltage. Each state has a range of voltage values (threshold voltage distribution) associated with the corresponding data. Hereinafter, the "Er" state is referred to as the deletion state. The "A" to "G" states are referred to as the program states.

[0560] Hereinafter, the voltages VAR to VGR are also referred to as determination levels or readout levels. The voltages VAR to VGR are also collectively referred to as the voltage VCGR.

[0561] The voltage VREAD is a voltage applied to a word line (non-selected word line) WL that is not a target of readout when a readout operation is performed. In the case where the voltage VREAD is applied to the gate (word line) of the memory cell MC, the memory cell MC is turned on regardless of the stored data of the memory cell MC.

[0562] To verify the writing of data (hereinafter, referred to as program verification), the voltages VAV to VGV are set for each state. The voltage VAV is higher than the readout level VAR and is lower than the lower limit value of the expected threshold voltage distribution of the "A" state. The voltage VBV is higher than the readout level VBR and is lower than the lower limit value of the expected threshold voltage distribution of the "B" state. The voltage VCV is higher than the readout level VCR and is lower than the lower limit value of the expected threshold voltage distribution of the "C" state. The voltage VDV is higher than the readout level VDR and is lower than the lower limit value of the expected threshold voltage distribution of the "D" state. The voltage VEV is higher than the readout level VER and is lower than the lower limit value of the expected threshold voltage distribution of the "E" state. The voltage VFV is higher than the readout level VFR and is lower than the lower limit value of the expected threshold voltage distribution of the "F" state. The voltage VGV is higher than the readout level VGR and is lower than the lower limit value of the expected threshold voltage distribution of the "G" state.

[0563] Hereinafter, the voltages VAV ~ VGV are also referred to as verification levels, respectively.

[0564] The threshold voltage distribution is realized by writing 3-bit (3-page) data including the lower bit, the middle bit, and the upper bit to the memory cells MC in the memory cell array 100. An example of the relationship between the state of the threshold voltage and the lower / middle / upper bits is as follows.

[0565] "Er" state: "111" (labeled in the order of "upper / middle / lower")

[0566] "A" state: "110"

[0567] "B" state: "100"

[0568] "C" state: "000"

[0569] "D" state: "010"

[0570] "E" state: "011"

[0571] "F" state: "001"

[0572] "G" state: "101"

[0573] Thus, among data corresponding to 2 states adjacent on the threshold voltage distribution, only 1 bit of the 3 bits changes.

[0574] The readout of the lower bit can use a voltage corresponding to the boundary point at which the value ("0" or "1") of the lower bit changes. The readout of the upper bit can use a voltage corresponding to the boundary point at which the value of the upper bit changes. The readout of the middle bit can use a voltage corresponding to the boundary point at which the value of the middle bit changes.

[0575] In the example of Figure 32 , the readout of the lower page is performed using, as the readout voltage, the voltage VAR that distinguishes the "Er" state from the "A" state, and the voltage VER that distinguishes the "D" state from the "E" state.

[0576] The readout of the middle page is performed using, as the readout voltage, the voltage VBR that distinguishes the "A" state from the "B" state, the voltage VDR that distinguishes the "C" state from the "D" state, and the voltage VFR that distinguishes the "E" state from the "F" state.

[0577] The readout of the upper page is performed using, as the readout voltage, the voltage VCR that distinguishes the "B" state from the "C" state, and the voltage VGR that distinguishes the "F" state from the "G" state.

[0578] The memory cell MC in the deletion state is specified by using the readout of the voltage VAR. Hereinafter, the readout (determination) using the voltage VAR is also referred to as AR readout. Similarly, the readout using each of the voltages VBR, VCR, VDR, VER, VFR, and VGR is referred to as BR readout, CR readout, DR readout, ER readout, FR readout, and GR readout, respectively.

[0579] Further, in the storage device of the present embodiment, one memory cell MC can be capable of storing data of 2 bits or less, or can be capable of storing data of 4 bits or more. A memory cell capable of storing data of 1 bit is referred to as an SLC (Single Level Cell). A memory cell capable of storing data of 2 bits is referred to as an MLC (Multi Level Cell). A memory cell capable of storing data of 4 bits is referred to as a QLC (Quadruple Level Cell).

[0580] The write and read of data are performed collectively on a plurality of memory cells belonging to the cell group CU.

[0581] In the write operation, the threshold voltage of the memory cell is shifted within the range of the threshold voltage distribution associated with the data to be written by applying a plurality of program voltages to the selected word line.

[0582] In the write operation, the threshold voltage of the memory cell MC is verified to be within the threshold voltage distribution corresponding to the data to be written by using the voltages (hereinafter, also referred to as verify levels) VAV, VBV, VCV, VDV, VEV, and VFV for verifying the threshold voltage of the memory cell associated with each state.

[0583] Thus, the data to be written is written to each memory cell MC within the selected cell group CU.

[0584] In the present embodiment, the data written to each memory cell MC is referred to as cell data. The write data DAT from the storage controller 2 is a collection of a plurality of cell data.

[0585] The flash memory 1 of the present embodiment writes data to the memory cell MC by the following configuration.

[0586] Figure 33 is a diagram showing the internal configuration of the flash memory of the present embodiment.

[0587] As shown in Figures 34 to 49 , the flash memory 1 of the present embodiment includes a circuit (function) 191 for evaluating the characteristics of a plurality of memory cells MC within the memory cell array 100.

[0588] The evaluation circuit 191 evaluates the writing speed of the plurality of memory cells located at the address of the writing target when the writing operation is performed. The evaluation circuit 191 can perform detection of the amount of shift of the threshold value of the memory cell after application of a program voltage of a certain size, and calculation processing of the detection result, to obtain the writing speed.

[0589] The flash memory 1 of the present embodiment includes a circuit (function) 192 that calculates the voltage value of the program voltage to be used in the writing operation.

[0590] The circuit (hereinafter, prediction circuit) 192 calculates the voltage value of a plurality of program voltages based on the data (writing state) written to each memory cell MC and the writing speed of each memory cell MC. Based on the calculation result, the prediction circuit 192 can predict a more appropriate voltage value for each of the plurality of program voltages to be used in the writing operation.

[0591] For example, the evaluation circuit 191 and the prediction circuit 192 are provided in the sequencer 190. However, the evaluation circuit 191 and the prediction circuit 192 can also be provided outside the sequencer 190. In addition, the memory controller 2 can have the evaluation circuit 191 and the prediction circuit 192 (or their functions).

[0592] For example, the sense amplifier 150 has an information storage circuit (register or latch circuit) 159. The information storage circuit 159 can store information related to the evaluation result (for example, the writing speed) of each memory cell by the evaluation circuit 191. Hereinafter, information related to the characteristics of the memory cell such as the writing speed of each memory cell is referred to as characteristic information. The information storage circuit 159 can also store information related to the writing operation other than the characteristic information.

[0593] The sense amplifier 150 includes a plurality of latch circuits. Each latch circuit stores cell data. Each latch circuit can hold the result (for example, the verification result and the read result, etc.) of the selection of the on and off of the cell with respect to a certain determination voltage.

[0594] For example, the drive circuit 160 has an information storage circuit (register or latch circuit) 161. The information storage circuit 169 can store information related to the prediction result of the voltage value of the program voltage by the prediction circuit 192. Hereinafter, information related to the voltage value of the program voltage is referred to as voltage information. The information storage circuit 159 can also store information related to the writing operation other than the voltage information.

[0595] In addition, the sequencer 190 can also have a circuit that stores the characteristic information and the voltage information. In this case, the sequencer 190 controls the operation of the sense amplifier 150 and the drive circuit 160 based on each information in the writing operation.

[0596] The flash memory 1 of the present embodiment calculates the voltage value of the program voltage to be used in the write operation, based on the cell data of each memory cell and the characteristics of the memory cell, and the like. Thus, the flash memory of the present embodiment can set the voltage value of the program voltage to a more appropriate value in accordance with the characteristics of the memory cell.

[0597] As a result, the flash memory 1 of the present embodiment can shorten the period of the write operation.

[0598] As described above, the flash memory of the present embodiment can improve the operation characteristics.

[0599] (b2) Operation Example

[0600] Reference Figures 34 to 39 An operation example of the flash memory of the present embodiment will be described.

[0601] (b2-1) Operation Example 1

[0602] Reference Figure 34 Operation Example 1 of the flash memory of the present embodiment will be described.

[0603] Figure 35 is a flowchart showing a sequence of the write operation of the flash memory of the present embodiment in Operation Example 1 (hereinafter, referred to as a write sequence).

[0604] Figure 36 is a schematic diagram showing the state within the memory cell array of the flash memory when the write operation is performed.

[0605] Figure 36 is a timing chart for explaining the application of a voltage to the selected word line when the write sequence of the flash memory of the present embodiment is performed in Operation Example 1. In Figure 37 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to the voltage value.

[0606] Figure 38 , Figure 39 and Figure 34 are diagrams for explaining the write sequence of the flash memory of the present embodiment.

[0607] <S00>

[0608] As shown in Figure 35 , in a case where the host device (not shown) requests the write of data to the storage system SYS, the storage controller 2 transmits the write instruction CMD, the address information ADD, and the write data DAT to the flash memory 1 of the present embodiment.

[0609] In step S00, the flash memory 1 of the present embodiment receives the write instruction, the address information, and the write data from the storage controller 2.

[0610] Thus, the flash memory 1 starts the write sequence.

[0611] As shown in FIG. 1, the memory cell array of the flash memory 1 has, for example, a structure in which a plurality of memory cells MC are arranged in a matrix of rows and columns. Figures 2 to 5 Figure 35

[0612] The word line (hereinafter, referred to as a selected word line) WL-s of the plurality of word lines WL-s, WL-u based on the address information (selection address) ADD is made into a selected state. The word line (hereinafter, referred to as a non-selected word line) WL-u other than the selected word line is made into a non-selected state.

[0613] The drain side selection gate line SGD-s based on the address information ADD is made into a selected state. The source side selection gate line SGS-s based on the address information ADD is made into a selected state. The selection gate lines (not shown) of the other drain side and source side are made into non-selected states.

[0614] For example, any of the plurality of string selection lines SSL is made into a selected state based on the address information ADD. Thus, the stacked body 700 connected to the selected string selection line SSL is selected from among the plurality of stacked bodies 700.

[0615] In the example of FIG. 1, the plurality of memory cells MC-s connected to the selected word line WL-s within the selected stacked body 700 is selected. Within the selected stacked body 700, the memory cells MC-s that are the write targets are arranged in the Z direction. Hereinafter, the memory cells MC-s connected to the selected word line WL-s are referred to as selected cells MC-s. Figure 36 The memory cells MC connected to the non-selected word line WL-u are made into a non-selected state. Hereinafter, the memory cells connected to the non-selected word line WL-u are referred to as non-selected cells.

[0616] Thus, in the memory cell array, the plurality of memory cells MC-s is selected based on the address information.

[0617] The write data is stored in the sense amplifier 150. The sense amplifier 150 includes a plurality of latch circuits (not shown). One latch circuit is associated with one bit line. When the write sequence is executed, each latch circuit can store the cell data written to the selected cells corresponding to each bit line.

[0618] <S20>

[0619] When the flash memory 1 of the present embodiment executes the write sequence, in step S20, an evaluation action is executed.

[0620] The evaluation action is a process for evaluating the write characteristics of the memory cells (selected cells MC-s).

[0621] Thus, in the memory cell array, the plurality of memory cells MC-s is selected based on the address information.​​

[0622] In this embodiment, the write speed of the select cell MC-s after the programming voltage is applied is measured and evaluated as a write characteristic. The write speed is an indicator based on the amount of shift that occurs at the threshold voltage of the memory cell after the programming voltage is applied.

[0623] As a flash memory, the write speed of multiple select cells MC-s varies due to the differences in characteristics among the multiple cells within the cell array 100. These differences in cell characteristics are caused by variations in the thickness of the tunneling insulating film and the shape of the cells.

[0624] As a result, even when the same programming voltage is applied to multiple selection units MC-s, the threshold voltage distribution of the set (unit group CU) of the selection units MC-s has a certain expansion.

[0625] like Figure 37 As shown, during the evaluation operation, in step S201, a programming voltage (hereinafter referred to as the evaluation programming voltage) Vest with a voltage value V0 is applied to the select word line WL-s. For example, the voltage value V0 is the voltage value used for programming the "A" state (more specifically, the initial voltage value).

[0626] For example, evaluation circuit 191 performs control to apply the evaluation programming voltage Vest.

[0627] Therefore, the threshold voltages of the multiple selection units MC-s located at the address of the data being written shift in the positive direction according to the writing speed of each selection unit MC-s.

[0628] Figure 37 This is a graph showing the distribution of threshold voltages in memory cells when an evaluation operation is performed during the write sequence of the flash memory in this embodiment.

[0629] In multiple selection units MC-s, the threshold voltage of the memory cell is shifted to a state above "A" and the memory cell is set to a programmable state by the potential control of the bit line BL.

[0630] When performing the evaluation action in the write sequence, the evaluation programming voltage Vest is applied, such as... Figure 38 As shown in (a), the threshold voltage of the select cell (hereinafter also referred to as the programmable cell) set to the programmable state among the multiple select cells varies to a value corresponding to the characteristics (write speed) of each memory cell.

[0631] This results in a threshold voltage distribution with a certain extent (voltage range) 999.

[0632] Further, the selection unit that should maintain the erased state is set to the inhibit programming state by the potential control of the bit line BL. Thus, the variation of the threshold voltage of the selection unit that should maintain the erased state (hereinafter, also referred to as the inhibit programming unit) is suppressed.

[0633] By applying the evaluation programming voltage Vest, the threshold voltage of the certain memory cell becomes the voltage value Vtha, and the threshold voltage of the other memory cell becomes the voltage value Vthb. In the case where the voltage value Vtha is higher than the voltage value Vthb, the write speed of the certain memory cell is greater than the write speed of the other memory cell. In the case where the voltage value Vtha is lower than the voltage value Vthb, the write speed of the certain memory cell is less than the write speed of the other memory cell. The plurality of selection units MC-s are classified into a plurality of groups based on the write speed.

[0634] Figure 38 is a diagram for explaining an example of classifying (grouping) the selection units based on the write speed of the selection unit corresponding to the application of the evaluation programming voltage Vest.

[0635] As shown in Figure 36 , when the evaluation operation is performed, in step S201, the grouping of the selection units (hereinafter, also referred to as the grouping processing) corresponding to the write speed is performed based on the threshold voltage of the selection unit (the programming target unit) after the application of the evaluation programming voltage Vest.

[0636] For example, the evaluation circuit 191 performs the grouping processing corresponding to the write speed based on the threshold voltage of each selection unit.

[0637] As shown in Figure 38 and Figure 39 , as with the read operation, the threshold voltage of the selection unit after the application of the evaluation programming voltage Vest is discriminated by applying the determination voltage Vgp (Vgpl, Vgp2, Vgp3, Vgp4, Vgp5, Vgp6, Vgp7) to the selection word line WL-s.

[0638] For example, in the case where the voltage Vgpl is applied to the selection word line WL-s, the selection unit having the threshold voltage equal to or lower than the voltage Vgpl is turned on. In the case where the voltage Vgpl is applied to the selection word line WL-s, the selection unit having the threshold voltage higher than the voltage Vgpl is turned off. The result of turning on and off of the selection unit due to the application of the voltage Vgpl is stored in the sense amplifier 150. The selection unit that becomes the on state by the application of the voltage Vgpl is classified into the first group G1 according to the write speed.

[0639] The selection unit having a threshold voltage lower than the voltage Vgp2 turns on when the voltage Vgp2 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp2 turns off when the voltage Vgp2 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to application of the voltage Vgp2 is held in the sense amplifier 150.

[0640] The selection unit which becomes in the off state by application of the voltage Vgpl and in the on state by application of the voltage Vgp2 is classified into the 2nd group set G2 depending on the writing speed.

[0641] The selection unit having a threshold voltage lower than the voltage Vgp3 turns on when the voltage Vgp3 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp3 turns off when the voltage V3 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to application of the voltage Vgp3 is held in the sense amplifier 150.

[0642] The selection unit which becomes in the off state by application of the voltage Vgp2 and in the on state by application of the voltage Vgp3 is classified into the 3rd group set G3 depending on the writing speed.

[0643] The selection unit having a threshold voltage lower than the voltage Vgp4 turns on when the voltage Vgp4 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp4 turns off when the voltage Vgp4 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to application of the voltage Vgp4 is held in the sense amplifier 150.

[0644] The selection unit which becomes in the off state by application of the voltage Vgp3 and in the on state by application of the voltage Vgp4 is classified into the 4th group set G4 depending on the writing speed.

[0645] The selection unit having a threshold voltage lower than the voltage Vgp5 turns on when the voltage Vgp5 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp5 turns off when the voltage Vgp5 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to application of the voltage Vgp5 is held in the sense amplifier 150.

[0646] The selection unit which becomes in the off state by application of the voltage Vgp4 and in the on state by application of the voltage Vgp5 is classified into the 5th group set G5 depending on the writing speed.

[0647] The selection unit having a threshold voltage lower than the voltage Vgp6 turns on when the voltage Vgp6 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp6 turns off when the voltage Vgp6 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to the application of the voltage V6 is held in the sense amplifier 150.

[0648] The selection unit which becomes in the off state by the application of the voltage Vgp5 and in the on state by the application of the voltage Vgp6 is classified into the 6th group set G6 depending on the write speed.

[0649] The selection unit having a threshold voltage lower than the voltage Vgp7 turns on when the voltage Vgp7 is applied to the selection word line WL-s. The selection unit having a threshold voltage higher than the voltage Vgp6 turns off when the voltage Vgp6 is applied to the selection word line WL-s. The result of turning on and off of the selection unit due to the application of the voltage Vgp7 is held in the sense amplifier 150.

[0650] The selection unit which becomes in the off state by the application of the voltage Vgp6 and in the on state by the application of the voltage Vgp7 is classified into the 7th group set G7 depending on the write speed.

[0651] The selection unit which becomes in the off state by the application of the voltage Vgp7 is classified into the 8th group set G8 depending on the write speed.

[0652] Thus, in the present embodiment, based on the magnitude of the threshold voltage of the selection unit corresponding to the application of the evaluation programming voltage Vest (the amount of shift of the threshold voltage), the plurality of selection units are classified into a plurality of group sets G1 to G8 corresponding to the write speed.

[0653] Further, the number of group sets for classifying the write speed is not limited to 8. For example, the number of group sets for classifying the write speed can be more than 8 (for example, 16), and can be less than 8 (for example, 4).

[0654] Thus, by the evaluation action, the characteristics of each selection unit are evaluated depending on the write speed.

[0655] <S21>

[0656] After the evaluation processing, in step S21, the flash memory 1 of the present embodiment performs a prediction action.

[0657] The prediction action is performed based on the result of the evaluation processing (in the present embodiment, the write speed). The prediction action includes a prediction processing of the programming voltage (S211), and a programming action using the predicted programming voltage (S212).

[0658] When the prediction operation is performed, in step S211, the flash memory 1 predicts the voltage values of the plurality of program voltages to be used in the write sequence, based on the cell data of each selection unit MC-s and the evaluation results (the write speeds of each selection unit).

[0659] For example, the prediction circuit 192 performs a calculation process based on the cell data of each selection unit MC-s and the write speed group set. Thereby, the voltage values of the program voltages to be used in the program operation in the prediction operation (predicted program operation) are obtained.

[0660] Figure 39 is a diagram for explaining an example of setting the predicted program voltages based on the evaluation results of the write state and the storage cell characteristics.

[0661] As shown in Figure 38 , a plurality of predicted program voltages Vfcp (Vfcp0, Vfcp1,..., Vfcp7, Vfcp8) are used in the predicted program operation.

[0662] Each predicted program voltage Vfcp has a voltage value (hereinafter, also referred to as a target value) corresponding to the combination of the write state (cell data) and the write speed group set.

[0663] As the tendency of the predicted program voltages Vfcp applied to the selection units, for the selection units to which the cell data corresponding to a certain write state is to be written, the voltage value of the predicted program voltage Vfcp applied to the storage cell having a slower write speed is higher than the voltage value of the predicted program voltage Vfcp applied to the storage cell having a faster write speed.

[0664] For example, for a plurality of selection units to which the cell data of the "A" state is to be written, three predicted program voltages Vfcp0, Vfcp1, Vfcp2 having different voltage values are used according to the write speed of the selection unit. The voltage value Va of the predicted program voltage Vfcp1 is higher than the voltage value Vo of the predicted program voltage Vfcp0. The voltage value Va of the predicted program voltage Vfcp1 is lower than the voltage value Vb of the predicted program voltage Vfcp2. For example, the voltage value Va of the predicted program voltage Vfcp0 can also be equal to the voltage value Vo of the evaluation program voltage Vest.

[0665] For example, for the selection units to which the cell data of the "A" state is to be written, the predicted program voltage Vfcp2 is used for the shift of the threshold voltage of the selection units (low-speed cells) of the group sets Gl, G2, the predicted program voltage Vfcp1 is used for the shift of the threshold voltage of the selection units (medium-speed cells) of the group sets G3, G4, G5, G6, and the predicted program voltage Vpgm0 is used for the shift of the threshold voltage of the selection units (high-speed cells) of the group sets G7, G8.

[0666] For example, in the predictive programming operation, the threshold voltages of the selected cells in the memory cells to which the cell data of a certain upper state should be written, and the threshold voltages of the selected cells in the memory cells to which the cell data of a state lower than the upper state should be written are shifted by a common predictive programming voltage Vfcp.

[0667] For example, the threshold voltages of the selected cells of the group sets Gl, G2 to which the cell data of the "A" state should be written, and the threshold voltages of the selected cells of the group sets G3 to G6 to which the cell data of the "B" state should be written are shifted to higher values by a common predictive programming voltage Vfcp2. Also, the threshold voltages of the selected cells of the group sets G7, G8 to which the cell data of the "C" state should be written can be shifted by the predictive programming voltage Vfcp2.

[0668] For another example, the threshold voltages of the selected cells of the group sets Gl, G2 to which the cell data of the "F" state should be written, and the threshold voltages of the selected cells of the group sets G3 to G6 to which the cell data of the "G" state should be written are shifted to higher values by a common predictive programming voltage Vfcp7.

[0669] Also, the threshold voltages of the selected cells of the group sets Gl, G2 to which the cell data of the "G" state should be written are shifted by a predictive programming voltage Vfcp8. The voltage value Vg of the predictive programming voltage Vfcp8 is higher than the voltage values of the other predictive programming voltages Vfcp0 to Vfcp7.

[0670] Thus, in the predictive programming operation, the voltage values of the predictive programming voltages Vfcp are determined based on the writing states (cell data) and the writing speeds of the selected cells.

[0671] The information (e.g., the setting information table) related to the predictive programming voltages of the selected cells of the selected addresses can be stored in the flash memory 1. The information related to the predictive programming voltages of the selected cells of the selected addresses can also be transmitted to the memory controller 2 at a certain timing, and stored in the memory controller 2.

[0672] Further, Figure 35 Nine predictive programming voltages Vfcp0 to Vfcp8 are shown in FIG. 9. The number of the predictive programming voltages Vfcp to be used in the predictive programming operation can be less than nine, or more than nine.

[0673] For example, a plurality of predictive programming voltages having different voltage values from each other can be set corresponding to a plurality of writing states.

[0674] When the predictive operation is performed, in the predictive programming operation of step S211, as Figure 37As shown in (a), the flash memory 1 does not perform the verification action related to the threshold voltage of the selection cell (hereinafter referred to as programming verification), but sequentially applies the obtained multiple predicted programming voltages Vfcp to the selection word line WL-s (S211).

[0675] For example, the prediction circuit 191 performs various controls to apply the prediction programming voltage Vfcp.

[0676] The predictive programming action does not involve the application of a verification voltage (hereinafter referred to as the verification step), but only involves the application of a programming voltage more than once (hereinafter referred to as the programming step).

[0677] Within the flash memory 1, the sequencer 190 (e.g., the prediction circuit 192) shifts the threshold voltage of the selection cell MC-s in a positive direction by predicting the programming action (predicting the application of the programming voltage). This coarsely writes cell data corresponding to each write state to the multiple selection cells in the programmable state.

[0678] like Figure 36 As shown in (b), the threshold voltage of each selection cell MC-s is shifted in the positive direction by the application of a predicted programming voltage Vfcp that takes into account the write speed of each selection cell MC-s, with a shift amount corresponding to the cell data and the write speed.

[0679] <S22>

[0680] After the prediction action, the flash memory of this embodiment performs a programming action in step S22.

[0681] Figure 36 (b) is a schematic diagram illustrating the programming operation in the write sequence of the flash memory in this embodiment. Figure 36 (b) shows the voltages Vpgm and Vvfy applied to the select word line.

[0682] In the flash memory 1 of this embodiment, the sequencer 190, as shown... Figure 36 As shown in (b), with programming verification, the operation of applying multiple programming voltages Vpgm to the memory cell connected to the select word line WL-s is performed.

[0683] A programming action consists of one or more programming steps and one or more verification steps. For distinction, programming actions that include verification are also referred to as refined programming actions (or verified programming actions or ordinary programming actions).

[0684] The sequencer 190 writes the cell data to each selected cell in detail by refining the programming action.

[0685] For example, the program voltage Vpgm used in the refinement programming operation of step S22 is determined based on the voltage value calculated by the prediction operation (e.g., the voltage value of the predicted program voltage Vfcp). For example, the sequencer 190 sets the voltage value of the program voltage Vpgm for the program of each write state (cell data) with reference to the predicted program voltage Vfcp corresponding to each write state. More specifically, the sequencer 190 uses the voltage value of the predicted program voltage Vfcp of each write state as the initial voltage value of the program voltage Vpgm associated with each program state.

[0686] The sequencer 190 sequentially adds an adjustment voltage (hereinafter, also referred to as a step-up voltage) dV to the program voltage Vpgm (Vpgm1, Vpgm2, Vpgm3, Vpgm4,..., Vpgmx, Vpgmy) corresponding to the predicted program voltage Vfcp in each write cycle LP (LP1, LP2, LP3, LP4,..., LPk-1, LPk) and executes the program step in the refinement programming operation. Each write cycle includes at least one application of the program voltage (program step) and at least one program verification (verify step). k is an integer of 2 or more.

[0687] The voltage value dV of the step-up voltage Vstp can also be determined based on the cell data and the characteristic information (write speed) by the prediction operation.

[0688] In the example of (b) of FIG. 17, Figure 40 In the example of (b) of FIG. 17,

[0689] After the application of the program voltage Vpgm1, the sequencer 190 applies the verify voltage Vvfy to the selected word line WL-s. The verify voltage Vvfy includes one or more verify levels. Thus, the threshold voltage of the selected cell after the application of the program voltage Vpgm1 is verified. In this way, the program operation is performed so that the threshold voltage of each selected cell MC-s converges within the threshold voltage distribution corresponding to the cell data.

[0690] After the verify voltage Vvfy in the first write cycle LP1, the sequencer 190 executes the second write cycle LP2.

[0691] In the 2nd write cycle LP2, the sequencer 190 applies the program voltage Vpgm2 to the selected word line WL-s. For example, the voltage value of the program voltage Vpgm2 is the voltage value ("Vp1+dV") obtained by adding the voltage value Vp1 (Va) of the program voltage Vpgm1 to the voltage value dV of the step-up voltage Vstp. After applying the program voltage Vpgm2, the sequencer 190 applies the verify voltage Vvfy to the selected word line WL-s. Thus, the threshold voltage of the selected cell MC-s after applying the program voltage Vpgm2 is verified.

[0692] Thus, the sequencer 190 changes the voltage value of the program voltage Vpgm (and the verify level of the verify voltage Vvfy) and executes a plurality of write cycles LP.

[0693] For example, in the flash memory 1 of the present embodiment, if the sequencer 190 determines that the application of one or more program voltages Vpgm (here, the program voltages Vpgm1, Vpgm2, Vpgm3) using the voltage value of the predicted program voltage Vfcp1 associated with the "A" state as a reference value has been completed, for example, in the 3rd write cycle LP3, the sequencer 190 executes the application of one or more program voltages Vpgm4 using the voltage value Vb of the predicted program voltage Vfcp2 associated with the "B" state as a reference value, for example, in the 4th write cycle LP4.

[0694] The sequencer 190 can determine the change of the predicted program voltage Vfcp as a reference value of the program voltage Vpgm based on the number of write cycles executed and / or the voltage value of the program voltage Vpgm used in the current write cycle.

[0695] Thus, in the present embodiment, the sequencer 190 can change and set the voltage value of the program voltage Vpgm based on the number of write cycles (e.g., the number of write cycles LP) of the refinement programming operation, when the sequencer 190 executes the refinement programming operation, to a value based on a plurality of predicted program voltages obtained by the prediction operation.

[0696] The sequencer 190 sequentially applies a plurality of program voltages Vpgm obtained based on a plurality of predicted program voltages Vfcp.

[0697] For example, in the (k-1)th write cycle LPk-1, the sequencer 190 applies the program voltage Vpgmx to the selected word line WL-s. For example, the voltage value Vpx of the program voltage Vpgmx is based on the voltage value Vf of the predicted program voltage associated with the "F" state as a reference value.

[0698] For example, in the k-th write loop LPk, the sequencer 190 applies the program voltage Vpgmy to the selected word line WL-s. For example, the voltage value Vpy of the program voltage Vpgmy is set as a reference value based on the voltage value Vf of the predicted program voltage associated with the "G" state.

[0699] As a result, the threshold voltage of the selected cell is shifted in the positive direction.

[0700] The sequencer 190 determines whether the refinement programming operation is completed based on the number of times of application of the program voltage Vpgm (or the verification result).

[0701] As a result, the sequencer 190 completes the refinement programming operation.

[0702] Further, when the refinement programming operation and the prediction programming operation of the present embodiment are performed, the selected cell (programmable cell) whose threshold voltage is shifted by the program voltage in each write state can also be set to the programmable state.

[0703] In addition, when the refinement programming operation and the prediction programming operation of the present embodiment are performed, the selected cell corresponding to the program voltage of the write state, and the selected cell corresponding to the program voltage of the write state higher than the write state can also be set to the programmable state.

[0704] As described above, the flash memory of the present embodiment completes the write sequence including the evaluation operation, the prediction programming operation, and the refinement programming operation.

[0705] The flash memory 1 of the present embodiment calculates the voltage values of the plurality of program voltages based on the evaluation result of the write speed of the selected cell MC-s when the write operation (write sequence) is performed. As a result, the flash memory of the present embodiment can apply the plurality of program voltages having more appropriate voltage values to the plurality of selected cells MC-s located at the selected address.

[0706] As a result, the flash memory 1 of the present embodiment can suppress an increase in the number of times of application of the program voltage. For example, the flash memory 1 of the present embodiment can realize a high speed of the write operation (for example, a reduction in the time of the write operation).

[0707] As described above, the flash memory 1 of the present embodiment can perform the write operation more efficiently. Therefore, the flash memory of the present embodiment can improve the quality.

[0708] (b2-2) Action Example 2

[0709] Referring to Figure 41 and Figure 40 An example of the write operation of the flash memory of the present embodiment is described.

[0710] Figure 41 is a flowchart showing the processing flow of Action Example 2 that represents the write operation of the flash memory of the present embodiment.

[0711] Figure 40 is a diagram for explaining Action Example 2 that represents the write operation of the flash memory of the present embodiment.

[0712] In the present Action Example 2, Figure 40 the prediction operation in Step S21A of the processing flow differs from the prediction operation of Action Example 1.

[0713] In the present Action Example 2, Figure 41 in Step S211, when the target value of the predicted program voltage Vfcp is predicted, the cell data (write state) of the adjacent multiple selection units is used in addition to the cell data of each selection unit and the write speed.

[0714] As shown in Figure 41 , the selection units MC-s in the write sequence are arranged in the Z direction. In this case, the write of data (application of the program voltage) is performed simultaneously on the multiple selection units MC-s arranged in the Z direction.

[0715] In the write operation, there is a possibility of a disturbance effect between the selection units MC-s. Therefore, in the present embodiment, the sequencer adjusts the voltage value of the program voltage in the write operation.

[0716] Based on the bit arrangement within the supplied write data, the cell data of the multiple selection units adjacent in the Z direction can be recognized. From this, the disturbance effect (for example, the magnitude of the disturbance) that is likely to occur between the adjacent selection units is predicted.

[0717] The sense amplifier 150, as described above, includes multiple latch circuits (not shown). Each latch circuit is associated with any one of the multiple bit lines BL. The cell data of each selection unit is temporarily stored in the latch circuit.

[0718] In the sequencer 190, the prediction circuit 192 recognizes the arrangement of the write state of the adjacent selection units by the operation processing of the cell data in the multiple latch circuits.

[0719] From this, the difference between the write state of one selection unit and the write state of another selection unit of the adjacent selection units is calculated.

[0720] When the target value of the predicted program voltage Vfcp is predicted, the difference in the cell data (write state) of the adjacent selection units is reflected.

[0721] In the example of Figures 42 to 44 , the cell data of the "B" state is written to the selection unit MC-s1.

[0722] The cell data in the "G" state is written to the selection cell MC-s2. The selection cell MC-s2 is above the selection cell MC-s1 in the Z direction, adjacent to the selection cell MC-s1.

[0723] The data in the "C" state is written to the selection cell MC-s0. The selection cell MC-s0 is below the selection cell MC-s1 in the Z direction, adjacent to the selection cell MC-s1.

[0724] The data in the "D" state is written to the selection cell MC-s3. The selection cell MC-s3 is above the selection cell MC-s2 in the Z direction, adjacent to the selection cell MC-s2.

[0725] The threshold voltage distribution in the "B" state is adjacent to the threshold voltage distribution in the "C" state. Therefore, the interference effect occurring between the selection cell MC-s1 and the selection cell MC-s0 is relatively small.

[0726] As described above, the threshold voltage distribution in the "G" state is a distribution 5 bits higher than the threshold voltage distribution in the "B" state. Therefore, the interference effect occurring between the selection cell MC-s1 and the selection cell MC-s2 is larger than the interference effect occurring between the selection cell MC-s1 and the selection cell MC-s0.

[0727] Thus, in a case where the influence of the interference effect is large, the target value of the predictive programming voltage Vfcp (for example, the target value of the predictive programming voltage related to the "G" state) is adjusted based on the difference in the write state (cell data) of the adjacent selection cells to shift to a voltage value lower than the target value of the predictive programming voltage Vfcp in a case where the influence of the interference effect is small.

[0728] Thus, the influence of the interference effect between the selection cells is suppressed.

[0729] For example, with respect to the predictive programming voltage Vfcp for a certain write state, the difference in the write state (here, referred to as a difference value) between a certain selection cell and a selection cell adjacent to the certain selection cell (here, referred to as an adjoining cell) is calculated in the plurality of selection cells MC-s in which the cell data in the write state is to be written. Based on the calculation results of the plurality of difference values, the target value of the predictive programming voltage Vfcp for the write state is adjusted.

[0730] The difference in the write state between the two selection units adjacent to the selection unit MC-s3 and the selection unit MC-s2 ("D" state and "G" state) is smaller than the difference in the write state between the selection unit MC-s1 and the selection unit MC-s2 ("B" state and "G" state). Even if the difference in the write state between the adjacent selection units is small, the voltage value of the predictive programming voltage Vfcp can be adjusted according to the magnitude of the difference in the write state between the adjacent selection units MC-s.

[0731] It is more preferable that the target value of the predictive programming voltage Vfcp be adjusted as long as the write states of the adjacent selection units MC-s are different.

[0732] In this way, the voltage values of the plurality of predictive programming voltages in the write sequence are calculated based on the cell data of each selection unit MC-s, the write speed of the selection unit MC-s, and the difference in the write state (cell data) between the adjacent selection units MC-s. Thus, the target value of the predictive programming voltage Vfcp is predicted.

[0733] In step S212, the predictive programming operation is performed using the voltage value of the predictive programming voltage Vfcp obtained.

[0734] After the predictive programming operation, the refinement programming operation is performed in step S22 as in the write sequence of Action Example 1.

[0735] Through the above actions, the write sequence of the flash memory of the present embodiment is completed.

[0736] If the target value of the programming voltage is set as in the write sequence described in the present embodiment, the distribution width of each threshold voltage distribution in the predictive programming operation is reduced when the write state of the adjacent selection unit is reflected.

[0737] As a result, the flash memory of the present embodiment can suppress the write error.

[0738] As the distribution width of the threshold voltage distribution is reduced when the predictive programming operation is performed, the number of write cycles when the refinement programming operation is performed is reduced.

[0739] (b2-3) Action Example 3

[0740] Reference Figure 42 An example of the write operation of the flash memory of the present embodiment will be described.

[0741] Figure 43 is a flowchart showing a processing flow of an example of the write operation of the flash memory of the present embodiment.

[0742] Figure 43is a schematic graph of voltages applied to the memory cells MC (selected word lines) in an example of a write operation of the flash memory of the present embodiment. In Figure 44 In the graph, the horizontal axis corresponds to time, and the vertical axis corresponds to voltage values.

[0743] Figures 42 to 44 is a schematic graph of changes in threshold voltages of the memory cells in an example of a write operation of the flash memory of the present embodiment.

[0744] As Figure 42 shown in the write sequence of the present action example 3, a plurality of evaluation actions (S20B, S20C) and a plurality of prediction actions (S21B, S21C) are executed.

[0745] An action group SS (SS1, SS2) including one evaluation action and one prediction action is executed as one sequence (hereinafter, also referred to as a write stage).

[0746] The flash memory of the present embodiment executes a write sequence including two write stages SS1, SS2.

[0747] As Figure 43 shown in the processing flow, the first write stage SS1 in the write sequence is executed.

[0748] In the present action example, in the case of the memory cells being TLC, the evaluation action (S20B) and the prediction action (S21B) of the first write stage SS1 are executed on the selected cells (selected cells of the first group set) to be written with data of the "D" "E" "F", and "G" states.

[0749] <S20B>

[0750] In the present action example, the sequencer 190 executes the evaluation action of the first write stage SS1 on a plurality of selected cells MC-s to be written with data of any one of the "D" to "G" states, by the evaluation circuit 191.

[0751] As Figure 44 shown, in the evaluation action of the first write stage SS1, the first evaluation programming voltage Vestl of a certain voltage value is applied to the selected word line WL-s. The threshold voltages of the selected cells MC-s of the first group set are shifted in the positive direction.

[0752] In the execution of the evaluation action of the first write stage SS1, the selected cells (selected cells of the second group set) MC-s to be written with data of any one of the "A" "B", and "C" states are set to the programming prohibited state.

[0753] As Figure 42As shown in (a), during the evaluation operation of the selection unit MC-s belonging to the first set of “D” to “G” states, the threshold voltage of the selection unit in the “D” to “G” states is shifted by the first evaluation programming voltage Vest1 to the threshold voltage distribution (hereinafter referred to as the “LM” state) 999A between the upper limit (upper end of the distribution) of the threshold voltage distribution in the “C” state (or “B” state) and the lower limit (lower end of the distribution) of the threshold voltage distribution in the “D” state.

[0754] The programming action that shifts the threshold voltage of the memory cell to the "LM" state is also called the LM programming action.

[0755] The write speed of the selection cell MC-s in the “D” to “G” states is measured by an evaluation action that includes LM programming actions.

[0756] <S21B>

[0757] like Figure 43 As shown, in the prediction operation of the first write stage SS1, the sequencer 190, through the prediction circuit 192, predicts and calculates the voltage value of the predicted programming voltage for the selected cells MC-s belonging to the first set, based on the cell data of each selected cell MC-s and the write speed of each selected cell MC-s (S211B). In addition, when calculating the predicted programming voltage, the difference in cell data between adjacent selected cells MC-s can also be used.

[0758] In the prediction operation, the sequencer 190 performs the first prediction programming operation (S212B) in the first write stage SS1 through the prediction circuit 192.

[0759] like Figure 44 As shown in (a), multiple predictive programming voltages Vfcp0a, Vfcp1a, ..., Vfcp2a are applied to the select word line WL-s. Using the predictive programming voltage Vfcp of a certain voltage value VLM, unverified programming actions are performed on multiple select cells MC-s in the "LM" state.

[0760] The predicted programming voltage Vfcp0a has a target value Vd1 for example, for cell data in state "D". The predicted programming voltage Vfcp1a has a target value Ve1 for example, for cell data in state "E". The predicted programming voltage Vfcp2a has a target value Vg1 for example, for cell data in state "G".

[0761] Therefore, as Figure 42 As shown in (b), in the first set, the threshold voltage of the selection unit MC-s for the “D” to “G” states is shifted in the positive direction.

[0762] like Figure 43In the example of the present embodiment, the sequencer 190 performs the evaluation action of the second write stage SS2 on the plurality of selection units MC-s of the cell data to be written into any of the "A" to "C" states, by the evaluation circuit 192.

[0763] The evaluation action (S20C) and the prediction action (S21C) of the second write stage SS2 are performed on the selection units (selection units of the second group set) MC-s of the cell data to be written into any of the "A" to "C" states.

[0764] <S20C>

[0765] In the present embodiment, the sequencer 190 performs the evaluation action of the second write stage SS2 on the plurality of selection units MC-s of the cell data to be written into any of the "A" to "C" states, by the evaluation circuit 192.

[0766] As shown in Figure 44 , in the evaluation action in the second write stage SS2, the second evaluation programming voltage Vest2 of a certain voltage value is applied to the selection word line WL-s. The threshold voltages of the selection units MC-s of the "A" to "C" states are shifted. For example, the voltage value of the second evaluation programming voltage Vest2 has a voltage value (preset value) V0 that shifts the threshold voltage of the selection unit MC-s into the threshold voltage distribution of the "A" state.

[0767] For example, in the evaluation action of the second write stage SS2, the selection units MC-s of the cell data to be written into any of the "D" to "G" states are set to the prohibited programming state.

[0768] Thus, as shown in Figure 42 , in the evaluation action (S20C) on the selection units MC-s of the "A" to "C" states, the threshold voltages of the selection units MC-s of the "A" to "C" states are shifted to the extent of the threshold voltage distribution 999B of the "A" state.

[0769] Hereinafter, the programming action that shifts the threshold voltage of the storage unit to the "A" state is referred to as an "A" programming action.

[0770] By the evaluation action including the "A" programming action, the write speed of the selection units of the "A" to "C" states is measured.

[0771] <S21C>

[0772] As shown in Figure 43As shown, in the prediction action in the 2nd write phase SS2, the sequencer 190 predicts and calculates the voltage values of the program voltages for the selection units MC-s of the "A" to "C" states based on the cell data of each selection unit MC-s and the write speeds of each selection unit MC-s through the prediction circuit 192 (S211C). In addition, the difference of the cell data of the adjacent selection units MC-s can also be used when calculating the predicted program voltages.

[0773] In the prediction action, the flash memory 1 performs the 2nd prediction program action in the 2nd write phase SS2 (S212C).

[0774] As shown, the multiple predicted program voltages Vfcp3a, Vfco4a, Vfcp5a are applied to the selection word line WL-s. The selection units belonging to the threshold distribution 999B of the "A" state are subjected to the program action without verification using the predicted program voltage Vfcp. Figure 44 The predicted program voltage Vfcp3a has a target value Va1 for the cell data of the "A" state, for example. The predicted program voltage Vfcp4a has a target value Vb1 for the cell data of the "B" state, for example. The predicted program voltage Vfcp5a has a target value Vc1 for the cell data of the "C" state, for example.

[0775] As shown, the threshold voltages of the selection units of the "A" to "C" states in the 2nd group are shifted in the positive direction.

[0776] Figure 42

[0777] <S22>

[0778] As shown, after the 2 write phases SS1, SS2, the sequencer 190 performs the refinement program action for the multiple selection units MC-s whose cell data are to be written into the "A" to "G" states. Figures 45 to 47 In this action example (and other action examples), the refinement program action can also be performed using the program voltages based on the target values of the predicted program voltages for each write state, respectively. By applying the program voltages, the threshold voltages of the selection units of a certain write state and the write states above the certain write state can also be shifted at the same time.

[0779] Through the above processing, the write sequence of the flash memory of the embodiment in Action Example 3 is completed.

[0780] In this embodiment, the prediction action related to the upper write state and the prediction action related to the lower write state are performed in different sequences (write phases).

[0781]

[0782] ​​​Accordingly, the flash memory of the present embodiment can predict the target value of the program voltage related to the lower write state (here, "A" to "C" states) without the influence of the interference effect between the selection units.

[0783] As a result, the flash memory of the present embodiment can set a more appropriate voltage value of the program voltage.

[0784] (b2-4) Action Example 4

[0785] Referring to Figure 45 An example of the write operation of the flash memory of the present embodiment will be described.

[0786] Figure 46 is a flowchart showing a processing flow of an example of the write operation of the flash memory of the present embodiment.

[0787] Figure 47 is a schematic diagram for explaining the change of the threshold voltage of the memory cell in an example of the write operation of the flash memory of the present embodiment.

[0788] Figure 47 is a schematic graph for explaining the voltage applied to the memory cell MC (select word line) in an example of the write operation of the flash memory of the present embodiment. In Figure 45 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to the voltage value.

[0789] As described above, the flash memory of the present embodiment holds information related to the write state of the selection unit (cell data) and the target value of the program voltage.

[0790] Accordingly, the flash memory of the present embodiment can recognize the number of selection units under each program voltage.

[0791] In the present action example 4, the flash memory 1 of the present embodiment applies a plurality of program voltages to the select word line in the order corresponding to the number of selection units based on the number of selection units under each program voltage in the program operation.

[0792] <S21D>

[0793] As Figure 46 shown, after the evaluation operation (S20), the sequencer 190 performs the prediction operation through the prediction circuit 192.

[0794] The sequencer 190 predicts and calculates the target value of the predicted program voltage Vfcp based on the write state of each selection unit MC-s, the write speed of each selection unit MC-s, and the write state difference of adjacent selection units MC-s, as in the example (S211D). In addition, in this example, the write state difference of adjacent selection units can not be used when predicting the target value of the predicted program voltage Vfcp.

[0795] In this Action Example 4, the flash memory 1 of the present embodiment counts the number of selection units programmed using each predicted program voltage Vfcp, for the obtained plurality of predicted program voltages Vfcp (Vfcpa, Vfcpb, Vfcpc, Vfcpd,...) (S219).

[0796] The sequencer 190 sets the order of application of the plurality of predicted program voltages based on the size relationship of the number of selection units using each predicted program voltage Vfcp.

[0797] Figure 46 is a graph showing the relationship between the write state and the number of selection units.

[0798] In the example of Figure 46 , as shown in (a) of Figure 46 , the number of selection units using the predicted program voltage Vfcpa among the plurality of predicted program voltages is "Na". The number of selection units using the predicted program voltage Vfcpb among them is "Nb". The number of selection units using the predicted program voltage Vfcpc among them is "Nc". The number of selection units using the predicted program voltage Vfcpd among them is "Nd".

[0799] As shown in (b) of Figure 46 , among the number of selection units using each predicted program voltage, the number Nc is the largest, and the other numbers Na, Nb, and Nd are smaller than Nc. The number Na is smaller than Nc and larger than the numbers Nd and Nb. The number Nd is larger than the number Nb.

[0800] As shown in (a) of Figure 47 and Figure 45 , the sequencer 190 applies the plurality of predicted program voltages Vfcp to the selection word line in the order of the predicted program voltage Vfcpc, the predicted program voltage Vfcpa, the predicted program voltage Vfcpd, and the predicted program voltage Vfcpb, according to the size relationship of the number of selection units.

[0801] The magnitude relationship of the voltage values of the prediction program voltages Vfcpa, Vfcpb, Vfcpc, Vfcpd is as follows: the voltage value Vdz of the prediction program voltage Vfcpd is higher than the voltage values Vaz, Vbz, Vcz of the prediction program voltages Vfcpa, Vfcpb, Vfcpc; the voltage value Vcz of the prediction program voltage Vfcpc is lower than the voltage value Vdz of the prediction program voltage Vfcpd and higher than the voltage values Vaz, Vbz of the prediction program voltages Vfcpa, Vfcpb; the voltage value of the prediction program voltage Vfcpb is lower than the voltage values Vcz, Vdz of the prediction program voltages Vfcpc, Vfcpd and higher than the voltage value Vaz of the prediction program voltage Vfcpa; and the voltage value of the prediction program voltage Vfcpa is lower than the voltage values Vbz, Vcz, Vdz of the prediction program voltages Vfcpb, Vfcpc, Vfcpd.

[0802] As shown in FIG. 18, the sequencer 190 does not perform program verification and applies the plurality of prediction program voltages Vfcp to the selected word line WL-s in the order of the number of selected cells using each prediction program voltage Vfcp (S212D). Figure 48

[0803] The flash memory 1 applies the prediction program voltage Vfcpc to the selected word line WL-s at a certain timing. After the application of the prediction program voltage Vfcpc, the sequencer 190 applies the prediction program voltage Vfcpa to the selected word line WL-s at a certain timing. After the application of the prediction program voltage Vfcpa, the flash memory 1 applies the prediction program voltage Vfcpd to the selected word line WL-s at a certain timing. After the application of the prediction program voltage Vfcpa, the flash memory 1 applies the prediction program voltage Vfcpb to the selected word line WL-s at a certain timing.

[0804] Thus, in the prediction program operation of the present action example, the sequencer 190 applies the plurality of prediction program voltages Vfcp to the selected word line WL-s in the order based on the magnitude relationship of the number of selected cells using each prediction program voltage Vfcp regardless of the magnitude relationship (level of the write state) of the voltage values of the plurality of prediction program voltages Vfcp.

[0805] <S22>

[0806] After the prediction operation, the sequencer 190 performs a refinement program operation (S22).

[0807] For example, as in the action example, the sequencer 190 sequentially performs the application of the program voltage and the program verification in the order from the lower write state (here, the "A" state) to the upper write state (here, the "G" state).

[0808] ​Further, in the refinement programming operation, the application order of the programming voltages can be set according to the number of the selected cells, as in the prediction programming operation.

[0809] Through the above operation, the write sequence of the flash memory of the present embodiment in the present operation example 4 is completed.

[0810] As described above, in the present operation example 4, the flash memory 1 of the present embodiment determines the application order of the plurality of prediction programming voltages according to the number of the selected cells using each prediction programming voltage.

[0811] Thus, the flash memory of the present embodiment can reduce the number of the selected cells whose threshold voltages can fluctuate due to the application of the prediction programming voltages after the threshold voltages of the selected cells are shifted.

[0812] As a result, in the present operation example, the flash memory of the present embodiment can suppress the write error.

[0813] (b2-5) Operation Example 5

[0814] Referring to Figure 49 and Figure 48 , an example of the write operation of the flash memory of the present embodiment is described.

[0815] Figure 49 is a flowchart showing a processing flow of an example of the write operation of the flash memory of the present embodiment.

[0816] Figure 49 is a schematic graph showing voltages applied to the memory cells MC (selected word lines) in an example of the write operation of the flash memory of the present embodiment. In Figure 48 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to voltage values.

[0817] <S20>

[0818] As shown in Figure 49 , in the present operation example 5, the sequencer 190 performs the evaluation operation on the plurality of selected cells MC-s, as in the above operation example.

[0819] Thus, the write speed of the selected cells MC-s is measured (S201).

[0820] The sequencer 190 acquires information related to the write speed based on the measurement result through the evaluation circuit 192 (S202).

[0821] <S21A>

[0822] The sequencer 190 performs the prediction operation, as in the above operation.

[0823] The sequencer 190 calculates a target value of the predicted program voltage Vfcp based on the cell data of each selection unit MC-s, the write speed of each selection unit MC-s, and the write state difference between adjacent selection units MC-s (S211A).

[0824] The sequencer 190 determines the target value of the predicted program voltage Vfcp using the calculation result (S212). Further, in the present action example, the write state difference between adjacent selection units can not be used when the target value of the predicted program voltage Vfcp is predicted.

[0825] The sequencer 190 applies the determined plurality of predicted program voltages Vfcp to the selection word line WL-s.

[0826] As shown in (a) of FIG. 17, when the predicted program operation is performed, the predicted program voltages Vfcp0, Vfcp1, Vfcp2, …, Vfcp7, Vfcp8, … are applied to the selection word line WL-s. Figure 49

[0827] Thus, the threshold voltage of each selection unit MC-s is shifted in the positive direction according to the corresponding predicted program voltage.

[0828] For example, the predicted program voltage Vfcp0 has a voltage value Va. The predicted program voltage Vfcp1 has a voltage value Vb. The predicted program voltage Vfcp2 has a voltage value Vc. The predicted program voltage Vfcp7 has a voltage value Vf. The predicted program voltage Vfcp8 has a voltage value Vg.

[0829] <S22A>

[0830] After the prediction operation, the sequencer 190 performs a refinement program operation.

[0831] In the present action example 5, the sequencer 190 does not use the voltage value (target value) used when the predicted program operation is performed when performing the refinement program operation.

[0832] In the refinement program operation, one or more program voltages Vpgm having voltage values different from the voltage values of one or more predicted program voltages Vfcp used in the predicted program operation are applied to the selection word line WL-s.

[0833] However, the voltage value of the program voltage Vpgm is set based on the voltage value calculated by the prediction operation, as in the example.

[0834] In the present action example 5, when the refinement program operation is performed, a program voltage having the same voltage value as the voltage value of the predicted program voltage applied to the selection word line WL-s when the predicted program operation is performed is skipped. ​

[0835] As ​ As shown in (b) of the same figure, the sequencer 190 applies a plurality of program voltages Vpgm to the selected word line WL-s.

[0836] The sequencer 190 applies a program voltage Vpgmlz having a voltage value Vplz to the selected word line WL-s. The voltage value Vplz is higher than the voltage value Va. For example, in a case where the voltage value VIa is higher than the voltage value VOa by "dVl", the voltage value Vplz has a value (Va+dV) obtained by adding the voltage value dV to the voltage value Va.

[0837] Thus, the sequencer 190 skips the application of the program voltage having the voltage value Va by adding the step-up voltage Vstp.

[0838] The sequencer 190 applies a program voltage Vpgm2z to the selected word line WL-s after applying the program voltage Vpgmlz. The program voltage Vpgm2z is higher than the voltage value Vplz and lower than the voltage value Vb.

[0839] The sequencer 190 applies a program voltage Vpgm3z to the selected word line WL-s after applying the program voltage Vpgm2z. The program voltage Vpgm3z has a voltage value Vp2 higher than the voltage value Vb. For example, the voltage value Vp2 has a voltage value (Vb+dV) obtained by adding the voltage value dV to the voltage value Vb.

[0840] Thus, the sequencer 190 skips the application of the program voltage having the voltage value Vb by adding the step-up voltage Vstp.

[0841] Thus, the sequencer 190 skips the application of the program voltage having the voltage value used in the execution of the predictive programming operation while sequentially executing the application of the program voltage Vpgm and the program verification.

[0842] Through the above operation, the flash memory of the present embodiment ends the write sequence of the present operation example 5.

[0843] As shown in the present operation example 5, the flash memory of the present embodiment does not apply the program voltage having the voltage value used in the predictive programming operation again in the execution of the refine programming operation.

[0844] Thus, the number of programming steps (the number of write cycles) in the refine programming operation is reduced. As a result, the period of the refine programming operation is shortened.

[0845] Therefore, the flash memory of the present embodiment can improve the speed of the write operation.

[0846] (c2) Summary

[0847] The flash memory of the embodiment acquires information related to characteristics (e.g., writing speed) of the plurality of selection units in the writing operation.

[0848] The flash memory of the embodiment calculates a voltage value suitable for a program voltage based on the cell data of each selection unit and the characteristic information of each selection unit.

[0849] The flash memory of the embodiment performs a program operation using the calculated program voltage.

[0850] Thus, the flash memory of the embodiment can shorten the period of the writing operation. In addition, the flash memory of the embodiment can reduce writing errors of data.

[0851] Therefore, the flash memory of the embodiment can improve the operation characteristics.

[0852] As described above, the storage device of the embodiment can improve the quality.

[0853] (3) Modification

[0854] The structure of the flash memory that performs the data writing described in the embodiment is not limited to the structure described in the first embodiment. The data writing described in the embodiment can also be applied to data writing of a flash memory having another structure. For example, the storage cell array can also have a structure in which a plurality of storage cells are arranged in a two-dimensional manner on a semiconductor substrate, instead of being stacked in the Z direction.

[0855] In addition, the three-dimensional structure storage cell array can also have a structure in which storage cells connected to a common word line are arranged in a direction parallel to the surface of the substrate.

[0856] The examples (structure examples and operation examples) described in the embodiment can be appropriately combined within a range that satisfies matching.

[0857] (4) Others

[0858] While several embodiments of the present application have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. The novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made thereto without departing from the scope of the application. Such embodiments and their variations are also encompassed within the scope or spirit of the application and are to be considered equivalents of the application as described in the claims.

[0859] [Explanation of Symbols]

[0860] 1: Storage device

[0861] 100: Storage cell array

[0862] 142: select gate line decoder

[0863] 151: bit line selection circuit

[0864] 152: amplification circuit

[0865] TRn, TRp: transistor

[0866] MC: memory cell

[0867] SGD, SGS: select gate line

[0868] WL: word line

[0869] BL: bit line

Claims

1. A storage device comprising: Substrate; The first and second stacks are arranged along a second direction parallel to the surface of the substrate, and each includes a plurality of first semiconductor layers arranged along a first direction perpendicular to the surface of the substrate. Multiple word lines cover the first and second stacked volumes; The second semiconductor layer is disposed above the first laminate in the first direction; The third semiconductor layer is disposed above the second laminate in the first direction; Multiple memory cells are respectively disposed between the multiple first semiconductor layers and the multiple word lines; The first transistor is disposed on the second semiconductor layer; and The second transistor is disposed on the third semiconductor layer; The first and second laminates are arranged at a first spacing in the second direction. The first and second semiconductor layers are arranged at a second spacing in the second direction, and The second spacing is equal to the first spacing.

2. The storage device according to claim 1, wherein The first transistor includes a first gate electrode, which is disposed above the second semiconductor layer in the first direction. The size of the first gate electrode in the second direction is equal to the size of the second semiconductor layer in the second direction.

3. The storage device according to claim 1, wherein It also has: Multiple select gate lines cover the first and second stacked layers; and Decoding circuitry is used to control the plurality of select gate lines; and The decoding circuit includes the first and second transistors.

4. The storage device according to claim 1, wherein It also has: Multiple first contacts are respectively connected to the multiple first semiconductor layers; Multiple bit lines are respectively connected to the multiple first contacts; and A selection circuit is used to control the connection between the plurality of first contacts and the plurality of bit lines; and The selection circuit includes the first and second transistors.

5. The storage device according to claim 1, wherein It also has: Multiple bit lines are respectively connected to the multiple first semiconductor layers; and An amplifier circuit is used to amplify the signals from the plurality of memory cells; and The amplifier circuit includes the first and second transistors.

6. The storage device according to claim 1, wherein It also has: Multiple storage cells are arranged within a storage cell array and connected to word lines; and The circuit controls the writing of data to the plurality of storage units; and When the circuit writes data to multiple memory cells connected to the word line, Measure the characteristics of each of the plurality of storage cells, Based on the data and the measurement results of the characteristics, the voltage values ​​of the multiple programming voltages applied to the word line are calculated. The plurality of programming voltages are applied to the word lines.

7. The storage device according to claim 6, wherein The characteristic mentioned is the write speed of the storage unit.

8. The storage device according to claim 6, wherein The plurality of programming voltages includes: a plurality of first programming voltages based on the measurement results, and a plurality of second programming voltages set based on the plurality of first programming voltages, and The circuit When the plurality of first programming voltages are applied, no verification action related to the threshold voltage of the plurality of memory cells is performed. The verification action is performed when the plurality of second programming voltages are applied.

9. The storage device according to claim 6, wherein The circuit calculates the voltage value of each of the plurality of programming voltages based on the data difference between adjacent memory cells in the plurality of memory cells.

10. The storage device according to claim 6, wherein The written data includes the first data, the second data, and the third data. The number of the first storage cells to be written with the first data is the first number. The number of the second storage cells to be written with the second data is the second number. The number of the third storage cells to be written with the third data is the third number, and The third number is more than the second number. The second number is more than the first number. The circuit is based on the first, second, and third numbers. A third programming voltage is applied to the word line to write the third data to the third memory cell. After applying the third programming voltage, a fourth programming voltage is applied to write the second data to the second memory cell. After the fourth programming voltage is applied, a fifth programming voltage is applied to write the first data to the first memory cell.

11. The storage device according to claim 6, wherein The plurality of storage units include: Multiple fourth storage units in the first set are to be written with data corresponding to any threshold voltage distribution among multiple threshold voltage distributions above the first threshold voltage; and The second set of multiple fifth storage cells are to be written with data corresponding to any one of the multiple threshold voltage distributions below the first threshold voltage; and The circuit Measure the first characteristic of each of the plurality of fourth memory cells. Based on the data written to the plurality of fourth memory cells respectively and the measurement results of the first characteristic, the voltage values ​​of the plurality of sixth programming voltages applied to the word lines are calculated. Measure the second characteristic of each of the plurality of fifth memory cells. Based on the data written to the plurality of fifth memory cells respectively and the measurement results of the second characteristic, the voltage values ​​of the plurality of seventh programming voltages applied to the word lines are calculated.

12. The storage device according to claim 6, wherein The plurality of memory cells are arranged along a first direction perpendicular to the surface of the substrate on which the memory cell array is disposed. The word lines are connected to the plurality of memory cells arranged along the first direction, and When writing the data, the plurality of storage cells arranged along the first direction and commonly connected to the word line are simultaneously driven.

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