Wafer etching method
By dividing the wafer into concentric ring areas and designing appropriate etching lithography line widths, the core particle loss and meteorological spacing problems caused by uneven etching rates during the wafer are solved, and efficient production of LED chips is achieved.
Patent Information
- Application Number
- CN202210390035.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-14
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2042-04-14
AI Technical Summary
During the deep etching process of wafers, the uneven etching rate of different regions of the wafers leads to loss of some LED core particles or the mesa spacing exceeds the requirements, affecting the cost of LED chip production.
The wafer is divided into concentric ring areas. Based on the correspondence between the line width of the etching lithography plate and the top width on the etching groove, the line width of the etching plate of each ring area is designed so that the top width on the etching groove does not exceed the mesa spacing, and deep etching is performed through the corresponding etching lithography plate.
Ensure that the top width of the etching groove does not exceed the table spacing when it reaches the depth, avoid the loss of LED core particles, keep the core particle arrangement unchanged, and reduce production costs.
Smart Images
Figure CN114843182B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a wafer etching method. Background Art
[0002] With the development of light-emitting diode (LED) technology, high-voltage LEDs and flip-chip LEDs are becoming increasingly popular. Both types of LED chips require deep etching during their production. Specifically, deep etching is performed in the area between the LED chips on the wafer, from the surface of the LED chips to the surface of the substrate (such as a sapphire substrate), penetrating the semiconductor layer.
[0003] Currently, inductively coupled plasma (ICP) etching technology is primarily used to deeply etch wafers. However, due to the uneven distribution of plasma concentration within the reaction chamber, different regions of the wafer have different etching rates. Consequently, within the same etching time, when the etching grooves in the regions with higher etching rates reach the etching depth, the etching grooves in the regions with lower etching rates have not yet reached the etching depth, resulting in the loss of some LED cores in the wafer. To avoid losing LED cores, the deep etching time needs to be increased. However, this will cause the top width of the etching grooves in the regions with higher etching rates to exceed the mesa spacing between adjacent LED cores, which is not permitted. Otherwise, the mesa spacing between LED cores needs to be increased, but this will affect the arrangement of the LED cores in the wafer, reducing the total number of LED cores produced in a wafer of the same size. This will also result in LED core losses, affecting production costs.
[0004] It can be seen that when deep etching the wafer, how to ensure that the top width of the etched grooves formed in the wafer does not exceed the mesa spacing between adjacent LED core particles has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention
[0005] To solve the above technical problems, an embodiment of the present application provides a wafer etching method, so that when the wafer is deeply etched, the top width of the etched grooves formed in the wafer after deep etching does not exceed the table spacing between adjacent LED core particles.
[0006] To achieve the above objectives, the present invention provides the following technical solutions:
[0007] A wafer etching method, comprising:
[0008] Divide the wafer to be etched into at least two concentric circular areas, each circular area corresponding to a radius value;
[0009] Based on the previously acquired correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the annular regions of different radii in the wafer and the line width of the etching photomask used, the line width of the etching photomask corresponding to each annular region in the wafer to be etched is designed;
[0010] Using an etching photomask with designed line widths corresponding to each circular area in the wafer to be etched, the layer to be etched in each circular area in the wafer to be etched is deeply etched, so that the upper top width of the etched groove formed after the layer to be etched in each circular area in the wafer to be etched is no greater than the first preset width.
[0011] Optionally, the process of obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the annular regions of different radii in the wafer and the line width of the etching photomask used includes:
[0012] Obtaining a corresponding relationship between an etching rate corresponding to an annular region of different radius in the wafer and a radius value corresponding to the annular region in the wafer;
[0013] Obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular ring regions of different radii in the wafer, the etching rate corresponding to the circular ring region in the wafer, and the line width of the etching photomask used;
[0014] Based on the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer, and the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the etching rates corresponding to the circular ring areas in the wafer, as well as the line width of the etching photomask used, the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the line width of the etching photomask used is obtained.
[0015] Optionally, the process of obtaining the corresponding relationship between the etching rates corresponding to the circular ring regions of different radii in the wafer and the radius values corresponding to the circular ring regions in the wafer includes:
[0016] Dividing the first sample wafer into a plurality of concentric annular regions, each annular region in the first sample wafer corresponds to a radius value;
[0017] Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each annular region of the first sample wafer for a first preset time, and an etching rate corresponding to each annular region in the first sample wafer is obtained, wherein etched grooves formed in the layer to be etched in each annular region of the first sample wafer after deep etching for the first preset time do not penetrate the layer to be etched;
[0018] Based on the etching rates corresponding to the annular regions in the first sample wafer and the radius values corresponding to the annular regions in the first sample wafer, the corresponding relationship between the etching rates corresponding to the annular regions with different radii in the wafer and the radius values corresponding to the annular regions in the wafer is obtained.
[0019] Optionally, using an etching photomask with a preset line width, deep etching is performed on the to-be-etched layer in each annular region of the first sample wafer for a first preset time, and the etching rates corresponding to each annular region in the first sample wafer are obtained, including:
[0020] Using an etching photomask with a preset line width, deep etching is performed on the to-be-etched layer in each annular region of the first sample wafer for a first preset time, to obtain the depth of the etched groove formed in the to-be-etched layer in each annular region of the first sample wafer after the deep etching for the first preset time;
[0021] Based on the depth of the etched groove formed after deep etching of the to-be-etched layer in each annular region in the first sample wafer for a first preset time and the first preset time, the etching rate corresponding to each annular region in the first sample wafer is obtained.
[0022] Optionally, the corresponding relationship between the etching rate D corresponding to the circular ring region of different radius in the wafer and the radius value R corresponding to the circular ring region in the wafer is: D=D1-R*D2;
[0023] Wherein, D1 is the etching rate corresponding to the center of the wafer, and D2 is a constant simulated according to the etching rate D corresponding to each annular region in the first sample wafer and the radius value R corresponding to the annular region in the first sample wafer.
[0024] Optionally, the process of obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular ring regions of different radii in the wafer, the etching rate corresponding to the circular ring region in the wafer, and the line width of the etching photomask used includes:
[0025] Dividing the second sample wafer into a plurality of concentric annular regions, each annular region in the second sample wafer corresponds to a radius value;
[0026] Based on the corresponding relationship between the etching rates corresponding to the annular regions of different radii in the wafer and the radius values corresponding to the annular regions in the wafer, the etching rates corresponding to the annular regions in the second sample wafer are obtained, and based on the etching rates corresponding to the annular regions in the second sample wafer, a second preset time is set so that the bottom width of the etched groove formed after the to-be-etched layer in the annular region corresponding to the lowest etching rate in the second sample wafer is deep-etched for the second preset time is not less than the second preset width;
[0027] Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each annular region of the second sample wafer for a second preset time, to obtain an upper top width of an etched groove formed in the layer to be etched in each annular region of the second sample wafer after deep etching for the second preset time;
[0028] Based on the upper top width of the etched groove formed after the layer to be etched in each circular area in the second sample wafer is deep-etched for a second preset time, the etching rate corresponding to each circular area in the second sample wafer, and the preset line width, the correspondence between the upper top width of the etched groove formed after the layer to be etched in the circular areas of different radii in the wafer is deep-etched, the etching rate corresponding to the circular area in the wafer, and the line width of the etching photomask used is obtained.
[0029] Optionally, the corresponding relationship between the top width K of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer, the etching rate D corresponding to the circular areas in the wafer, and the line width K1 of the etching photomask used is: K=K1+D*K2;
[0030] Among them, K2 is a constant simulated based on the upper top width K of the etched groove formed after the etched layer in each annular area in the second sample wafer is deeply etched for a second preset time, the etching rate D corresponding to each annular area in the second sample wafer, and the preset line width K1.
[0031] Optionally, based on a previously acquired correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the annular regions of different radii in the wafer and the line width of the etching photomask used, designing the line width of the etching photomask corresponding to each annular region in the to-be-etched wafer includes:
[0032] Setting a target width, wherein the target width is not greater than the first preset width;
[0033] Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer obtained in advance and the line width of the etching photoresist used, the line width of the etching photoresist required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular ring area in the wafer to be etched is equal to the target width is obtained, which is used as the line width of the etching photoresist designed corresponding to the circular ring area in the wafer to be etched.
[0034] Optionally, the first preset width is not greater than the mesa spacing between adjacent grains in the wafer to be etched.
[0035] Optionally, dividing the wafer to be etched into at least two concentric annular regions includes:
[0036] The radius of the wafer to be etched is divided into N equal parts, thereby dividing the wafer to be etched into N concentric ring areas, where N is an integer not less than 2.
[0037] Compared with the existing technology, the above technical solution has the following advantages:
[0038] The wafer etching method provided in the embodiment of the present application first divides the wafer to be etched into at least two concentric annular areas, and then designs the line width of the etching photoresist corresponding to each annular area in the wafer to be etched based on the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer obtained in advance and the line width of the etching photoresist used. That is, according to the correspondence, the line width of the etching photoresist required to be used when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer to be etched reaches a certain width can be obtained. Then, in the subsequent use of the to-be-etched The etching photomask with designed line width corresponding to each circular area in the wafer can make the upper top width of the etching groove formed after the layer to be etched in each circular area in the wafer to be etched is deep-etched not greater than the first preset width, so that when the etching grooves in each circular area in the wafer to be etched reach the etching depth, that is, when the layer to be etched is completely etched, the upper top width of the etching groove does not exceed the table spacing between adjacent LED core particles, thereby preventing the loss of LED core particles and affecting the arrangement of the LED core particles, thereby reducing the production cost of the LED chip.
[0039] Furthermore, a target width can also be set. Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer obtained in advance and the line width of the etching photomask used, the line width of the etching photomask required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular area in the wafer to be etched can be obtained to be equal to the target width. This is used as the line width of the etching photomask designed corresponding to the circular area in the wafer to be etched, and ultimately the upper top width of the etching groove in each circular area in the wafer to be etched is equal to the target width, thereby ensuring the uniformity of the upper top width of the etching groove in each circular area in the wafer to be etched. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0041] Figure 1Schematic diagram of deep etching of a wafer using an ICP etching machine;
[0042] Figure 2 A schematic flow chart of a wafer etching method provided in an embodiment of the present application;
[0043] Figure 3 and Figure 4 A schematic diagram of dividing a wafer to be etched into at least two concentric ring areas;
[0044] Figure 5 A schematic diagram of a process for obtaining the corresponding relationship between the top width of the etched groove formed after deep etching of the to-be-etched layer in annular regions of different radii in the wafer and the line width of the etching photomask used in the wafer etching method provided in an embodiment of the present application;
[0045] Figure 6 A schematic diagram of a process for obtaining a corresponding relationship between etching rates corresponding to circular ring regions of different radii in a wafer and the radius values corresponding to the circular ring regions in the wafer in the wafer etching method provided in an embodiment of the present application;
[0046] Figure 7 In the wafer etching method provided in the embodiment of the present application, a schematic flow chart of a process for obtaining an etching rate corresponding to each circular area in the first sample wafer is provided by using an etching photomask with a preset line width to deeply etch the to-be-etched layer in each circular area in the first sample wafer for a first preset time;
[0047] Figure 8 A schematic flow chart of obtaining the corresponding relationship between the top width of an etched groove formed after deep etching of a layer to be etched in annular regions of different radii in a wafer, the etching rate corresponding to the annular region in the wafer, and the line width of the etching photomask used in the wafer etching method provided in an embodiment of the present application;
[0048] Figure 9 is a schematic cross-sectional view of an etching groove formed after a layer to be etched in a wafer is deeply etched;
[0049] Figure 10 A schematic diagram of a process for designing the line width of the etching photomask corresponding to each circular region in the wafer to be etched, based on the previously acquired correspondence between the top width of the etched groove formed after deep etching of the layer to be etched in circular regions of different radii in the wafer and the line width of the etching photomask used in the wafer etching method provided in an embodiment of the present application;
[0050] Figure 11 A schematic diagram of a partial top view of a wafer. DETAILED DESCRIPTION
[0051] Figure 1A schematic diagram of deep etching of a wafer using an ICP etching machine is given, as shown in Figure 1 As shown, in the reaction chamber, the wafer 01 is placed on the aluminum plate 02 , and the edge area of the wafer 01 is covered by the quartz cover plate 03 .
[0052] The inventors have discovered that the plasma concentration distribution in the reaction chamber is affected by the quartz cover plate 03, resulting in a plasma edge effect. This results in different etching rates corresponding to different areas of the wafer 01. Specifically, the etching rate corresponding to the central area of the wafer 01 is higher, while the etching rate corresponding to the edge area of the wafer 01 is lower. Therefore, within the same etching time, when the etching groove in the central area of the wafer 01 reaches the etching depth, that is, when it penetrates the semiconductor layer from the surface of the LED core to the substrate, the etching groove in the edge area of the wafer 01 has not yet reached the etching depth, that is, the etching is not clean. To address this problem, the following two methods are currently used:
[0053] The first method is to perform a buckle design on the edge area of the wafer, that is, directly discard the LED core particles in the edge area of wafer 01. However, this will inevitably lose the LED core particles in the edge area of wafer 01, affecting the production cost of the LED chip.
[0054] The second method: To utilize the LED cores in the edge area of wafer 01, the deep etching time can be increased to ensure that the etched grooves in the edge area of wafer 01 also reach the etching depth, that is, the edge area of wafer 01 can also be etched cleanly. However, this will cause the top width of the etched grooves in the center area of wafer 01 to be wider, even exceeding the mesa spacing between adjacent LED cores, which is not allowed. To this end, the mesa spacing between adjacent LED cores needs to be increased, but this will affect the arrangement of the LED cores in wafer 01, resulting in a reduction in the total number of LED cores produced in a wafer of the same size. This will also result in LED core loss, affecting the production cost of the LED chip.
[0055] Moreover, since the etching rates corresponding to different areas of the wafer are different, the top width and bottom width of the etched grooves formed after deep etching in different areas of the wafer will also vary greatly.
[0056] Therefore, as described in the background technology section, when deep etching is performed on the wafer, how to ensure that the top width of the etched grooves formed in the wafer does not exceed the table spacing between adjacent LED core particles has become a technical problem that needs to be solved urgently by technical personnel in this field.
[0057] The inventors further discovered that when deep etching is performed on a wafer, not only does the etching rate affect the upper width of the etched groove formed in the wafer after deep etching, but the line width of the etching photomask used also affects the upper width of the etched groove formed in the wafer after deep etching. In the prior art, when deep etching is performed on a wafer, the line widths of the etching photomasks used are all equal, and the etching photomasks used are arranged in an array on the entire wafer.
[0058] In view of this, an embodiment of the present application provides a wafer etching method, which first divides the wafer to be etched into at least two concentric annular areas, and then designs the line width of the etching photoresist corresponding to each annular area in the wafer to be etched based on the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer and the line width of the etching photoresist used. That is, according to the correspondence, the line width of the etching photoresist required to be used when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer to be etched reaches a certain width can be obtained. Then, in the subsequent use The etching photomask with designed line width corresponding to each circular area in the wafer to be etched can make the upper top width of the etching groove formed after the layer to be etched in each circular area in the wafer to be etched is deep-etched not greater than the first preset width, so that when the etching grooves in each circular area in the wafer to be etched reach the etching depth, that is, when the layer to be etched is completely etched, the upper top width of the etching groove does not exceed the table spacing between adjacent LED core particles, thereby preventing the loss of LED core particles and affecting the arrangement of the LED core particles, thereby reducing the production cost of the LED chip.
[0059] Furthermore, a target width can also be set. Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer obtained in advance and the line width of the etching photomask used, the line width of the etching photomask required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular area in the wafer to be etched can be obtained to be equal to the target width. This is used as the line width of the etching photomask designed corresponding to the circular area in the wafer to be etched, and ultimately the upper top width of the etching groove in each circular area in the wafer to be etched is equal to the target width, thereby ensuring the uniformity of the upper top width of the etching groove in each circular area in the wafer to be etched.
[0060] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0062] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.
[0063] Figure 2 A schematic flow chart of the wafer etching method provided in the embodiment of the present application is given, as shown in FIG. Figure 2 As shown, the wafer etching method includes:
[0064] S100: Divide a wafer to be etched into at least two concentric circular areas, each of which corresponds to a radius value.
[0065] Optionally, in one embodiment of the present application, dividing the wafer to be etched into at least two concentric annular regions includes:
[0066] The radius of the wafer to be etched is divided into N equal parts, thereby dividing the wafer to be etched into N concentric ring areas, where N is an integer not less than 2.
[0067] In other embodiments of the present application, the radius of the wafer to be etched may be divided into N segments of unequal amounts, thereby dividing the wafer to be etched into N concentric circular ring areas, which is not limited in the present application.
[0068] For example, since the plasma concentration distribution corresponding to the center area of the wafer is relatively uniform, the etching rate corresponding to the center area of the wafer is also relatively consistent. Therefore, Figure 3 As shown, the central area of the wafer 100 to be etched can be set as the first part 110, and the other areas of the wafer 100 to be etched except the central area 110 can be set as the second part 120, so that the second part 120 of the wafer to be etched can be divided into at least one concentric ring area.
[0069] It should be noted that the center of each circular area in the wafer to be etched is the center of the wafer to be etched.
[0070] It should also be noted that each circular area in the wafer to be etched corresponds to a radius value. Since the circular area can be regarded as an inner circle dug out from an outer circle, the radius value corresponding to the circular area can be the outer circle radius value of the circular area, or the average of the outer circle radius value and the inner circle radius value of the circular area, or other values that can characterize the radius size of the circular area.
[0071] Usually, the radius of the annular area is represented by the outer radius of the annular area, for example, Figure 4 A schematic diagram of dividing the wafer 100 to be etched into at least two concentric ring areas is given, as shown in FIG. Figure 4 As shown, the outer circle radius value of the first circular area (which can be regarded as a circular area with an outer circle radius of R1 and an inner circle radius of 0) is R1, and the corresponding radius value of this circular area is R1; the outer circle radius value of the second circular area is R2, and the corresponding radius value of this circular area is R2; and so on, the outer circle radius value of the Nth circular area is Rn, and the corresponding radius value of this circular area is Rn.
[0072] S200: Based on the previously acquired correspondence between the top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer and the line width of the etching photomask used, the line width of the etching photomask corresponding to each circular area in the wafer to be etched is designed.
[0073] Optionally, in one embodiment of the present application, Figure 5 As shown, the process of obtaining the corresponding relationship between the top width of the etching groove formed after the to-be-etched layer in the circular ring area with different radii in the wafer is deeply etched and the line width of the etching photomask used includes:
[0074] S10: Obtaining a corresponding relationship between etching rates corresponding to circular ring regions of different radii in the wafer and radius values corresponding to the circular ring regions in the wafer.
[0075] From the above analysis, we can see that Figure 1 As shown in the figure, during the deep etching of the wafer using the ICP etching machine, the plasma concentration distribution will be affected by the quartz cover plate, resulting in a higher etching rate corresponding to the center area of the wafer and a lower etching rate corresponding to the edge area of the wafer. It can be seen that the etching rates corresponding to the circular areas of different radii in the wafer are different, and there is a corresponding relationship between the etching rate corresponding to each circular area and the radius value corresponding to the circular area.
[0076] Optionally, in one embodiment of the present application, Figure 6 As shown, the process of obtaining the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer includes:
[0077] S11: Divide the first sample wafer into a plurality of concentric annular regions, where each annular region in the first sample wafer corresponds to a radius value.
[0078] Optionally, dividing the first sample wafer into a plurality of concentric ring areas includes:
[0079] The radius of the first sample wafer is divided into M equal parts, thereby dividing the first sample wafer into M concentric circular ring areas, where M is an integer not less than 2.
[0080] In other embodiments of the present application, the radius of the first sample wafer may be divided into M segments of unequal amounts, thereby dividing the first sample wafer into M concentric ring areas, which is not limited in the present application.
[0081] Similar to the wafer to be etched, in the first sample wafer, the radius value corresponding to each annular area can be the outer radius value of the annular area, or the average of the outer radius value and the inner radius value of the annular area, or other values that can characterize the radius size of the annular area.
[0082] The following description will be continued by taking as an example the case where the first sample wafer is divided into M concentric annular regions, and the radius value corresponding to each annular region is the outer circle radius value of the annular region.
[0083] S12: Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each circular area of the first sample wafer for a first preset time to obtain an etching rate corresponding to each circular area in the first sample wafer, wherein etched grooves formed after deep etching of the layer to be etched in each circular area of the first sample wafer for the first preset time do not penetrate the layer to be etched.
[0084] Specifically, in one embodiment of the present application, Figure 7 As shown, using an etching photomask with a preset line width, the to-be-etched layer in each annular region of the first sample wafer is deeply etched for a first preset time, and the etching rates corresponding to each annular region in the first sample wafer are obtained, including:
[0085] S12-1: Using an etching photomask with a preset line width, deep etching is performed on the to-be-etched layer in each annular region of the first sample wafer for a first preset time, to obtain the depth of the etched groove formed after the to-be-etched layer in each annular region of the first sample wafer is deep-etched for the first preset time.
[0086] Specifically, an etching photoresist array with a preset line width is arranged in the etching area of the first sample wafer, and an ICP etching machine is used to deeply etch the layer to be etched in each circular area of the first sample wafer for a first preset time, so as to obtain the depth H of the etched groove formed after the layer to be etched in each circular area of the first sample wafer is deeply etched for the first preset time.
[0087] S12-2: Based on the depth of the etched groove formed after the to-be-etched layer in each annular region in the first sample wafer is deeply etched for a first preset time and the first preset time, obtaining an etching rate corresponding to each annular region in the first sample wafer.
[0088] Specifically, the etching rate D=H / T1 corresponding to each annular region in the first sample wafer can be obtained by dividing the depth H of the etched groove formed after deep etching of the to-be-etched layer in each annular region in the first sample wafer for the first preset time by the first preset time T1.
[0089] It should be noted that, in step S12, the purpose of deep etching the layer to be etched in each annular area in the first sample wafer is to obtain the etching rate corresponding to each annular area in the first sample wafer, and the etching rate is obtained by dividing the etching depth (depth H of the etching groove) by the etching time (first preset time T1). Therefore, the etching depth cannot penetrate the layer to be etched, that is, the etching grooves formed after the layer to be etched in each annular area in the first sample wafer is deep etched for the first preset time do not penetrate the layer to be etched, thereby preventing over-etching of the layer to be etched and ensuring the accuracy of the etching rate corresponding to each annular area in the first sample wafer.
[0090] S13: Based on the etching rates corresponding to the respective annular regions in the first sample wafer and the radius values corresponding to the annular regions in the first sample wafer, a corresponding relationship between the etching rates corresponding to the annular regions with different radii in the wafer and the radius values corresponding to the annular regions in the wafer is obtained.
[0091] Specifically, the corresponding relationship between the etching rate D corresponding to the circular ring area of different radius in the wafer and the radius value R corresponding to the circular ring area in the wafer is:
[0092] D=D1-R*D2 (1)
[0093] Among them, D1 is the etching rate corresponding to the center of the wafer. The etching rate at the center of the first sample wafer can be used as D1. D2 is a constant simulated according to the etching rate D corresponding to each circular area in the first sample wafer and the radius value R corresponding to the circular area in the first sample wafer.
[0094] It should be noted that, through step S11, step S12 and step S13, the etching rate D corresponding to each circular area in the first sample wafer and the radius value R corresponding to the circular area in the first sample wafer can be obtained. Then, by performing linear fitting on the etching rate D corresponding to each circular area in the first sample wafer and the radius value R corresponding to the circular area in the first sample wafer, the corresponding relationship between the etching rate D corresponding to the circular areas of different radii in the wafer and the radius value R corresponding to the circular area in the wafer can be obtained as follows: D=D1-R*D2.
[0095] It can be seen from formula (1) that as the radius value R corresponding to the circular area in the wafer increases, the etching rate D corresponding to the circular area decreases linearly, that is, the larger the radius value R corresponding to the circular area in the wafer, the smaller the etching rate D corresponding to the circular area.
[0096] It should also be noted that in actual applications, when the ICP etching machines are different, the formulas for the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer may be different. However, the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer can be obtained according to steps S11, S12 and S13.
[0097] S20: Obtaining a correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer, the etching rate corresponding to the circular areas in the wafer, and the line width of the etching photomask used.
[0098] Optionally, in one embodiment of the present application, Figure 8 As shown, the process of obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer, the etching rate corresponding to the circular areas in the wafer, and the line width of the etching photomask used includes:
[0099] S21: Divide the second sample wafer into a plurality of concentric annular regions, where each annular region in the second sample wafer corresponds to a radius value.
[0100] Optionally, dividing the second sample wafer into a plurality of concentric ring areas includes:
[0101] The radius of the second sample wafer is divided into X equal parts, thereby dividing the second sample wafer into X concentric circular ring areas, where X is an integer not less than 2.
[0102] In other embodiments of the present application, the radius of the second sample wafer may be divided into X segments in unequal amounts, thereby dividing the second sample wafer into X concentric annular regions, which is not limited in the present application.
[0103] Similar to the wafer to be etched, in the second sample wafer, the radius value corresponding to each annular area can be the outer radius value of the annular area, or the average of the outer radius value and the inner radius value of the annular area, or other values that can characterize the radius size of the annular area.
[0104] The following description will be continued by taking as an example the case where the second sample wafer is divided into X concentric annular regions, and the radius value corresponding to each annular region is the radius value of the outer circle of the annular region.
[0105] S22: Based on the corresponding relationship between the etching rates corresponding to the circular areas of different radii in the wafer and the radius values corresponding to the circular areas in the wafer, the etching rates corresponding to the circular areas in the second sample wafer are obtained, and based on the etching rates corresponding to the circular areas in the second sample wafer, a second preset time is set so that the bottom width of the etched groove formed after the to-be-etched layer in the circular area corresponding to the lowest etching rate in the second sample wafer is deep-etched for the second preset time is not less than the second preset width.
[0106] In step S10, the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer has been obtained, and in step S21, the second sample wafer is divided into multiple concentric circular ring areas, each circular ring area corresponds to a radius value. Then, in step S22, the radius value corresponding to each circular ring area in the second sample wafer is substituted into the obtained corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer, and the etching rate corresponding to each circular ring area in the second sample wafer can be obtained.
[0107] It should be noted that Figure 9 The cross-sectional diagram of the etching groove formed after the etched layer in the wafer is deeply etched is given. Figure 9 It can be seen that when the wafer is deeply etched, the etching depth (i.e., the depth of the etching groove) is required to extend from the surface of the LED core to the surface of the substrate 10, penetrating the semiconductor layer 20. The semiconductor layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is the layer to be etched. After the second semiconductor layer 22 is formed, the mesa spacing W3 between adjacent LED cores is first etched. Then, when the wafer is deeply etched, the first semiconductor layer 21 (i.e., the layer to be etched) is etched. For example, the substrate 10 is a sapphire substrate, and the semiconductor layer 20 is a GaN semiconductor layer. Figure 9 As shown, the upper top width W2 and lower bottom width W1 of the etching groove formed after the layer to be etched in the wafer is deeply etched refer to the spacing between adjacent LED core particles of the etching groove. It can be seen that the upper top width W2 of the etching groove formed after the layer to be etched in the wafer is deeply etched is greater than its lower bottom width W1, that is, the etching groove is in an inverted trapezoidal shape.
[0108] In order to ensure that the semiconductor layer 20 between adjacent LED core particles in the wafer is etched cleanly, it is usually required that the bottom width W1 of the etched groove formed after the layer to be etched in the wafer is deeply etched is not less than a certain preset value. Therefore, in step S22, based on the etching rate corresponding to each annular region in the second sample wafer, a second preset time is set so that the bottom width of the etched groove formed after the layer to be etched in the annular region corresponding to the lowest etching rate in the second sample wafer is deeply etched for the second preset time is not less than the second preset width. Then, in the second sample wafer, since the etching rates corresponding to the other annular regions are all greater than the lowest etching rate, the bottom width of the etched groove formed after the layer to be etched in any annular region in the second sample wafer is deeply etched for the second preset time is not less than the second preset width, that is, the layer to be etched in any annular region in the second sample wafer can be etched clean.
[0109] Specifically, in one embodiment of the present application, based on the etching rates corresponding to the respective annular regions in the second sample wafer, setting the second preset time so that the bottom width of the etched groove formed after the to-be-etched layer in the annular region corresponding to the lowest etching rate in the second sample wafer is deep-etched for the second preset time is not less than the second preset width includes:
[0110] S22-1: Determine the minimum etching rate corresponding to the second sample wafer based on the etching rates corresponding to the circular regions in the second sample wafer;
[0111] S22-2: Based on the thickness of the layer to be etched in the second sample wafer and the corresponding lowest etching rate in the second sample wafer, a second preset time is set so that the bottom width of the etched groove formed after the layer to be etched in the circular area corresponding to the lowest etching rate in the second sample wafer is deep-etched for the second preset time is not less than the second preset width.
[0112] Specifically, in step S22-2, the thickness of the layer to be etched in the second sample wafer is divided by the corresponding minimum etching rate in the second sample wafer, and the etching time required to etch through the layer to be etched in the annular area with the lowest etching rate in the second sample wafer can be obtained. Then, the second preset time is set to be greater than the etching time. For example, the second preset time is set to 1.2 times or 1.5 times the etching time, so that the bottom bottom width of the etched groove formed after the layer to be etched in the annular area corresponding to the lowest etching rate in the second sample wafer is deeply etched for the second preset time is not less than the second preset width.
[0113] S23: Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each annular region of the second sample wafer for a second preset time, to obtain the top width of the etched groove formed after the layer to be etched in each annular region of the second sample wafer is deep-etched for the second preset time.
[0114] S24: Based on the upper top width of the etched groove formed after the layer to be etched in each circular area in the second sample wafer is deeply etched for a second preset time, the etching rate corresponding to each circular area in the second sample wafer, and the preset line width, obtain the correspondence between the upper top width of the etched groove formed after the layer to be etched in the circular areas of different radii in the wafer is deeply etched, the etching rate corresponding to the circular area in the wafer, and the line width of the etching photomask used.
[0115] Specifically, the corresponding relationship between the top width K of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer, the etching rate D corresponding to the circular area in the wafer, and the line width K1 of the etching photomask used is:
[0116] K=K1+D*K2 (2)
[0117] Among them, K2 is a constant simulated based on the upper top width K of the etched groove formed after the etched layer in each annular area in the second sample wafer is deeply etched for a second preset time, the etching rate D corresponding to each annular area in the second sample wafer, and the preset line width K1.
[0118] It should be noted that, through step S21, step S22, step S23 and step S24, the upper top width K of the etched groove formed after the layer to be etched in each circular area in the second sample wafer is deeply etched for the second preset time, the etching rate D corresponding to each circular area in the second sample wafer, and the preset line width K1 can be obtained. Then, by performing linear fitting on the upper top width K of the etched groove formed after the layer to be etched in each circular area in the second sample wafer is deeply etched for the second preset time, the etching rate D corresponding to each circular area in the second sample wafer, and the preset line width K1, the corresponding relationship between the upper top width K of the etched groove formed after the layer to be etched in the circular areas of different radii in the wafer is deeply etched, the etching rate D corresponding to the circular area in the wafer, and the line width K1 of the etching photomask used can be obtained as follows: K=K1+D*K2.
[0119] It can be seen from formula (2) that when the line width K1 of the etching photomask used remains unchanged, as the etching rate D corresponding to the circular ring area in the wafer increases, the upper top width K of the etching groove formed after the layer to be etched in the circular ring area in the wafer is deeply etched increases linearly, that is, the larger the etching rate D corresponding to the circular ring area in the wafer, the larger the upper top width K of the etching groove formed after the layer to be etched in the circular ring area in the wafer is deeply etched.
[0120] It can also be seen from formula (2) that when the etching rate D corresponding to each circular area in the wafer remains unchanged, as the line width K1 of the etching photomask used increases, the upper top width K of the etching groove formed after the to-be-etched layer in the circular area of the wafer is deeply etched increases linearly, that is, the larger the line width K1 of the etching photomask used is, the larger the upper top width K of the etching groove formed after the to-be-etched layer in the circular area of the wafer is deeply etched.
[0121] Since the etching rate D corresponding to each circular area in the wafer is mainly affected by the plasma concentration distribution in the reaction chamber, in the wafer etching method provided in this embodiment, for any circular area in the wafer to be etched, assuming that the etching rate D in the circular area is unchanged, then, based on the linear relationship between the upper top width K of the etching groove formed after the layer to be etched corresponding to the circular area is deeply etched and the etching photomask K1 used, the line width K1 of the etching photomask corresponding to the circular area is designed, so that the upper top width K of the etching groove formed after the layer to be etched in the circular area is deeply etched does not exceed the table spacing between adjacent LED core particles in the wafer.
[0122] S30: Based on the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer, and the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the etching rates corresponding to the circular ring areas in the wafer, as well as the line width of the etching photomask used, the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the line width of the etching photomask used is obtained.
[0123] Specifically, the corresponding relationship between the etching rate D corresponding to the circular ring area of different radius in the wafer and the radius value R corresponding to the circular ring area in the wafer is shown in formula (1). The corresponding relationship between the upper top width K of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring area of different radius in the wafer and the etching rate D corresponding to the circular ring area in the wafer, as well as the line width K1 of the etching photomask used is shown in formula (2). Then, the corresponding relationship between the upper top width K1 of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring area of different radius R in the wafer and the line width K1 of the etching photomask used can be obtained as follows:
[0124] K=K1+(D1-R*D2)*K2 (3)
[0125] Among them, D2 and K2 are constants.
[0126] Optionally, in one embodiment of the present application, Figure 10As shown, based on the previously obtained correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer and the line width of the etching photomask used, the line width of the etching photomask corresponding to each circular area in the to-be-etched wafer is designed to include:
[0127] S210: Setting a target width, where the target width is not greater than the first preset width.
[0128] S220: Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer obtained in advance and the line width of the etching photomask used, the line width of the etching photomask required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular area in the wafer to be etched is equal to the target width is obtained, and this is used as the line width of the etching photomask designed corresponding to the circular area in the wafer to be etched.
[0129] Specifically, assuming that the target width is K3, then, by substituting K=K3 in formula (3), the line width K1 of the etching photomask required when the top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular area with different radius R in the to-be-etched wafer is equal to K3 can be obtained, which is used as the line width of the etching photomask designed corresponding to the circular area in the to-be-etched wafer.
[0130] S300: Using an etching photomask with designed line widths corresponding to the circular areas in the wafer to be etched, deep etching is performed on the layer to be etched in each circular area in the wafer to be etched, so that the upper top widths of the etched grooves formed after the layer to be etched in each circular area in the wafer to be etched is not greater than a first preset width.
[0131] Figure 11 A partial top view of the wafer is given, combined with Figure 9 From the cross-sectional schematic diagram of the etched groove in the wafer, it can be seen that the upper top width W2 of the etched groove formed after the etched layer 21 in each circular area of the wafer to be etched is deeply etched should not be greater than the table spacing W3 between adjacent LED grains in the wafer to be etched. Therefore, the first preset width can be set to be no greater than the table spacing W3 between adjacent LED grains in the wafer to be etched.
[0132] From the above analysis, it can be seen that after step S210 and step S220, the line width K1 of the etching photomask required when the top width of the etched groove formed after the to-be-etched layer is deeply etched in the annular regions of different radii R in the to-be-etched wafer is equal to the target width K3 is obtained, and is used as the line width of the etching photomask designed corresponding to the annular region in the wafer to be etched. Then, in step S300, the etching photomask with the designed line width corresponding to each annular region in the wafer to be etched is used to deeply etch the to-be-etched layer in each annular region in the wafer to be etched, so that the top width of the etched groove formed after the to-be-etched layer in each annular region in the wafer to be etched is not greater than the first preset width, including:
[0133] Using an etching photomask with designed line width corresponding to each circular area in the wafer to be etched, the layer to be etched in each circular area in the wafer to be etched is deeply etched, so that the upper top width of the etched groove formed after the layer to be etched in each circular area in the wafer to be etched is equal to the target width.
[0134] It can be seen that the wafer etching method provided in the embodiment of the present application utilizes an etching photomask with a designed line width corresponding to each circular area in the wafer to be etched to perform deep etching on the layer to be etched in each circular area in the wafer to be etched. This not only ensures that the upper top width of the etched groove formed after the layer to be etched in each circular area in the wafer to be etched is deep-etched does not exceed the table spacing between adjacent LED grains in the wafer, but also further ensures that the upper top width of the etched groove formed after the layer to be etched in each circular area in the wafer to be etched is equal, that is, ensures the uniformity of the upper top width of the etched groove in the wafer to be etched.
[0135] It should be noted that the sizes of the wafer to be etched, the first sample wafer and the second sample wafer are all the same, so as to ensure that the correspondence between the top width of the etched groove formed after the layer to be etched is deeply etched in the circular areas of different radii in the wafers obtained based on the first sample wafer and the second sample wafer and the line width of the etching photomask used is applicable to the wafer to be etched.
[0136] Among them, the first sample wafer and the second sample wafer can also be the same sample wafer, but the area corresponding to the deep etching of the sample wafer for the first preset time is different from the area corresponding to the deep etching of the sample wafer for the second preset time. This is because the etching groove formed after the sample wafer is deep etched for the first preset time does not penetrate the layer to be etched, while the etching groove formed after the sample wafer is deep etched for the second preset time penetrates the layer to be etched, and the bottom width of the etching groove is not less than the second preset width.
[0137] It should also be noted that the thickness of the layer to be etched in the second sample wafer is equal to the thickness of the layer to be etched in the wafer to be etched. Therefore, the upper top width of the etching groove formed after the second sample wafer is deep-etched for a second preset time can be used to obtain the correspondence between the upper top width of the etching groove formed after the layer to be etched is deep-etched in the circular ring area of different radius in the wafer and the line width of the etching photomask used. Then, using this correspondence, the line width of the etching photomask required when the upper top width of the etching groove formed after the wafer to be etched is deep-etched for a second preset time is equal to the target width is inferred as the line width of the etching photomask designed accordingly in the wafer to be etched.
[0138] Among them, the time for deep etching of the wafer to be etched is also the second preset time, so that the lower bottom width of the etching groove formed by the deep etching of the to-be-etched layer in the circular area of the wafer to be etched corresponding to the lowest etching rate after the second preset time is not less than the second preset width, that is, the lower bottom width of the etching groove formed by the deep etching of the to-be-etched layer in each circular area of the wafer to be etched after the second preset time is not less than the second preset width, and the upper top width of the etching groove formed by the deep etching of the to-be-etched layer in each circular area of the wafer to be etched after the second preset time is not greater than the first preset width. Therefore, the etching grooves in each circular area of the wafer to be etched can reach the etching depth, that is, they can all be etched cleanly, and the upper top width of the etching grooves does not exceed the table spacing between adjacent LED core particles, thereby not losing LED core particles, and ensuring that the upper top width of the etching grooves does not exceed the table spacing between adjacent LED core particles, does not affect the arrangement of the LED core particles, and reduces the production cost of the LED chip.
[0139] In summary, the embodiment of the present application provides a wafer etching method, first dividing the wafer to be etched into at least two concentric annular areas, and then based on the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer obtained in advance and the line width of the etching photomask used, the line width of the etching photomask corresponding to each annular area in the wafer to be etched is designed, that is, according to the correspondence, the line width of the etching photomask required to be used when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the annular areas of different radii in the wafer to be etched reaches a certain width can be obtained. Then, in the subsequent use of the to-be-etched The etching photomask with designed line width corresponding to each circular area in the etched wafer can make the upper top width of the etching groove formed after the layer to be etched in each circular area in the etched wafer is deeply etched not greater than the first preset width, so that when the etching grooves in each circular area in the etched wafer reach the etching depth, that is, when the layer to be etched is completely etched, the upper top width of the etching groove does not exceed the table spacing between adjacent LED core particles, thereby preventing the loss of LED core particles and affecting the arrangement of the LED core particles, thereby reducing the production cost of the LED chip.
[0140] Furthermore, a target width can also be set. Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer obtained in advance and the line width of the etching photomask used, the line width of the etching photomask required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular area in the wafer to be etched can be obtained to be equal to the target width. This is used as the line width of the etching photomask designed corresponding to the circular area in the wafer to be etched, and ultimately the upper top width of the etching groove in each circular area in the wafer to be etched is equal to the target width, thereby ensuring the uniformity of the upper top width of the etching groove in each circular area in the wafer to be etched.
[0141] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.
[0142] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A wafer etching method, characterized in that: The wafer includes a substrate and a semiconductor layer located on the substrate, and the wafer etching method includes: Divide the wafer to be etched into at least two concentric circular areas, each circular area corresponding to a radius value; Based on the previously acquired correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the annular regions of different radii in the wafer and the line width of the etching photomask used, the line width of the etching photomask corresponding to each annular region in the wafer to be etched is designed; Using an etching photomask with designed line widths corresponding to each circular area in the wafer to be etched, the layer to be etched in each circular area in the wafer to be etched is deeply etched, so that the upper top width of the etched groove formed after the layer to be etched in each circular area in the wafer to be etched is no greater than a first preset width, and the first preset width is no greater than the table spacing between adjacent grains in the wafer to be etched.
2. The method according to claim 1, characterized in that The process of obtaining the corresponding relationship between the top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the line width of the etching photomask used includes: Obtaining a corresponding relationship between an etching rate corresponding to an annular region of different radius in the wafer and a radius value corresponding to the annular region in the wafer; Obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular ring regions of different radii in the wafer, the etching rate corresponding to the circular ring region in the wafer, and the line width of the etching photomask used; Based on the corresponding relationship between the etching rates corresponding to the circular ring areas of different radii in the wafer and the radius values corresponding to the circular ring areas in the wafer, and the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the etching rates corresponding to the circular ring areas in the wafer, as well as the line width of the etching photomask used, the corresponding relationship between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer and the line width of the etching photomask used is obtained.
3. The method according to claim 2, characterized in that The process of obtaining the corresponding relationship between the etching rates corresponding to the circular ring regions of different radii in the wafer and the radius values corresponding to the circular ring regions in the wafer includes: Dividing the first sample wafer into a plurality of concentric annular regions, each annular region in the first sample wafer corresponds to a radius value; Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each annular region of the first sample wafer for a first preset time, and an etching rate corresponding to each annular region in the first sample wafer is obtained, wherein etched grooves formed in the layer to be etched in each annular region of the first sample wafer after deep etching for the first preset time do not penetrate the layer to be etched; Based on the etching rates corresponding to the annular regions in the first sample wafer and the radius values corresponding to the annular regions in the first sample wafer, the corresponding relationship between the etching rates corresponding to the annular regions with different radii in the wafer and the radius values corresponding to the annular regions in the wafer is obtained.
4. The method according to claim 3, characterized in that Using an etching photomask with a preset line width, the to-be-etched layer in each annular region of the first sample wafer is deeply etched for a first preset time, and the etching rates corresponding to each annular region in the first sample wafer are obtained, including: Using an etching photomask with a preset line width, deep etching is performed on the to-be-etched layer in each annular region of the first sample wafer for a first preset time, to obtain the depth of the etched groove formed in the to-be-etched layer in each annular region of the first sample wafer after the deep etching for the first preset time; Based on the depth of the etched groove formed after deep etching of the to-be-etched layer in each annular region in the first sample wafer for a first preset time and the first preset time, the etching rate corresponding to each annular region in the first sample wafer is obtained.
5. The method according to claim 4, characterized in that The corresponding relationship between the etching rate D corresponding to the circular area of different radius in the wafer and the radius value R corresponding to the circular area in the wafer is: D = D1-R*D2; Wherein, D1 is the etching rate corresponding to the center of the wafer, and D2 is a constant simulated according to the etching rate D corresponding to each annular region in the first sample wafer and the radius value R corresponding to the annular region in the first sample wafer.
6. The method according to claim 2, characterized in that The process of obtaining the corresponding relationship between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular ring regions of different radii in the wafer, the etching rate corresponding to the circular ring region in the wafer, and the line width of the etching photomask used includes: Dividing the second sample wafer into a plurality of concentric annular regions, each annular region in the second sample wafer corresponds to a radius value; Based on the corresponding relationship between the etching rates corresponding to the annular regions of different radii in the wafer and the radius values corresponding to the annular regions in the wafer, the etching rates corresponding to the annular regions in the second sample wafer are obtained, and based on the etching rates corresponding to the annular regions in the second sample wafer, a second preset time is set so that the bottom width of the etched groove formed after the to-be-etched layer in the annular region corresponding to the lowest etching rate in the second sample wafer is deep-etched for the second preset time is not less than the second preset width; Using an etching photomask with a preset line width, deep etching is performed on the layer to be etched in each annular region of the second sample wafer for a second preset time, to obtain an upper top width of an etched groove formed in the layer to be etched in each annular region of the second sample wafer after deep etching for the second preset time; Based on the upper top width of the etched groove formed after the layer to be etched in each circular area in the second sample wafer is deep-etched for a second preset time, the etching rate corresponding to each circular area in the second sample wafer, and the preset line width, the correspondence between the upper top width of the etched groove formed after the layer to be etched in the circular areas of different radii in the wafer is deep-etched, the etching rate corresponding to the circular area in the wafer, and the line width of the etching photomask used is obtained.
7. The method according to claim 6, characterized in that The corresponding relationship between the top width K of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer, the etching rate D corresponding to the circular area in the wafer, and the line width K1 of the etching photomask used is: K = K1 + D * K2; Among them, K2 is a constant simulated based on the upper top width K of the etched groove formed after the etched layer in each annular area in the second sample wafer is deeply etched for a second preset time, the etching rate D corresponding to each annular area in the second sample wafer, and the preset line width K1.
8. The method according to claim 1, characterized in that Based on the previously acquired correspondence between the top width of the etched groove formed after the to-be-etched layer is deeply etched in the circular areas of different radii in the wafer and the line width of the etching photomask used, the line width of the etching photomask corresponding to each circular area in the to-be-etched wafer is designed to include: Setting a target width, wherein the target width is not greater than the first preset width; Based on the target width and the correspondence between the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in the circular ring areas of different radii in the wafer obtained in advance and the line width of the etching photoresist used, the line width of the etching photoresist required when the upper top width of the etching groove formed after the to-be-etched layer is deeply etched in each circular ring area in the wafer to be etched is equal to the target width is obtained, which is used as the line width of the etching photoresist designed corresponding to the circular ring area in the wafer to be etched.
9. The method according to claim 1, characterized in that Dividing the wafer to be etched into at least two concentric ring areas includes: The radius of the wafer to be etched is divided into N equal parts, thereby dividing the wafer to be etched into N concentric ring areas, where N is an integer not less than 2.
Citation Information
Patent Citations
Multi-ring beam shaper and manufacturing method thereof
CN101930090A
Method of using critical dimension mapping to qualify a reticle used in integrated circuit fabrication
US6345210B1