Contact hole etching method for CMOS device and CMOS device manufacturing method

Abstract

The present invention provides a contact hole etching method for a CMOS device and a CMOS device manufacturing method. After the device layer is formed through a front-end process, an etch stop layer is formed on the gate and active area of ​​the device layer, a carbon cap layer is formed on the etch stop layer, or carbon is ion-implanted into the etch stop layer to form a carbon-rich layer on the surface of the etch stop layer, and then an interlayer dielectric layer is formed on the etch stop layer. Due to the presence of the carbon cap layer or the carbon-rich layer above the etch stop layer, when etching to a shallower etch stop layer, a large amount of polymer will be formed in the etch stop layer, and the polymer will protect the etch stop layer from being further etched. Therefore, in the subsequent etching process of the deeper contact holes, the shallower contact holes can be effectively protected from over-etching until the etching of the deeper contact holes is completed. This avoids over-etching and also ensures that the deeper contact holes can be fully etched, avoiding the phenomenon of insufficient etching.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a contact hole etching method for a CMOS device and a CMOS device manufacturing method. Background Art

[0002] In semiconductor devices, contacts are typically formed on the gate and active region (i.e., source or drain). In CMOS devices, the contacts on the active region are typically deeper than those on the gate. In other advanced technologies, such as FDSOI (fully depleted silicon on insulator) and 3D NAND, contacts with different depths to the active region exist.

[0003] In the prior art, contact holes in semiconductor devices are typically formed by simultaneous etching. At this point, for gates and active areas of varying depths, shallower contact holes may be over-etched, while shallower contact holes may be under-etched. Both over- and under-etching can lead to poor device conductivity or even short circuits. To address this issue, different etching masks can be used to perform step-by-step etching for contact holes of varying depths, but this approach undoubtedly increases device manufacturing costs. This issue is particularly prominent for FDSOI and 3D NAND, which have more contact holes of varying depths.

[0004] Therefore, there is an urgent need for a method that can solve the problems of over-etching and under-etching of contact holes of different depths without significantly increasing the cost of the device. Summary of the Invention

[0005] In view of the above-mentioned problems and defects in etching contact holes of different depths in semiconductor devices, the present invention provides a contact hole etching method for CMOS devices and a CMOS device manufacturing method. After the device layer is formed by the front-end process, an etch stop layer is formed on the gate and active area of ​​the device layer, a carbon cap layer is formed on the etch stop layer or carbon is ion-implanted into the etch stop layer to form a carbon-rich layer on the surface of the barrier layer, and then an interlayer dielectric layer is formed on the etch stop layer. The interlayer dielectric layer is etched. Due to the presence of carbon in the carbon cap layer or the etch stop layer above the etch stop layer, when etching to the etch stop layer with a shallower depth, a large amount of polymer will be formed in the etch stop layer. The polymer will protect the etch stop layer from being further etched. Therefore, in the subsequent etching process of contact holes with a deeper depth, the contact holes with a shallower depth can be effectively protected from over-etching until the etching of the contact holes with a deeper depth is completed.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a contact hole etching method for a CMOS device, the method comprising the following steps:

[0007] forming a device layer on a substrate, wherein the device layer includes a gate and an active region, wherein the gate and the active region are located at different depth planes;

[0008] forming an etch stop layer above the gate and the active area, wherein the etch stop layer is a carbon-containing etch stop layer;

[0009] forming an interlayer dielectric layer above the etch stop layer;

[0010] Etching the interlayer dielectric layer until a contact hole is formed above the etch stop layer;

[0011] removing a polymer formed at the bottom of the contact hole during etching;

[0012] The etch stop layer is continuously etched until a contact hole is formed above the gate and the active region.

[0013] Optionally, forming an etch stop layer above the gate and the active area includes:

[0014] forming a silicon nitride layer above the gate and the active area;

[0015] A carbon cap layer is deposited over the silicon nitride layer.

[0016] Optionally, the thickness of the carbon cap layer is less than or equal to 1 nm.

[0017] Optionally, forming an etch stop layer above the gate and the active area includes:

[0018] forming a silicon nitride layer above the gate and the active area;

[0019] Carbon is implanted into the silicon nitride layer to form a carbon-rich layer on the surface of the barrier layer.

[0020] Optionally, the concentration of carbon implanted into the barrier layer is between 1E15 cm-2 and 1E16 cm-2, and the implantation energy is less than 5 KeV.

[0021] Optionally, removing the polymer formed at the bottom of the contact hole during the etching process includes: performing dry etching using chlorine-containing plasma.

[0022] Optionally, removing the polymer formed at the bottom of the contact hole during the etching process includes:

[0023] Wet etching is performed using a diluted hydrofluoric acid solution;

[0024] Rinse with deionized water.

[0025] According to another aspect of the present invention, a method for manufacturing a CMOS device is provided, the method comprising the following steps:

[0026] The contact hole etching method of the CMOS device provided by the present invention forms contact holes on the gate and active area of ​​the CMOS device;

[0027] The contact hole is filled with a conductive material to form a contact.

[0028] As described above, the contact hole etching method for a CMOS device and the CMOS device manufacturing method provided by the present invention have at least the following beneficial technical effects:

[0029] The contact hole etching method for a CMOS device of the present invention forms an etch stop layer on the gate and active area of ​​the device layer after the device layer is formed through a front-end process, forms a carbon cap layer on the etch stop layer or ion-implants carbon into the etch stop layer, and then forms an interlayer dielectric layer on the etch stop layer. When the interlayer dielectric layer is etched, due to the presence of carbon in the carbon cap layer above the etch stop layer or in the etch stop layer, a large amount of polymer will be formed in the etch stop layer when etching to the shallower etch stop layer. The polymer will protect the etch stop layer from being further etched. Therefore, during the subsequent etching process of the deeper contact holes, the shallower contact holes can be effectively protected from over-etching until the etching of the deeper contact holes is completed. The carbon cap layer above the etch stop layer or the ion-implanted carbon in the etch stop layer can form a polymer during the etching process. Therefore, after a shallow contact hole is etched to the etch stop layer, when the interlayer dielectric layer is etched to form a deeper contact hole, the polymer can prevent the shallower etch stop layer from being further etched, thus avoiding over-etching. It also ensures that the deeper contact hole is fully etched, thus avoiding under-etching. The above method uses the same etch mask to etch contact holes of different depths simultaneously, which helps save manufacturing steps and manufacturing costs.

[0030] The CMOS device manufacturing method of the present invention adopts the above method of the present invention to form contact holes of different depths, then fills the contact holes with conductive material to form contacts, and then completes the remaining back-end processes of the CMOS device, which also has the above beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shown is a schematic structural diagram of contact hole etching at different depths in the prior art.

[0032] Figure 2 Shown is a flow chart of a contact hole etching method for a CMOS device provided in the first embodiment of the present invention.

[0033] Figure 3 The diagram shows a structure schematic diagram of forming an etch stop layer on a substrate having a device layer formed thereon.

[0034] Figure 4 Shown as Figure 3 Schematic diagram of the structure in which a carbon cap layer is formed above the etch stop layer.

[0035] Figure 5 Shown as Figure 4 Schematic diagram of a structure in which an interlayer dielectric layer is formed above the structure shown.

[0036] Figure 6 It shows a structural schematic diagram of etching the interlayer dielectric layer to the carbon cap layer above the gate under the protection of the mask layer.

[0037] Figure 7 Displayed as continued etching Figure 6 The structure diagram of the carbon cap layer formed on the source and drain electrodes is shown.

[0038] Figure 8 Show as removed Figure 7 Schematic diagram of the structure of the polymer at the bottom of the contact hole.

[0039] Figure 9 A schematic diagram showing the structure of etching the etch stop layer above the device layer to form a contact hole.

[0040] Figure 10 Shown is a structural schematic diagram of forming a carbon-rich layer on the surface of an etch stop layer in a contact hole etching method for a CMOS device provided in a second embodiment of the present invention.

[0041] Figure 11 It shows a structural schematic diagram of etching the interlayer dielectric layer to form contact holes under the protection of the mask layer.

[0042] Figure 12 Show as removed Figure 11 Schematic diagram of the structure of the polymer at the bottom of the structural pore is shown.

[0043] Figure 13 A schematic diagram showing the structure of etching the etch stop layer above the device layer to form a contact hole.

[0044] Figure 14 It shows a schematic structural diagram of filling a conductive material in a contact hole to form a contact in the manufacturing method of a CMOS device provided in embodiment 3 of the present invention.

[0045] Figure 15 Shown is a schematic structural diagram of filling a conductive material in a contact hole to form a contact in a method for manufacturing a CMOS device provided in a fourth embodiment of the present invention.

[0046] Reference Signs List

[0047] 10 substrate 100 substrate

[0048] 11 Source 101 Source

[0049] 12 Drain 102 Drain

[0050] 13 gate 103 gate

[0051] 14 Etch stop layer 104 Etch stop layer

[0052] 15 interlayer dielectric layer 105 carbon cap layer

[0053] 151 first dielectric layer 1050 polymer layer

[0054] 152 second dielectric layer 106 interlayer dielectric layer

[0055] 011 Source contact hole 107 Mask layer

[0056] 012 drain contact hole 1010 source contact hole

[0057] 013 Gate contact hole 1020 Drain contact hole

[0058] 01 Etching less than 1030 gate contact hole

[0059] 02 Over-etching 205 carbon-rich layer

[0060] 110 Source contact 2050 Polymer layer

[0061] 130 Gate contact 120 Drain contact DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0064] Example 1

[0065] In semiconductor devices, contacts are usually formed on the gate and active region (i.e., source or drain). Figure 1 As shown, taking a CMOS device as an example, a device layer is formed in a substrate 10, and the device layer includes a source 11 and a drain 12 located inside the substrate and a gate 13 located above the substrate. In this case, the source and drain have a deeper depth than the gate. An interlayer dielectric layer 15 (usually a multi-layer structure, such as Figure 1 When the first dielectric layer 151 and the second dielectric layer 152 as shown in FIG. 1 are etched to form the source contact hole 011, the drain contact hole 012 and the gate contact hole 013, they are usually etched simultaneously. Figure 1 As shown, over-etching 02 occurs at the bottom of the shallow gate contact hole 013, while under-etching 01 occurs at the bottom of the deeper source contact holes 011 and drain contact holes 012. Both over-etching 02 and under-etching 01 will cause the conductivity of the contacts subsequently formed in the contact holes to deteriorate, affecting the electrical performance of the device.

[0066] In view of the above defects, this embodiment provides a contact hole etching method for a CMOS device, in which an etching stop layer containing carbon is formed above the device layer to eliminate the phenomenon of insufficient etching or over-etching. Figure 2 As shown, the method includes the following steps:

[0067] Step S101: forming a device layer on a substrate, wherein the device layer includes a gate and an active region, and the gate and the active region are located at different depth planes;

[0068] like Figure 3 As shown, a device layer is formed on a substrate 100. Taking a CMOS device as an example, the device layer includes an active region and a gate 103. The active region is specifically a source 101 and a drain 102. The source 101 and the drain 102 are formed in the substrate, as shown in FIG. Figure 3 As shown, it is formed below the surface of the substrate 100. The second gate 103 is formed above the substrate 100. The substrate 100 can be selected according to the actual requirements of the device, for example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc.

[0069] Step S102: forming an etch stop layer above the gate and the active area, wherein the etch stop layer is a carbon-containing etch stop layer;

[0070] Experimental studies have shown that carbon-based polymers can maintain the morphology of the material or film being etched during anisotropic etching in dry etching processes. Therefore, the present invention utilizes this characteristic to form a carbon-containing etch stop layer above the gate and active layer. The carbon in the etch stop layer reacts with the etching gas to form a carbon-based polymer when etching reaches it, thereby preventing further etching.

[0071] In this embodiment, first, Figure 3 As shown, an etch stop layer 104 is formed above the gate and the active area. The etch stop layer can be a SiN layer or a stack of SiN and SiO2. Figure 4 As shown, a thin carbon cap layer 105 is formed on the etch stop layer 104. For example, carbon can be deposited on the etch stop layer using methods such as CVD (chemical vapor deposition), ALD (atomic layer deposition), or PVD (physical vapor deposition) to form the carbon cap layer 105. Preferably, the thickness of the carbon cap layer 105 is controlled to be less than or equal to 1 nm.

[0072] Step S103: forming an interlayer dielectric layer above the etch stop layer;

[0073] Step S104: etching the interlayer dielectric layer until a contact hole is formed above the etch stop layer;

[0074] like Figure 5 As shown in FIG. 1 , after forming the carbon cap layer 105, an interlayer dielectric layer is deposited on the carbon cap layer 105. The interlayer dielectric layer may be a SiO2 layer. Figure 6 As shown, a mask layer 107 is formed on the interlayer dielectric layer. The mask layer 107 can be formed by the following steps: forming an APF layer (Advanced Patterning Film), a DARC (Dielectric Anti-Reflection Layer), a BARC (Back Anti-Reflection Layer) and a photoresist layer on the interlayer dielectric layer in sequence; then performing exposure and development processes on the photoresist layer to form a patterned photoresist layer; etching the APF layer through the patterned photoresist layer to form a mask layer 107 with a contact hole pattern. Similarly, Figure 6 As shown, the interlayer dielectric layer is etched under the shielding of the mask layer 107, and firstly the carbon cap layer 105 with a shallow depth, that is, the carbon cap layer above the gate 103, is etched to form Figure 6The gate contact hole 1030 is shown. Dry etching is used to etch the interlayer dielectric layer. The etching gas is an etching gas containing C and F. At this time, the etching gas acts on the carbon cap layer 105 at the bottom of the shallow gate contact hole, forming a large amount of carbon-based polymer, which can prevent further etching. Then Figure 7 As shown, the interlayer dielectric layer is further etched to the carbon cap layer 105 above the deeper source 101 and drain 102, forming source contact holes 1010 and drain contact holes 1020. During the continued etching of the interlayer dielectric layer, the carbon-based polymer formed in the carbon cap layer above the gate 103 prevents the etch stop layer 104 above the gate 103 from being etched, effectively protecting the etch stop layer above the gate 103. This allows the integrity of the etch stop layer at a shallower depth to be protected while completing the etching of the deeper interlayer dielectric layer, thus avoiding over-etching or under-etching during the subsequent etching of the etch stop layer.

[0075] Step S105: removing the polymer formed at the bottom of the contact hole during the etching process;

[0076] As mentioned above, the carbon-containing polymer at the bottom of each contact hole prevents the etch stop layer from being etched. Figure 8 Before etching the stop layer shown, the carbon-containing polymer at the bottom of each contact hole is first removed to form Figure 8 The bottom portion shown includes the source contact hole 1010, drain contact hole 1020, and gate contact hole 1030 of the etch stop layer 104. The carbon-containing polymer can be removed using either dry etching or wet etching. For example, dry etching involves using a Cl-containing plasma to remove the carbon-containing polymer. When wet etching is used, the carbon-containing polymer is first etched with a diluted HF acid solution, followed by rinsing with deionized water to completely remove the carbon-containing polymer from the bottom of the contact hole. The HF acid can be diluted at a ratio of 50:1.

[0077] Step S106: continue etching the etch stop layer until a contact hole is formed above the gate and the active area.

[0078] After the carbon-containing polymer at the bottom of the contact hole is removed to expose the etch stop layer 104, Figure 9 As shown, the etch stop layer 104 above the source, drain and gate is formed Figure 9 The source contact hole 1010 , the drain contact hole 1020 and the gate contact hole 1030 are shown.

[0079] like Figure 4As shown, since a carbon cap layer is formed above the etch stop layer, the carbon-containing polymer formed by the carbon cap layer during the etching process can effectively protect the etch stop layer, eliminating the problem of over-etching or under-etching during the etching of contact holes of different depths. This can improve the electrical performance of the device.

[0080] Example 2

[0081] This embodiment also provides a contact hole etching method for a CMOS device, in which an etch stop layer comprising carbon is formed above the device layer to eliminate under-etching or over-etching. The similarities between this embodiment and the contact hole etching method for a CMOS device provided in the first embodiment are not repeated here. The differences are as follows:

[0082] In step S102, an etch stop layer is formed above the gate and active area. When the etch stop layer contains carbon, in this embodiment, a carbon-rich layer 205 is formed on the surface of the etch stop layer. Specifically, carbon particles are implanted into the surface of the etch stop layer using ion implantation. The implantation concentration is between 1E15 cm⁻² and 1E16 cm⁻², and the implantation energy is less than 5 KeV. The thickness of the formed carbon-rich layer 205 is also less than or equal to 1 nm.

[0083] After forming the carbon-rich layer 205, an interlayer dielectric layer 106 and a mask layer 107 are also formed on the etch stop layer. The interlayer dielectric layer is etched under the shielding of the mask layer 107 to form Figure 11 The shallow gate contact hole 1030 and the deeper source contact hole 1010 and drain contact hole 1020 are shown. In the deeper source contact hole, the carbon-rich layer 205 at the bottom of the contact hole also forms a carbon-containing polymer, preventing the etch stop layer above the shallow gate from being etched or damaged. Then, as shown in FIG. Figure 12 As shown in FIG, the carbon-containing polymer at the bottom of the contact hole is also removed until the etch stop layer 104 at the bottom of the contact hole is exposed. Figure 13 As shown, the etching stop layer 104 above the gate, source and drain is continuously etched until the gate contact hole 1030 , the source contact hole 1010 and the drain contact hole 1020 are completely formed.

[0084] like Figure 10 As shown, since carbon is injected into the etch stop layer to form a carbon-rich layer on its surface, the carbon-containing polymer formed in the carbon-rich layer during the etching process can effectively protect the etch stop layer, eliminating the problem of over-etching or under-etching during the etching of contact holes of different depths. This can improve the electrical performance of the device.

[0085] Example 3

[0086] This embodiment provides a method for manufacturing a CMOS device. The method first forms a device layer on a substrate through a front-end process. Taking a CMOS device as an example, the device layer includes a gate 103 , a source 101 , and a drain 102 .

[0087] Then, the contact hole etching method described in the first embodiment is used to form a gate contact hole 1030, a source contact hole 1010, and a drain contact hole 1020 above the device layer. The formation of the above contact holes can refer to the method described in the first embodiment and will not be described in detail here. Figure 14 As shown, each contact hole is filled with a conductive material to form a gate contact 130, a source contact 110, and a drain contact 120. In an optional embodiment, the conductive material filled is tungsten, and may also be other conductive materials such as copper and silver.

[0088] Since the contact holes of different depths are formed without defects of over-etching or under-etching, the device has good electrical performance after being filled with a conductive material to form contacts.

[0089] Example 4

[0090] This embodiment provides a method for manufacturing a CMOS device. The method first forms a device layer on a substrate through a front-end process. Taking a CMOS device as an example, the device layer includes a gate 103 , a source 101 , and a drain 102 .

[0091] Then, the contact hole etching method described in the second embodiment is used to form a gate contact hole 1030, a source contact hole 1010, and a drain contact hole 1020 above the device layer. The formation of the above contact holes can refer to the method described in the second embodiment and will not be described in detail here. Figure 15 As shown, each contact hole is filled with a conductive material to form a gate contact 130, a source contact 110, and a drain contact 120. In an optional embodiment, the conductive material filled is tungsten, and may also be other conductive materials such as copper and silver.

[0092] Since the contact holes of different depths are formed without defects of over-etching or under-etching, the device has good electrical performance after being filled with a conductive material to form contacts.

[0093] As described above, the contact hole etching method for a CMOS device and the CMOS device manufacturing method provided by the present invention have at least the following beneficial technical effects:

[0094] The contact hole etching method for a CMOS device of the present invention forms an etch stop layer on the gate and active area of ​​the device layer after the device layer is formed through a front-end process, forms a carbon cap layer on the etch stop layer or ion-implants carbon into the etch stop layer, and then forms an interlayer dielectric layer on the etch stop layer. When the interlayer dielectric layer is etched, due to the presence of carbon in the carbon cap layer above the etch stop layer or in the etch stop layer, a large amount of polymer will be formed in the etch stop layer when etching to the shallower etch stop layer. The polymer will protect the etch stop layer from being further etched. Therefore, during the subsequent etching process of the deeper contact holes, the shallower contact holes can be effectively protected from over-etching until the etching of the deeper contact holes is completed. The carbon cap layer above the etch stop layer or the ion-implanted carbon in the etch stop layer can form a polymer during the etching process. Therefore, after a shallow contact hole is etched to the etch stop layer, when the interlayer dielectric layer is etched to form a deeper contact hole, the polymer can prevent the shallower etch stop layer from being further etched, thus avoiding over-etching. It also ensures that the deeper contact hole is fully etched, thus avoiding under-etching. The above method uses the same etch mask to etch contact holes of different depths simultaneously, which helps save manufacturing steps and manufacturing costs.

[0095] The CMOS device manufacturing method of the present invention adopts the above method of the present invention to form contact holes of different depths, then fills the contact holes with conductive material to form contacts, and then completes the remaining back-end processes of the CMOS device, which also has the above beneficial effects.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A contact hole etching method for a CMOS device, characterized in that: The following steps are involved: forming a device layer on a substrate, wherein the device layer includes a gate and an active region, wherein the gate and the active region are located at different depth planes; forming an etch stop layer above the gate and the active area, wherein the etch stop layer is a carbon-containing etch stop layer, the etch stop layer includes a carbon-containing layer, and the thickness of the carbon-containing layer is less than or equal to 1 nm; forming an interlayer dielectric layer above the etch stop layer; Etching the interlayer dielectric layer until a contact hole is formed above the etch stop layer, wherein an etching gas containing C and F acts on the carbon-containing etch stop layer at the bottom of the contact hole to form a carbon-based polymer to prevent further etching; removing the carbon-based polymer formed at the bottom of the contact hole during the etching process; The etch stop layer is continuously etched until a contact hole is formed above the gate and the active region.

2. The contact hole etching method according to claim 1, wherein: Forming an etch stop layer above the gate and the active area, comprising: forming a silicon nitride layer above the gate and the active area; A carbon cap layer is deposited over the silicon nitride layer.

3. The contact hole etching method according to claim 1, wherein: Forming an etch stop layer above the gate and the active area, comprising: forming a silicon nitride layer above the gate and the active area; Carbon is implanted into the silicon nitride layer to form a carbon-rich layer on the surface of the etch stop layer.

4. The contact hole etching method according to claim 3, wherein: The concentration of carbon implanted in the etch stop layer is between 1E15 cm -2 ~ 1E16 cm -2 , the injection energy is less than 5Kev.

5. The contact hole etching method according to claim 1, wherein: Removing the polymer formed at the bottom of the contact hole during the etching process includes: performing dry etching using chlorine-containing plasma.

6. The contact hole etching method according to claim 1, wherein: Removing the polymer formed at the bottom of the contact hole during the etching process includes: Wet etching is performed using a diluted hydrofluoric acid solution; Rinse with deionized water.

7. A method for manufacturing a CMOS device, characterized in that: The following steps are involved: The contact hole etching method for a CMOS device according to any one of claims 1 to 6 forms contact holes in the gate and active area of ​​the CMOS device; The contact hole is filled with a conductive material to form a contact.

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