Driving backplane, display panel and electronic device

Abstract

The application provides a driving backboard, a display panel and an electronic device. The driving backboard comprises a substrate, a first power supply line and a first auxiliary power supply line arranged on opposite sides of the substrate. The first power supply line extends along a first direction and is electrically connected with the first auxiliary power supply line. The orthogonal projection of the first power supply line on the substrate coincides with the orthogonal projection of the first auxiliary power supply line on the substrate. In this way, the impedance of the first power supply line can be reduced. On the premise of not increasing the voltage drop of the first power supply line, a first power supply line with a smaller line width can be arranged, so that the transparency of the transparent display is improved, and the problem that the transparency of the existing transparent display is limited is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving backboard, a display panel and an electronic device. BACKGROUND

[0002] With the development of display technology, transparent display has been widely used. In addition to displaying pictures for users to watch, transparent display can also allow users to see the scenery on the other side relative to the user through the transparent display, greatly improving the applicability of display technology. However, the numerous metal traces in the transparent display seriously restrict the improvement of its transparency, such as the power voltage signal line (PVDD). In particular, in order to reduce the voltage drop (IR-Drop) of the power voltage signal line, the power voltage signal line is usually set to be larger, which further hinders the improvement of the transparency of the transparent display area. SUMMARY

[0003] The present application provides a driving backboard, a display panel and an electronic device to alleviate the technical problem that the transparency of the existing transparent display is restricted.

[0004] To solve the above problems, the technical solutions provided by the present application are as follows:

[0005] The present application provides a driving backboard, which comprises:

[0006] a substrate;

[0007] a first power line arranged on a first side of the substrate and extending in a first direction; and

[0008] a first auxiliary power line arranged on a second side of the substrate away from the first power line and electrically connected with the first power line.

[0009] Wherein, the orthographic projection of the first power line on the substrate coincides with the orthographic projection of the first auxiliary power line on the substrate.

[0010] In the driving backboard provided by the present application, the film layer thickness of the first power line is less than or equal to the film layer thickness of the first auxiliary power line.

[0011] In the driving backboard provided by the present application, the first power line comprises a first conductive part and at least one second conductive part electrically connected with the first conductive part; the substrate is provided with a first opening at a position corresponding to the second conductive part, the first opening exposes part of the second conductive part, and the first auxiliary power line is electrically connected with the corresponding second conductive part through the first opening.

[0012] In the driving backboard provided in the embodiments of the present application, the width of the second conductive part is greater than the width of the first conductive part.

[0013] In the driving backboard provided in the embodiments of the present application, the width of the first power line is greater than or equal to 4 microns.

[0014] In the driving backboard provided in the embodiments of the present application, the driving backboard further comprises:

[0015] The second power line is arranged on the first side of the substrate and is arranged in insulation with the first power line;

[0016] The second auxiliary power line is arranged on the second side of the substrate away from the second power line and is electrically connected with the second power line;

[0017] The orthographic projection of the second power line on the substrate coincides with the orthographic projection of the second auxiliary power line on the substrate.

[0018] In the driving backboard provided in the embodiments of the present application, the driving backboard further comprises a plurality of pixel units arranged in an array on the first side of the substrate, each pixel unit comprising at least three sub-pixels, each sub-pixel comprising a first electrode and a second electrode, the first electrode and the second electrode being arranged in insulation, the first power line being electrically connected with the first electrode, and the second power line being electrically connected with the second electrode.

[0019] In the driving backboard provided in the embodiments of the present application, the sub-pixel comprises a driving circuit, the first power line being electrically connected with the first electrode through the driving circuit, and the driving circuit comprising a plurality of transistors and at least one capacitor.

[0020] The driving backboard further comprises a first signal transfer line and a second signal transfer line arranged on the first side of the substrate, the first signal transfer line and the second signal transfer line both extending along a second direction and being arranged in insulation with each other, the first power line being electrically connected with the driving circuit of two of the three sub-pixels through the first signal transfer line, and the second power line being electrically connected with the second electrode of two of the three sub-pixels through the second signal transfer line.

[0021] The embodiments of the present application further provide a display panel comprising the driving backboard of any one of the foregoing embodiments.

[0022] The embodiments of the present application further provide an electronic device comprising a housing and the display panel of the foregoing embodiments, the housing being formed with a receiving cavity, and the display panel being assembled in the receiving cavity.

[0023] The application has the beneficial effects that: the driving backboard, the display panel and the electronic device provided by the application, the driving backboard comprises a substrate and a first power supply line and a first auxiliary power supply line arranged on opposite sides of the substrate, the first power supply line extends along a first direction and is electrically connected with the first auxiliary power supply line, and the orthogonal projection of the first power supply line on the substrate coincides with the orthogonal projection of the first auxiliary power supply line on the substrate, so that the impedance of the first power supply line can be reduced, and on the premise of ensuring that the voltage drop of the first power supply line is not increased, the first power supply line with a smaller line width can be arranged, so that the transparency of the transparent display is improved, and the problem that the transparency of the existing transparent display is restricted is solved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0025] Figure 1 A top view structural schematic diagram of the driving backboard provided by the embodiments of the application.

[0026] Figure 2 A partial cross-sectional structural schematic diagram of the driving backboard provided by the embodiments of the application.

[0027] Figure 3 A circuit structural schematic diagram of the driving circuit provided by the embodiments of the application.

[0028] Figure 4 A detailed structural schematic diagram of the active layer provided by the embodiments of the application.

[0029] Figure 5 A detailed structural schematic diagram of the first metal layer provided by the embodiments of the application.

[0030] Figure 6 A detailed structural schematic diagram of the second metal layer provided by the embodiments of the application.

[0031] Figure 7 A cross-sectional structural schematic diagram of the display panel provided by the embodiments of the application.

[0032] Figure 8 A cross-sectional structural schematic diagram of the electronic device provided by the embodiments of the application. DETAILED DESCRIPTION

[0033] The following description of the embodiments refers to the accompanying drawings, which are used to exemplify particular embodiments of the present application. Directional terms as used, such as up, down, right, left, front, back, rear, lateral, etc., are used for purposes of explanation with reference to the drawings. Thus, these directional terms are used in relation to the drawings and are not used to limit the present application. In the drawings, similar elements are designated with like reference numerals. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0034] Please refer to Figure 1 and Figure 2 , Figure 1 a top view of a driving backplane provided by an embodiment of the present application, Figure 2 a partial cross-sectional view of a driving backplane provided by an embodiment of the present application. The driving backplane 100 includes a substrate 10, a plurality of pixel units P arranged in an array on a first side of the substrate 10, and a first power line 20 and a second power line 30 located on opposite sides of the pixel units P. Each pixel unit P includes at least three sub-pixels (such as Figure 1 a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3) shown, each of the sub-pixels includes a first electrode 41 and a second electrode 42, the first electrode 41 and the second electrode 42 are insulatively arranged, the first power line 20 is electrically connected to the first electrode 41 to provide a power signal to the first electrode 41, and the second power line 30 is electrically connected to the second electrode 42 to provide a power signal to the second electrode 42.

[0035] Optionally, the first power line 20 is a VDD signal line, and the second power line 30 is a VSS signal line. The first power line 20 and the second power line 30 are located on opposite sides of the pixel units P, but the present application is not limited thereto. The first power line 20 and the second power line 30 of the present application can also be located on the same side of the pixel units P, but still need to be insulatively arranged between the first power line 20 and the second power line 30.

[0036] In an embodiment, the driving backplane 100 further comprises a first auxiliary power line 21 electrically connected with the first power line 20. The first power line 20 is disposed on the first side of the substrate 10 and extends along the first direction X. The first auxiliary power line 21 is disposed on the second side of the substrate 10 away from the first power line 20. The first power line 20 on the substrate 10 and the first auxiliary power line 21 on the substrate 10 are coincident in projection. Wherein the first side and the second side of the substrate 10 are opposite sides of the substrate 10.

[0037] By disposing the first auxiliary power line 21 electrically connected with the first power line 20 on the second side of the substrate 10, the impedance of the first power line 20 can be reduced, so that the minimum line width of the first power line 20 can be set according to the process capability without increasing the voltage drop of the first power line 20, for example, the line width of the first power line 20 is 4 microns, of course, the present application is not limited to this, the line width of the first power line 20 of the present application can be greater than or equal to 4 microns according to the actual process capability. At the same time, the first power line 20 on the substrate 10 and the first auxiliary power line 21 on the substrate 10 are coincident in projection, so that the line width of the first auxiliary power line 21 is the same as the line width of the first power line 20.

[0038] Optionally, the first power line 20 comprises a first conductive part 22 and at least one second conductive part 23 electrically connected with the first conductive part 22. The substrate 10 is provided with a first opening 211 at a position corresponding to the second conductive part 23, the first opening 211 exposes part of the second conductive part 23, and the first auxiliary power line 21 is electrically connected with the corresponding second conductive part 23 through the first opening 211.

[0039] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it can include a glass substrate and other hard transparent substrates; when the substrate 10 is a flexible substrate, it can include a polyimide (PI) film, an ultra-thin glass film and other flexible transparent substrates. Taking the glass substrate as an example, laser drilling and other processes can be used to drill holes on the substrate 10 corresponding to the position of the second conductive part 23 to form the first opening 211.

[0040] In an embodiment, the width D2 of the second conductive part 23 is greater than the width D1 of the first conductive part 22, i.e. the width of the first power line 20, and the width D2 of the second conductive part 23 is set to be greater than the width D1 of the first power line 20, so that a larger first opening 211 can be formed on the substrate 10, facilitating the implementation of the process and improving the reliability of the connection between the first auxiliary power line 21 and the first power line 20.

[0041] Alternatively, the number of the second conductive part 23 is multiple, to further improve the reliability of the connection between the first auxiliary power line 21 and the first power line 20. Each of the second conductive part 23 connects two adjacent first conductive parts 22, but the application is not limited thereto, and in some embodiments, the second conductive part 23 can also be located at both ends of the first power line 20. Moreover, the second conductive part 23 is located as far away from the pixel unit P as possible to avoid affecting the pixel unit P when forming the first opening 211.

[0042] The shape of the first opening 211 depends on the shape of the second conductive part 23. Optionally, the surface shape of the second conductive part 23 includes a square, a circle, etc., and correspondingly, the cross-sectional shape of the first opening 211 also includes a square, a circle, etc. For example, when the surface shape of the second conductive part 23 is a square, the cross-sectional shape of the first opening 211 can be a circle, and optionally, the diameter of the first opening 211 ranges from 10 microns to 50 microns. The opening of the first opening 211 near the second conductive part 23 completely falls within the coverage range of the second conductive part 23.

[0043] In an embodiment, the film thickness L1 of the first power line 20 is less than or equal to the film thickness L2 of the first auxiliary power line 21. Preferably, the film thickness L2 of the first auxiliary power line 21 is greater than the film thickness L1 of the first power line 20, for example, the film thickness L2 of the first auxiliary power line 21 is 5 to 10 times the film thickness L1 of the first power line 20, so that the impedance of the first power line 20 can be further reduced, and the line width of the first power line 20 can be set to the minimum within the process capability range, and the voltage drop of the first power line 20 can also be reduced.

[0044] In an embodiment, the driving backplane 100 further comprises a second auxiliary power line 31 electrically connected with the second power line 30. The second power line 30 is arranged on the first side of the substrate 10 and is insulated from the first power line 20. Optionally, the second power line 30 also extends along the first direction X, i.e., the second power line 30 is arranged in parallel with the first power line 20. The second auxiliary power line 31 is arranged on the second side of the substrate 10 away from the second power line 30. The orthogonal projection of the second power line 30 on the substrate 10 coincides with the orthogonal projection of the second auxiliary power line 31 on the substrate 10, so that the second auxiliary power line 31 is also arranged in parallel with the first auxiliary power line 21.

[0045] Optionally, the structure of the second power line 30 and the connection mode of the second auxiliary power line 31 with the second power line 30 are similar to the structure of the first power line 20 and the connection mode of the first auxiliary power line 21 with the first power line 20. Specifically, the second power line 30 comprises a third conductive part 32 and a fourth conductive part 33, and the width of the fourth conductive part 33 is greater than the width of the third conductive part 32. The substrate 10 is provided with a second opening 311 at a position corresponding to the fourth conductive part 33. The second opening 311 penetrates the substrate 10 and exposes part of the fourth conductive part 33. The second auxiliary power line 31 is electrically connected with the first power line 20 through the second opening 311.

[0046] It should be noted that the description of the second power line 30 and the second auxiliary power line 31 in the present embodiment is not exhaustive, and specific reference can be made to the description of the first power line 20 and the second auxiliary power line 31 in the above embodiments, which will not be described here.

[0047] In an embodiment, the sub-pixel comprises a driving circuit, and the first power line 20 is electrically connected with the first electrode 41 through the driving circuit. Specifically, the driving backplane 100 further comprises a first signal transfer line 51 and a second signal transfer line 52 arranged on the first side of the substrate 10. The first signal transfer line 51 and the second signal transfer line 52 both extend along a second direction Y and are insulated from each other. The first power line 20 is electrically connected with the driving circuit of two of the three sub-pixels through the first signal transfer line 51, and the second power line 30 is electrically connected with the second electrode 42 of the two of the three sub-pixels through the second signal transfer line 52. The first direction X is perpendicular to the second direction Y, such as the first direction X is a vertical direction and the second direction Y is a horizontal direction, but the present application is not limited thereto.

[0048] Optionally, the driving circuit comprises a plurality of transistors and at least one capacitor, and correspondingly, the driving backplane 100 further comprises a plurality of data lines DL extending along the first direction X and a plurality of gate scanning lines SL extending along the second direction Y, the gate scanning lines SL are used to control the switching of the transistors, and the data lines DL are used to provide driving voltage to the transistors and charge the capacitor when the transistors are turned on. Each of the gate scanning lines SL controls a row of the sub-pixels, each of the data lines DL connects a column of the sub-pixels, and the three sub-pixels of each of the pixel units P correspond to three data lines DL respectively. Wherein, "row" refers to the second direction Y, and "column" refers to the first direction X.

[0049] The structure of the driving circuit will be described in detail below taking the driving circuit of each of the sub-pixels comprising three transistors and one capacitor as an example:

[0050] Please refer to Figures 1 to 6 , Figure 3 a circuit structure diagram of the driving circuit provided by the embodiment of the present application, Figure 4 a detailed structure diagram of the active layer provided by the embodiment of the present application, Figure 5 a detailed structure diagram of the first metal layer provided by the embodiment of the present application, Figure 6 a detailed structure diagram of the second metal layer provided by the embodiment of the present application. The driving circuit comprises a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1, wherein the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a detection transistor used to compensate the driving circuit. The driving backplane 100 further comprises a detection signal line 60 electrically connected with the third transistor T3 and a third signal transfer line 53 used to transfer the detection signal line 60, and the detection signal line 60 is electrically connected with the third transistor T3 of two of the three sub-pixels through the third signal transfer line 53. Wherein, the detection signal line 60 extends along the first direction X, the third signal transfer line 53 extends along the second direction Y and is insulated from the first signal transfer line 51 and the second signal transfer line 52.

[0051] Specifically, as Figure 3As shown, the gate of the first transistor T1 is electrically connected with the gate scan line SL, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with the gate of the second transistor T2 and the first plate of the first capacitor C1. The source of the second transistor T2 is electrically connected with the first power supply line 20, the drain of the second transistor T2 is electrically connected with the second plate of the first capacitor C1, the drain of the third transistor T3 and the first electrode 41. The gate of the third transistor T3 is electrically connected with the gate scan line SL, and the source of the third transistor T3 is electrically connected with the detection signal line 60. The second power supply line 30 is electrically connected with the second electrode 42.

[0052] Next, the embodiment takes the second transistor T2 as an example to illustrate the specific film layer structure of each transistor, and continues to refer to Figure 2 , the second transistor T2 includes an active layer 71, a gate 72, a source 73 and a drain 74, and is arranged on the substrate 10. Specifically, the driving backboard 100 further includes a light shielding layer 13, a buffer layer 12, a gate insulating layer 14, an interlayer insulating layer 15 and a passivation layer 16 which are arranged in layers on the first side of the substrate 10.

[0053] Specifically, please refer to Figure 2 and Figure 4 , the light shielding layer 13 is arranged on the substrate 10, and the material of the light shielding layer 13 includes a metal with light shielding performance. The buffer layer 12 is arranged on the light shielding layer 13 and the substrate 10, and the material of the buffer layer 12 includes inorganic materials such as silicon oxide and silicon nitride to block water and oxygen. The active layer 71 of the second transistor T2 is arranged on the buffer layer 12 and corresponds to the light shielding layer 13. The light shielding layer 13 is used to shield the active layer 71 to avoid light irradiating the active layer 71, and at the same time, the light shielding layer 13 also serves as the second plate of the first capacitor C1.

[0054] Please refer to Figure 2 and Figure 5The gate insulating layer 14 is deposited on the active layer 71 and is arranged corresponding to the channel region of the active layer 71. The gate 72 of the second transistor T2 is arranged on the gate insulating layer 14 and is also arranged corresponding to the channel region of the active layer 71. Specifically, a first inorganic thin film and a first metal layer are deposited on the active layer 71 and the buffer layer 12, and the first metal layer is located on the side of the first inorganic thin film away from the active layer 71. The first metal layer and the first inorganic thin film are patterned, the first inorganic thin film forms the gate insulating layer 14, and the first metal layer forms the gate 72 of the second transistor T2, the gate scan line SL, the first signal transfer line 51, the second signal transfer line 52, the third signal transfer line 53, and the first plate C11 of the first capacitor C1. The interlayer insulating layer 15 is deposited on the gate 72 and the buffer layer 12, and the interlayer insulating layer 15 is patterned to form a plurality of vias, such as the first via 151 and the second via 152 located on both sides of the gate 72 of the second transistor T2.

[0055] Please refer to Figure 2 and Figure 6 The source 73 and the drain 74 of the second transistor T2 are arranged on the interlayer insulating layer 15, the source 73 is electrically connected to the source region of the active layer 71 through the first via 151 of the interlayer insulating layer 15, and the drain 74 is electrically connected to the drain region of the active layer 71 through the second via 152 of the interlayer insulating layer 15, wherein the source region and the drain region of the active layer 71 are located on both sides of the channel region of the active layer 71.

[0056] Specifically, a second metal layer is deposited on the interlayer insulating layer 15, and the second metal layer is patterned to form the source 73 and the drain 74 of the second transistor T2, and at the same time, the data line DL, the first power line 20, the second power line 30, the detection signal line 60, and the second plate C12 of the first capacitor C1 are formed. The first power line 20 is electrically connected to the first signal transfer line 51 through a via of the interlayer insulating layer 15, the second power line 30 is electrically connected to the second signal transfer line 52 through a via of the interlayer insulating layer 15, the detection signal line 60 is electrically connected to the third signal transfer line 53 through a via of the interlayer insulating layer 15, and the second plate C12 of the first capacitor C1 is electrically connected to the light shielding layer 13 through a via of the interlayer insulating layer 15.

[0057] It should be noted that the first power line 20 and the second power line 30 are not limited to be arranged in the second metal layer, for example, the first power line 20 and the second power line 30 can also be arranged in the first metal layer. Moreover, the first power line 20 and the second power line 30 are not limited to be arranged in the same layer and are not limited to extend in the same direction, for example, one of the first power line 20 and the second power line 30 is arranged in the first metal layer and extends in the first direction X, and the other is arranged in the second metal layer and extends in the second direction Y.

[0058] Please refer to Figure 1 and Figure 2 The passivation layer 16 is arranged on the source electrode 73, the drain electrode 74 and the interlayer insulating layer 15, and a via hole is arranged in the passivation layer 16 at a position corresponding to the drain electrode 74 of the second transistor T2 and part of the second power line 30. The first electrode 41 and the second electrode 42 are arranged in the via hole of the passivation layer 16, wherein the first electrode 41 is electrically connected to the drain electrode 74 of the second transistor T2, and the second electrode 42 is electrically connected to the second power line 30.

[0059] In an embodiment, a display panel is also provided. Please refer to Figures 1 to 7 , Figure 7 A cross-sectional structure diagram of the display panel provided in an embodiment of the present application is shown. The display panel 1000 includes the driving back plate 100 of any one of the foregoing embodiments. Optionally, the display panel 1000 further includes a light emitting device 200, which is bonded to the driving back plate 100. The light emitting device 200 includes an LED chip or the like.

[0060] Based on the same inventive concept, the present application also provides an electronic device. Please refer to Figure 7 and Figure 8 , Figure 8 A cross-sectional structure diagram of the electronic device provided in an embodiment of the present application is shown. The electronic device 1 includes a housing 2000 and the display panel 1000 of the foregoing embodiment. The housing 2000 is formed with a receiving cavity 2001, and the display panel 1000 is assembled in the receiving cavity 2001. The electronic device 1 includes a mobile phone, an electronic book, an electronic newspaper, a television or a personal portable computer, and can also be a flexible OLED display or lighting device that is bendable and foldable. The specific form of the electronic device is not limited in the embodiments of the present application.

[0061] According to the above embodiments, it can be known that:

[0062] The application provides a driving backboard, a display panel and an electronic device, the driving backboard comprising a substrate, a first power supply line and a first auxiliary power supply line arranged on opposite sides of the substrate, the first power supply line extending along a first direction and being electrically connected with the first auxiliary power supply line, and the orthographic projection of the first power supply line on the substrate coincides with the orthographic projection of the first auxiliary power supply line on the substrate, so that the impedance of the first power supply line can be reduced, and the first power supply line with a smaller line width can be arranged on the premise of ensuring that the voltage drop of the first power supply line is not increased, so that the transparency of the transparent display is improved, and the problem that the transparency of the existing transparent display is restricted is solved.

[0063] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0064] The above describes the embodiments of the application in detail, and the principle and implementation mode of the application are described by applying specific examples; the above embodiment is only used to help understand the technical scheme and core idea of the application; those skilled in the art should understand that the technical scheme recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and the modification or replacement does not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A drive backplane, characterized by, The drive backplane comprises: a substrate; a first power line arranged on a first side of the substrate and extending in a first direction; a first auxiliary power line arranged on a second side of the substrate away from the first power line and electrically connected with the first power line; a light shielding layer on the first side of the substrate; a buffer layer on the light shielding layer and the substrate; a gate insulating layer on the buffer layer and arranged corresponding to the light shielding layer; a first metal layer on the gate insulating layer, comprising a gate arranged corresponding to the gate insulating layer, and a first plate connected with the gate; an interlayer insulating layer on the first metal layer and the buffer layer; and a second metal layer on the interlayer insulating layer, comprising a second plate at least partially overlapping with the first plate, and the second plate being electrically connected with the light shielding layer; wherein a projection of the first power line on the substrate coincides with a projection of the first auxiliary power line on the substrate, a line width of the first auxiliary power line is the same as a line width of the first power line, and a film layer thickness of the first power line is less than or equal to a film layer thickness of the first auxiliary power line; the drive backplane comprises a drive circuit, and the drive circuit comprises a capacitor, the capacitor comprising the first plate, the second plate and the light shielding layer. The first power line comprises a first conductive part and at least one second conductive part electrically connected with the first conductive part; the substrate is provided with a first opening at a position corresponding to the second conductive part, the first opening exposing part of the second conductive part, and the first auxiliary power line is electrically connected with the corresponding second conductive part through the first opening.

2. The drive backplane of claim 1, wherein, The width of the second conductive part is greater than the width of the first conductive part.

3. The drive backplane of claim 2, wherein, The width of the first power line is greater than or equal to 4 microns.

4. The drive backplane of claim 1, wherein, The drive backplane further comprises:

5. The drive backsheet of any one of claims 1 to 4, wherein, a second power line arranged on the first side of the substrate and insulated from the first power line; a second auxiliary power line arranged on the second side of the substrate away from the second power line and electrically connected with the second power line; wherein a projection of the second power line on the substrate coincides with a projection of the second auxiliary power line on the substrate. The drive backplane further comprises a plurality of pixel units arranged in an array on the first side of the substrate, each pixel unit comprising at least three sub-pixels, each sub-pixel comprising a first electrode and a second electrode, the first electrode and the second electrode being arranged in insulation, the first power line being electrically connected with the first electrode, and the second power line being electrically connected with the second electrode.

6. The drive backplane of claim 5, wherein, The sub-pixel comprises the drive circuit, the first power line being electrically connected with the first electrode through the drive circuit, and the drive circuit comprising a plurality of transistors and at least one capacitor; 7. The drive backplane of claim 6, wherein, ​ The driving backplane further comprises a first signal transfer line and a second signal transfer line arranged on the first side of the substrate, the first signal transfer line and the second signal transfer line both extend along a second direction and are insulated from each other, the first power line is electrically connected with the driving circuit of two of the three sub-pixels through the first signal transfer line, and the second power line is electrically connected with the second electrode of two of the three sub-pixels through the second signal transfer line.

8. A display panel, characterized by, A display panel comprising the driving backplane as claimed in any one of claims 1 to 7.

9. An electronic device, comprising: A display device comprising a housing formed with a receiving cavity and the display panel as claimed in claim 8, the display panel being assembled in the receiving cavity.

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