An error amplifier for a high-current dc-dc power supply module

Abstract

The application discloses an error amplifier for a large-current DCDC power module, which comprises a soft-starting circuit and an error amplifier main circuit. The soft-starting circuit is used for stabilizing the rising voltage during starting; and the error amplifier main circuit is used for comparing a feedback voltage VFB with a reference voltage VREF, and forming a far-from-origin secondary main pole with a compensation capacitor. The application is applied to the large-current DCDC power module, and in the technology, the transconductance of the error amplifier is increased, the output resistance is reduced, the pole position of the error amplifier output end is far from the origin position, the error amplifier output end is used as a secondary main pole of the power module system, and the system stability is ensured.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply technology, specifically to an error amplifier for a high-current DC-DC power supply module. Background Technology

[0002] With the expansion of electronic systems and the significant increase in computing power, especially in applications involving high-quality image acquisition, processing, and transmission, the power supplies for electronic systems require greater load capacity and faster transient response speeds. Modern electronic systems, such as ASICs, FPGAs, and processors in high-performance communication, server, and computing systems, need to use core power supplies capable of generating 1.0V (or lower) voltage directly from 12V or an intermediate bus, and require power supplies to provide load capacities of up to tens or even hundreds of amperes.

[0003] As is well known, current-mode DC-DC converters typically contain two poles and one zero, with the appropriate pole and zero positions set to ensure system stability. In high-current DC-DC power modules, to ensure output voltage stability and transient response requirements, the output capacitor needs to be configured to be several hundred or even several thousand microfarads, making the output pole close to the origin. This means that the pole can only serve as the dominant pole of the high-current DC-DC power module system. Therefore, the pole at the output of the error amplifier in the system must be designated as the secondary dominant pole to better ensure system stability and improve transient response performance.

[0004] However, in the existing technology, the poles at the output of the error amplifier cannot be used as secondary dominant poles, which cannot meet the application requirements. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides an error amplifier for a high-current DC-DC power supply module, thereby solving the aforementioned problems.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An error amplifier for a high-current DC-DC power supply module includes a soft-start circuit and an error amplifier main circuit.

[0008] The soft-start circuit is used to stabilize the rising voltage during startup;

[0009] The error amplifier main circuit is used to compare the feedback voltage VFB with the reference voltage VREF, forming a secondary dominant pole far from the origin with the compensation capacitor.

[0010] Preferably, the soft-start circuit includes a first P-type MOSFET MP1, a second P-type MOSFET MP2, a third P-type MOSFET MP3, a fourth P-type MOSFET MP4, a first N-type MOSFET MN1, a second N-type MOSFET MN2, a third N-type MOSFET MN3, a resistor R, and a capacitor C;

[0011] The source of the first P-type MOSFET MP1 and the source of the second P-type MOSFET MP2 are connected to the internal power supply INTVCC.

[0012] The gate of the first P-type MOS transistor MP1, the drain of the first P-type MOS transistor MP1, and the gate of the second P-type MOS transistor MP2 are connected to the external bias current IBIAS1.

[0013] The drain of the second P-type MOS transistor MP2, the source of the third P-type MOS transistor MP3, and the source of the fourth P-type MOS transistor MP4 are connected.

[0014] The gate of the third P-type MOS transistor MP3 and the drain of the third N-type MOS transistor MN3 are connected to the external reference voltage VREF.

[0015] The drain of the third P-type MOS transistor MP3 is connected to the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1, and the gate of the second N-type MOS transistor MN2.

[0016] The gate of the fourth P-type MOS transistor MP4 is connected to the external soft-start voltage VSS. The drain of the fourth P-type MOS transistor MP4 is connected to the drain of the second N-type MOS transistor MN2, the gate of the third N-type MOS transistor MN3, and one end of the capacitor C. The other end of the capacitor C is connected to one end of the resistor R. The source of the first N-type MOS transistor MN1, the source of the second N-type MOS transistor MN2, the source of the third N-type MOS transistor MN3, and the other end of the resistor R are connected to ground GND.

[0017] Furthermore, the soft-start voltage VSS is a ramp voltage formed by charging the capacitor with current.

[0018] Furthermore, when the soft-start voltage VSS is lower than the reference voltage VREF, the reference voltage VREF is pulled down. The reference voltage VREF increases with the soft-start voltage VSS until the soft-start voltage VSS is higher than the reference voltage VREF. At this point, the soft-start circuit loses its function, and the reference voltage VREF is fixed at the set value.

[0019] Preferably, the error amplifier main circuit includes the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, the ninth P-type MOSFET MP9, the tenth P-type MOSFET MP10, the eleventh P-type MOSFET MP11, the twelfth P-type MOSFET MP12, the thirteenth P-type MOSFET MP13, the fourteenth P-type MOSFET MP14, the fifteenth P-type MOSFET MP15, the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, the tenth N-type MOSFET MN10, the eleventh N-type MOSFET MN11, the twelfth N-type MOSFET MN12, the thirteenth N-type MOSFET MN13, and the fourteenth N-type MOSFET MN14.

[0020] The source of the fifth P-type MOSFET MP5, the source of the sixth P-type MOSFET MP6, the source of the eighth P-type MOSFET MP8, the source of the twelfth P-type MOSFET MP12, and the source of the fourteenth P-type MOSFET MP14 are connected to the internal power supply INTVCC.

[0021] The gate of the fifth P-type MOS transistor MP5, the drain of the fifth P-type MOS transistor MP5, the gate of the seventh P-type MOS transistor MP7, the gate of the ninth P-type MOS transistor MP9, the gate of the thirteenth P-type MOS transistor MP13, and the gate of the fifteenth P-type MOS transistor MP15 are connected to the drain of the fifth N-type MOS transistor MN5.

[0022] The gate of the sixth P-type MOS transistor MP6, the gate of the eighth P-type MOS transistor MP8, and the drain of the seventh P-type MOS transistor MP7 are connected to the drain of the sixth N-type MOS transistor MN6.

[0023] The drain of the sixth P-type MOSFET MP6 is connected to the source of the seventh P-type MOSFET MP7, the drain of the eighth P-type MOSFET MP8 is connected to the source of the ninth P-type MOSFET MP9, the drain of the ninth P-type MOSFET MP9 and the source of the tenth P-type MOSFET MP10 are connected to the source of the eleventh P-type MOSFET MP11, and the gate of the tenth P-type MOSFET MP10 is connected to the external feedback voltage VFB.

[0024] The drain of the tenth P-type MOS transistor MP10 is connected to the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12.

[0025] The gate of the eleventh P-type MOSFET MP11 is connected to the external reference voltage VREF. The drain of the eleventh P-type MOSFET MP11 is connected to the drain of the ninth N-type MOSFET MN9, the gate of the tenth N-type MOSFET MN10, and the gate of the fourteenth N-type MOSFET MN14. The gates of the twelfth P-type MOSFET MP12, the fourteenth P-type MOSFET MP14, and the drain of the thirteenth P-type MOSFET MP13 are connected to the drain of the eleventh N-type MOSFET MN11.

[0026] The drain of the twelfth P-type MOSFET MP12 is connected to the source of the thirteenth P-type MOSFET MP13, the drain of the fourteenth P-type MOSFET MP14 is connected to the source of the fifteenth P-type MOSFET MP15, and the drains of the fifteenth P-type MOSFET MP15 and the thirteenth N-type MOSFET MN13 are connected to the external output port VC.

[0027] The drain of the fourth N-type MOS transistor MN4, the gate of the fourth N-type MOS transistor MN4, the gate of the fifth N-type MOS transistor MN5, and the gate of the sixth N-type MOS transistor MN6 are connected to the external bias current IBIAS2.

[0028] The gates of the seventh N-type MOS transistor MN7, the ninth N-type MOS transistor MN9, the eleventh N-type MOS transistor MN11, and the thirteenth N-type MOS transistor MN13 are connected to the external bias voltage VBIAS.

[0029] The source of the seventh N-type MOSFET MN7 is connected to the drain of the eighth N-type MOSFET MN8; the source of the ninth N-type MOSFET MN9 is connected to the drain of the tenth N-type MOSFET MN10; the source of the eleventh N-type MOSFET MN11 is connected to the drain of the twelfth N-type MOSFET MN12; the source of the thirteenth N-type MOSFET MN13 is connected to the drain of the fourteenth N-type MOSFET MN14; and the sources of the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the eighth N-type MOSFET MN8, the tenth N-type MOSFET MN10, the twelfth N-type MOSFET MN12, and the fourteenth N-type MOSFET MN14 are connected to ground (GND).

[0030] Furthermore, the ratio of the layout area of ​​the seventh N-type MOS transistor MN7, the eighth N-type MOS transistor MN8, the ninth N-type MOS transistor MN9, and the tenth N-type MOS transistor MN10 is 1:1.

[0031] Furthermore, the ratio of the layout area of ​​the twelfth P-type MOSFET MP12, the thirteenth P-type MOSFET MP13, the fourteenth P-type MOSFET MP14, and the fifteenth P-type MOSFET MP15 is 1:N, where N is a positive integer greater than 1.

[0032] Furthermore, the ratio of the layout area of ​​the eleventh N-type MOS transistor MN11, the twelfth N-type MOS transistor MN12, the thirteenth N-type MOS transistor MN13, and the fourteenth N-type MOS transistor MN14 is 1:N, where N is a positive integer greater than 1.

[0033] Compared with the prior art, the present invention has the following beneficial technical effects:

[0034] This invention provides an error amplifier for high-current DC-DC power modules. By setting up a soft-start circuit and an error amplifier main circuit, the soft-start circuit stabilizes the rising voltage during startup. The error amplifier main circuit compares the feedback voltage VFB with the reference voltage VREF, and adjusts the feedback voltage VFB according to the change in the error amplifier's output voltage VC, making it approach VREF. This forms a secondary dominant pole away from the origin with the compensation capacitor, ensuring system stability. When applied to high-current DC-DC power modules, this error amplifier increases the transconductance and decreases the output resistance, causing the pole at the error amplifier's output to be located away from the origin, serving as a secondary dominant pole for the power module system and ensuring system stability. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of an error amplifier for a high-current DC-DC power supply module according to the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0037] Example

[0038] This invention provides a high transconductance error amplifier for use in high-current DC-DC power modules. Technically, by increasing the transconductance of the error amplifier and reducing the output resistance, the pole position of the output terminal of the error amplifier is moved away from the origin position, serving as the secondary dominant pole of the power module system, thus ensuring system stability.

[0039] The specific implementation of the large transconductance error amplifier in this embodiment Figure 1 As shown, the circuit consists of two parts: the first part is a soft-start circuit, and the second part is the main circuit of the error amplifier.

[0040] In the soft-start circuit, the soft-start port voltage VSS is a ramp voltage formed by charging the capacitor with current. When the soft-start voltage VSS is lower than the reference voltage VREF, the reference voltage VREF is pulled down. The reference voltage VREF increases with the soft-start voltage VSS until the soft-start voltage VSS is higher than the reference voltage VREF. At this point, the soft-start circuit loses its function, and the reference voltage VREF is fixed at the set value.

[0041] The main circuit of the error amplifier compares the feedback voltage VFB with the reference voltage VREF. When the feedback voltage VFB is lower than the reference voltage VREF, the output voltage VC of the error amplifier is pulled high; when the feedback voltage VFB is higher than the reference voltage VREF, the output voltage VC of the error amplifier is pulled low. Subsequent circuits adjust the feedback voltage VFB based on the change in the output voltage VC of the error amplifier, bringing it closer to VREF. The MP14 and MN14 terminals in the output stage of this error amplifier have a large width-to-length ratio to achieve high transconductance characteristics, forming a secondary dominant pole far from the origin with the compensation capacitor, ensuring system stability.

[0042] The soft-start circuit includes a first P-type MOSFET MP1, a second P-type MOSFET MP2, a third P-type MOSFET MP3, a fourth P-type MOSFET MP4, a first N-type MOSFET MN1, a second N-type MOSFET MN2, a third N-type MOSFET MN3, a resistor R, and a capacitor C.

[0043] The specific connections are as follows: the source of the first P-type MOSFET MP1 and the source of the second P-type MOSFET MP2 are connected to the internal power supply INTVCC; the gate of the first P-type MOSFET MP1, the drain of the first P-type MOSFET MP1, and the gate of the second P-type MOSFET MP2 are connected to the external bias current IBIAS1; the drain of the second P-type MOSFET MP2 and the source of the third P-type MOSFET MP3 are connected to the source of the fourth P-type MOSFET MP4; the gate of the third P-type MOSFET MP3 and the drain of the third N-type MOSFET MN3 are connected to the external reference voltage VREF; the third P-type MOSFET MP... The drain of transistor 3 is connected to the drain of the first N-type MOSFET MN1, the gate of the first N-type MOSFET MN1, and the gate of the second N-type MOSFET MN2. The gate of the fourth P-type MOSFET MP4 is connected to the external soft-start voltage VSS. The drain of the fourth P-type MOSFET MP4 is connected to the drain of the second N-type MOSFET MN2, the gate of the third N-type MOSFET MN3, and one end of capacitor C. The other end of capacitor C is connected to one end of resistor R. The source of the first N-type MOSFET MN1, the source of the second N-type MOSFET MN2, the source of the third N-type MOSFET MN3, and the other end of resistor R are connected to ground GND.

[0044] The main circuit of the error amplifier includes the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, the ninth P-type MOSFET MP9, the tenth P-type MOSFET MP10, the eleventh P-type MOSFET MP11, the twelfth P-type MOSFET MP12, the thirteenth P-type MOSFET MP13, the fourteenth P-type MOSFET MP14, the fifteenth P-type MOSFET MP15, the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, the tenth N-type MOSFET MN10, the eleventh N-type MOSFET MN11, the twelfth N-type MOSFET MN12, the thirteenth N-type MOSFET MN13, and the fourteenth N-type MOSFET MN14.

[0045] The specific connections are as follows: The source of the fifth P-type MOSFET MP5, the source of the sixth P-type MOSFET MP6, the source of the eighth P-type MOSFET MP8, the source of the twelfth P-type MOSFET MP12, and the source of the fourteenth P-type MOSFET MP14 are connected to the internal power supply INTVCC. The gate and drain of the fifth P-type MOSFET MP5, the gate of the seventh P-type MOSFET MP7, the gate of the ninth P-type MOSFET MP9, the gate of the thirteenth P-type MOSFET MP13, and the gate of the fifteenth P-type MOSFET MP15 are connected to the drain of the fifth N-type MOSFET MN5. The gates of the sixth P-type MOSFET MP6, the eighth P-type MOSFET MP8, and the seventh P-type MOSFET MP14 are connected to the drain of the fifth N-type MOSFET MN5. The drain of the P-type MOSFET MP7 is connected to the drain of the sixth N-type MOSFET MN6; the drain of the sixth P-type MOSFET MP6 is connected to the source of the seventh P-type MOSFET MP7; the drain of the eighth P-type MOSFET MP8 is connected to the source of the ninth P-type MOSFET MP9; the drain of the ninth P-type MOSFET MP9 and the source of the tenth P-type MOSFET MP10 are connected to the source of the eleventh P-type MOSFET MP11; the gate of the tenth P-type MOSFET MP10 is connected to the external feedback voltage VFB; the drain of the tenth P-type MOSFET MP10 is connected to the drain of the seventh N-type MOSFET MN7, the gate of the eighth N-type MOSFET MN8, and the gate of the twelfth N-type MOSFET MN12; the eleventh P-type MOSFET MP7... The gate of P11 is connected to the external reference voltage VREF. The drain of the eleventh P-type MOSFET MP11 is connected to the drain of the ninth N-type MOSFET MN9, the gate of the tenth N-type MOSFET MN10, and the gate of the fourteenth N-type MOSFET MN14. The gate of the twelfth P-type MOSFET MP12, the gate of the fourteenth P-type MOSFET MP14, and the drain of the thirteenth P-type MOSFET MP13 are connected to the drain of the eleventh N-type MOSFET MN11. The drain of the twelfth P-type MOSFET MP12 is connected to the source of the thirteenth P-type MOSFET MP13. The drain of the fourteenth P-type MOSFET MP14 is connected to the source of the fifteenth P-type MOSFET MP15. The drain of the fifteenth P-type MOSFET MP15... The drain of the thirteenth N-type MOSFET MN13 is connected to the external output port VC. The drain and gate of the fourth N-type MOSFET MN4, the gate of the fifth N-type MOSFET MN5, and the gate of the sixth N-type MOSFET MN6 are connected to the external bias current IBIAS2. The gates of the seventh N-type MOSFET MN7, the ninth N-type MOSFET MN9, the eleventh N-type MOSFET MN11, and the thirteenth N-type MOSFET MN13 are connected to the external bias voltage VBIAS. The source of the seventh N-type MOSFET MN7 is connected to the drain of the eighth N-type MOSFET MN8, and the source of the ninth N-type MOSFET MN9 is connected to the drain of the tenth N-type MOSFET MN10.The source of the eleventh N-type MOSFET MN11 is connected to the drain of the twelfth N-type MOSFET MN12. The source of the thirteenth N-type MOSFET MN13 is connected to the drain of the fourteenth N-type MOSFET MN14. The sources of the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the eighth N-type MOSFET MN8, the tenth N-type MOSFET MN10, the twelfth N-type MOSFET MN12, and the fourteenth N-type MOSFET MN14 are connected to ground (GND).

[0046] To achieve high transconductance characteristics, the ratio of the layout area between the seventh N-type MOSFET MN7, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, and the tenth N-type MOSFET MN10 is set to 1:1.

[0047] The layout area ratio between the twelfth P-type MOSFET MP12, the thirteenth P-type MOSFET MP13, the fourteenth P-type MOSFET MP14, and the fifteenth P-type MOSFET MP15 is set to 1:N, where N is a positive integer greater than 1.

[0048] The ratio of the layout area between the eleventh N-type MOSFET MN11, the twelfth N-type MOSFET MN12, the thirteenth N-type MOSFET MN13, and the fourteenth N-type MOSFET MN14 is set to 1:N, where N is a positive integer greater than 1.

Claims

1. An error amplifier for a high-current DC-DC power supply module, characterized by The soft start circuit and the error amplifier main circuit are included; The soft start circuit is used for stabilizing the rising voltage during starting; The error amplifier main circuit is used for comparing the feedback voltage VFB with the reference voltage VREF, and forming a far-from-origin secondary main pole with the compensation capacitor; The soft start circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a resistor R and a capacitor C; The source of the first P-type MOS transistor MP1 and the source of the second P-type MOS transistor MP2 are connected with an internal power supply INTVCC; The gate of the first P-type MOS transistor MP1, the drain of the first P-type MOS transistor MP1 and the gate of the second P-type MOS transistor MP2 are connected with an external bias current IBIAS1; The drain of the second P-type MOS transistor MP2, the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP4 are connected; The gate of the third P-type MOS transistor MP3 and the drain of the third N-type MOS transistor MN3 are connected with an external reference voltage VREF; The drain of the third P-type MOS transistor MP3, the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN2 are connected; The gate of the fourth P-type MOS transistor MP4 is connected with an external soft start voltage VSS, the drain of the fourth P-type MOS transistor MP4, the drain of the second N-type MOS transistor MN2, the gate of the third N-type MOS transistor MN3 and one end of the capacitor C are connected, the other end of the capacitor C is connected with one end of the resistor R, the source of the first N-type MOS transistor MN1, the source of the second N-type MOS transistor MN2, the source of the third N-type MOS transistor MN3 and the other end of the resistor R are connected with a ground terminal GND; The error amplifier main circuit includes a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, an eleventh P-type MOS transistor MP11, a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a fifteenth P-type MOS transistor MP15, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13 and a fourteenth N-type MOS transistor MN14. The source of the fifth P-type MOS transistor MP5, the source of the sixth P-type MOS transistor MP6, the source of the eighth P-type MOS transistor MP8, the source of the twelfth P-type MOS transistor MP12, and the source of the fourteenth P-type MOS transistor MP14 are connected with an internal power supply INTVCC; The gate of the fifth P-type MOS transistor MP5, the drain of the fifth P-type MOS transistor MP5, the gate of the seventh P-type MOS transistor MP7, the gate of the ninth P-type MOS transistor MP9, the gate of the thirteenth P-type MOS transistor MP13, the gate of the fifteenth P-type MOS transistor MP15, and the drain of the fifth N-type MOS transistor MN5 are connected; The gate of the sixth P-type MOS transistor MP6, the gate of the eighth P-type MOS transistor MP8, the drain of the seventh P-type MOS transistor MP7, and the drain of the sixth N-type MOS transistor MN6 are connected; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The gate of the eleventh P-type MOS transistor MP11 is connected with an external reference voltage VREF, the drain of the eleventh P-type MOS transistor MP11 is connected with the drain of the ninth N-type MOS transistor MN9, the gate of the tenth N-type MOS transistor MN10, and the gate of the fourteenth N-type MOS transistor MN14, the gate of the twelfth P-type MOS transistor MP12, the gate of the fourteenth P-type MOS transistor MP14, and the drain of the thirteenth P-type MOS transistor MP13 are connected with the drain of the eleventh N-type MOS transistor MN11; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and the gate of the twelfth N-type MOS transistor MN12; The drain of the tenth P-type MOS transistor MP10 is connected with the drain of the seventh N-type MOS transistor MN7, the gate of the eighth N-type MOS transistor MN8, and The gate of the seventh N-type MOS transistor MN7, the gate of the ninth N-type MOS transistor MN9, the gate of the eleventh N-type MOS transistor MN11, and the gate of the thirteenth N-type MOS transistor MN13 are connected with an external bias voltage VBIAS. The source of the seventh N-type MOS transistor MN7 is connected with the drain of the eighth N-type MOS transistor MN8, the source of the ninth N-type MOS transistor MN9 is connected with the drain of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11 is connected with the drain of the twelfth N-type MOS transistor MN12, the source of the thirteenth N-type MOS transistor MN13 is connected with the drain of the fourteenth N-type MOS transistor MN14, and the source of the fourth N-type MOS transistor MN4, the source of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6, the source of the eighth N-type MOS transistor MN8, the source of the tenth N-type MOS transistor MN10, the source of the twelfth N-type MOS transistor MN12, and the source of the fourteenth N-type MOS transistor MN14 are connected with a ground terminal GND.

2. An error amplifier for a high-current DC-DC power supply module according to claim 1, characterized in that The soft start voltage VSS is a ramp voltage formed by charging a capacitor with a current.

3. An error amplifier for a high-current DC-DC power supply module according to claim 1, characterized in that, When the soft start voltage VSS is lower than the reference voltage VREF, the reference voltage VREF is pulled low, the reference voltage VREF follows the increase of the soft start voltage VSS, and when the soft start voltage VSS is higher than the reference voltage VREF, the soft start circuit loses effect, and the reference voltage VREF is fixed at a set value.

4. An error amplifier for a high-current DC-DC power supply module according to claim 1, characterized in that, The ratio of the layout area between the seventh N-type MOS transistor MN7, the eighth N-type MOS transistor MN8, and the ninth N-type MOS transistor MN9 and the tenth N-type MOS transistor MN10 is 1:

1.

5. An error amplifier for a high-current DC-DC power supply module according to claim 1, characterized in that, The ratio of the layout area between the twelfth P-type MOS transistor MP12, the thirteenth P-type MOS transistor MP13, and the fourteenth P-type MOS transistor MP14 and the fifteenth P-type MOS transistor MP15 is 1:N, N is a positive integer greater than 1.

6. An error amplifier for a high-current DC-DC power supply module according to claim 1, characterized in that, The ratio of the layout area between the eleventh N-type MOS transistor MN11, the twelfth N-type MOS transistor MN12, and the thirteenth N-type MOS transistor MN13 and the fourteenth N-type MOS transistor MN14 is 1:N, N is a positive integer greater than 1.

Images