Negative pressure pulse control signal generation circuit and method
By combining logic shaping and delay modules with charge pump capacitors, the leakage problem in existing analog circuit designs is solved, enabling effective analog-to-digital converter (ADC) operation under X-ray and gamma-ray environments. This also solves the problem of analog switch shutdown, achieving effective and reliable shutdown of the ADC and thus enhancing its overall efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING GIGACHIP TECH CO LTD
- Filing Date
- 2022-05-27
- Publication Date
- 2026-07-21
AI Technical Summary
In X-ray and gamma-ray environments, the threshold of NMOS transistors drops, causing the analog input signal to fail to turn off, resulting in leakage problems. Existing solutions increase design complexity and cost, and limit device performance.
By employing a combination of logic shaping and delay modules, charge pump capacitors, and charge/discharge control modules, a negative voltage pulse signal is generated through the charge/discharge process of the control signal to ensure reliable turn-off of the MOSFET in complex environments.
It achieves reliable shutdown of the analog switch under X-ray and gamma-ray environment, avoids conversion errors of analog-to-digital converter, reduces design difficulty and production cost, and improves the reliability of charge-type analog-to-digital converter.
Smart Images
Figure CN114844488B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a negative pressure pulse control signal generation circuit and method. Background Technology
[0002] In monolithic integrated circuit design of analog-to-digital converters (ADCs), rail-to-rail analog input signals are sampled, held, and transmitted using switching MOSFETs, with the control signal being a power-to-ground pulse signal controlling the logic transmission. However, after prolonged operation in X-ray or gamma-ray environments, the threshold voltage of NMOS transistors decreases, causing analog input signals near the lower rail to fail to turn off, resulting in significant leakage and abnormal conversion of the analog input signals near the lower rail. Current common solutions include introducing a negative power supply or using a special substrate-isolated CMOS process to generate negative voltage pulses. Introducing a negative power supply increases the overall design complexity and cost. While the special substrate-isolated CMOS process maintains the device's peripheral functions, it increases fabrication complexity, limits the performance of other components, and requires multiple pulse signals for coordination. These factors increase manufacturing costs and limit the realization of other device performance characteristics.
[0003] Therefore, there is an urgent need for a simple and efficient technology for generating negative pressure pulse signals. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a negative pressure pulse signal generation scheme, which further reduces the gate voltage of the MOSFET through the control signal of the negative pressure pulse, so as to ensure the reliable turn-off of the MOSFET switch in X-ray and gamma-ray environments.
[0005] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.
[0006] A negative pressure pulse control signal generation circuit includes:
[0007] The logic shaping and delay module receives a pulse signal, performs logic shaping and delay processing on the pulse signal, and obtains and outputs a first signal, a second signal, and a third signal.
[0008] A charge pump capacitor, one end of which is connected to the first signal and the other end of which is connected to the load, outputs a control signal to the load;
[0009] The charge-discharge control module is connected to one end of the charge pump capacitor that outputs the control signal, and performs charge-discharge processing on the charge pump capacitor under the control of the second signal and the third signal;
[0010] Under the control of the second signal and the third signal, the power supply voltage and the high level of the first signal are first introduced to charge the charge pump capacitor, and then the ground potential is introduced to discharge the charge pump capacitor, pulling the control signal low. After a certain delay, the first signal changes from high level to low level, the charge pump capacitor is activated, and the control signal changes accordingly, pulling the control signal low to a negative voltage.
[0011] Optionally, the logic shaping and delay module includes a first logic shaping unit, a second logic shaping unit, and a delay unit. The delay unit is connected between the first logic shaping unit and the second logic shaping unit. The first logic shaping unit performs logic shaping processing on the pulse signal to obtain and output the second signal, the third signal, and the fourth signal. The delay unit performs delay processing on the fourth signal to obtain and output the fifth signal. The second logic shaping unit performs logic shaping processing on the fifth signal to obtain and output the first signal.
[0012] Optionally, the first logic shaping unit includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the pulse signal. The first inverter, the second inverter, and the third inverter are connected in series. The output terminal of the first inverter outputs the second signal, the output terminal of the second inverter outputs the third signal, and the output terminal of the third inverter outputs the fourth signal.
[0013] Optionally, the delay unit includes a first resistor and a first capacitor. One end of the first resistor is connected to the output terminal of the third inverter, and the other end of the first resistor is connected to one end of the first capacitor. The other end of the first capacitor is grounded, and the first capacitor is connected to one end of the first resistor to output the fifth signal.
[0014] Optionally, the second logic shaping unit includes a fourth inverter, a fifth inverter, and a sixth inverter. The input terminal of the fourth inverter is connected to one end of the first capacitor connected to the first resistor. The fourth inverter, the fifth inverter, and the sixth inverter are connected in series. The output terminal of the sixth inverter outputs the first signal.
[0015] Optionally, the first signal is the in-phase delayed signal of the pulse signal, the second signal is the out-of-phase signal of the pulse signal, and the third signal is the in-phase signal of the pulse signal.
[0016] Optionally, the charge / discharge control module includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the gate of the first PMOS transistor is connected to the second signal, the drain of the first PMOS transistor is connected to one end of the charge pump capacitor that outputs the control signal, the source of the second PMOS transistor is connected to one end of the charge pump capacitor that outputs the control signal, the gate of the second PMOS transistor is connected to the third signal, and the drain of the second PMOS transistor is grounded.
[0017] A method for generating a negative pressure pulse control signal includes:
[0018] A charge pump capacitor is provided, with a first signal connected to one end and a load connected to the other end, so as to output a control signal to the load;
[0019] During the first half-cycle of the first signal, the first signal changes from low level to high level, introduces a power supply voltage to one end of the charge pump capacitor that outputs the control signal, charges the charge pump capacitor, and pulls the control signal high to the power supply voltage.
[0020] During the second half-cycle of the first signal, the first signal changes from high level to low level, introducing ground potential to one end of the charge pump capacitor that outputs the control signal, discharging the charge pump capacitor and pulling the control signal low;
[0021] During the second half-cycle of the first signal, when the first signal changes from high level to low level, the charge pump capacitor is activated, causing the control signal to change accordingly and pull the control signal down to a negative voltage.
[0022] As described above, the negative pressure pulse control signal generation circuit and method provided by the present invention have at least the following beneficial effects:
[0023] The entire negative voltage pulse control signal generation circuit is based on a structure design of "logic shaping and delay module + charge pump capacitor + charge / discharge control module". First, the power supply voltage and the high level of the first signal are introduced to charge the charge pump capacitor and pull the control signal high to the power supply voltage. Then, the ground potential is introduced to discharge the charge pump capacitor and pull the control signal low. After a certain delay, when the first signal jumps from high level to low level, the charge pump capacitor is activated, causing the control signal to jump accordingly and pull the control signal low to a negative voltage. This results in a negative voltage pulse in the control signal, which can effectively solve the leakage problem of various analog switches in existing analog-to-digital converter designs when X-ray, gamma-ray environments or when the input signal has a negative overshoot. It avoids conversion errors of charge-type analog-to-digital converters in complex radiation and electromagnetic environments. Moreover, the overall circuit structure is simple and can be implemented based on conventional CMOS technology without the need for special processes such as dielectric isolation or substrate floating. This reduces design difficulty and manufacturing costs while effectively improving the reliability of charge-type analog-to-digital converters. Attached Figure Description
[0024] Figure 1 The diagram shown is a structural block diagram of the negative pressure pulse control signal generation circuit in this invention.
[0025] Figure 2 The diagram shown is a circuit diagram of a negative pressure pulse control signal generation circuit according to an embodiment of the present invention.
[0026] Figure 3 show Figure 2 Timing state diagram of multiple signals.
[0027] Figure 4 The diagram shows the steps of the negative pressure pulse control signal generation method in this invention. Detailed Implementation
[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] Please see Figures 1 to 4It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.
[0030] First, such as Figure 1 As shown, the present invention provides a negative pressure pulse control signal generation circuit, which includes:
[0031] The logic shaping and delay module receives the pulse signal Clk0, performs logic shaping and delay processing on the pulse signal Clk0, and obtains and outputs the first signal Clk1, the second signal Clk2 and the third signal Clk3.
[0032] The charge pump capacitor C0 has one end connected to the first signal Clk1 and the other end connected to the load, outputting a control signal Vout to the load.
[0033] The charge / discharge control module is connected to one end of the output control signal Vout of the charge pump capacitor C0. Under the control of the second signal Clk2 and the third signal Clk3, it performs charge / discharge processing on the charge pump capacitor C0.
[0034] Under the control of the second signal Clk2 and the third signal Clk3, the power supply voltage VDD (not shown in the figure) and the high level of the first signal Clk1 are first introduced to charge the charge pump capacitor C0 and pull the control signal Vout high to the power supply voltage VDD. Then, the ground potential is introduced to discharge the charge pump capacitor C0 and pull the control signal Vout low. After a certain delay, the first signal Clk1 changes from high level to low level, the charge pump capacitor C0 is started, and the control signal Vout changes accordingly, pulling the control signal Vout low to a negative voltage.
[0035] In detail, such as Figure 2As shown, in an optional embodiment of the present invention, the logic shaping and delay module includes a first logic shaping unit, a second logic shaping unit, and a delay unit. The delay unit is connected between the first logic shaping unit and the second logic shaping unit. The first logic shaping unit performs logic shaping processing on the pulse signal Clk0 to obtain and output the second signal Clk2, the third signal Clk3, and the fourth signal Clk4. The delay unit performs delay processing on the fourth signal Clk4 to obtain and output the fifth signal Clk5. The second logic shaping unit performs logic shaping processing on the fifth signal Clk5 to obtain and output the first signal Clk1.
[0036] More in detail, such as Figure 2 As shown, the first logic shaping unit includes a first inverter T1, a second inverter T2, and a third inverter T3. The input terminal of the first inverter T1 is connected to the pulse signal Clk0. The first inverter T1, the second inverter T2, and the third inverter T3 are connected in series. The output terminal of the first inverter T1 outputs the second signal Clk2, the output terminal of the second inverter T2 outputs the third signal Clk3, and the output terminal of the third inverter T3 outputs the fourth signal Clk4.
[0037] More in detail, such as Figure 2 As shown, the delay unit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the output terminal of the third inverter T3, and the other end of the first resistor R1 is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is grounded, and the first capacitor C1 is connected to one end of the first resistor R1 to output the fifth signal Clk5.
[0038] More in detail, such as Figure 2 As shown, the second logic shaping unit includes a fourth inverter T4, a fifth inverter T5, and a sixth inverter T6. The input terminal of the fourth inverter T4 is connected to one end of the first capacitor C1 and the first resistor R1. The fourth inverter T4, the fifth inverter T5, and the sixth inverter T6 are connected in series. The output terminal of the sixth inverter T6 outputs the first signal Clk1.
[0039] It should be noted that, in an optional embodiment of the present invention, according to the overall design requirements of the analog-to-digital converter, a pulse width of 1 ns and 10% to 5% is designed as the delay time for the charge pump capacitor C0 to start. For the working requirements of X-ray and gamma-ray environments, an RC delay structure is selected for the delay unit, with a delay time constant of 10 ps to 50 ps. It is understood that the specific structure of the delay unit can have other forms, which are not limited here. The delay of the inverters in the first logic shaping unit and the second logic shaping unit can be ignored.
[0040] More in detail, such as Figures 2-3As shown, the first signal Clk1 is obtained by the pulse signal Clk0 after six inversions and one delay. That is, the first signal Clk1 is the in-phase delayed signal of the pulse signal Clk0, and the delay time of the signal is denoted as t0. The second signal Clk2 is obtained by the pulse signal Clk0 after one inversion. That is, the second signal Clk2 is the inverted signal of the pulse signal Clk0. The third signal Clk3 is obtained by the pulse signal Clk0 after two inversions. That is, the third signal Clk3 is the in-phase signal of the pulse signal Clk0.
[0041] In detail, such as Figure 2 As shown, in an optional embodiment of the present invention, the charge / discharge control module includes a first PMOS transistor P1 and a second PMOS transistor P2. The source of the first PMOS transistor P1 is connected to the power supply voltage VDD, the gate of the first PMOS transistor P1 is connected to the second signal Clk2, the drain of the first PMOS transistor P1 is connected to one end of the output control signal Vout of the charge pump capacitor C0, the source of the second PMOS transistor P2 is connected to one end of the output control signal Vout of the charge pump capacitor C0, the gate of the second PMOS transistor P2 is connected to the third signal Clk3, and the drain of the second PMOS transistor P2 is grounded.
[0042] More in detail, such as Figure 2 and Figure 3 As shown, the working principle of the negative pressure pulse control signal generation circuit is as follows:
[0043] 1) During the high level of pulse signal Clk0, such as Figure 3 In stage a shown, the first PMOS transistor P1 is turned on and the second PMOS transistor P2 is turned off. The power supply voltage VDD is introduced to one end of the control signal Vout output to the charge pump capacitor C0. During this period, the first signal Clk1 jumps from low level to high level. Through the combined action of the power supply voltage VDD and the first signal Clk1, the charge pump capacitor C0 is charged and the control signal Vout is pulled high to the power supply voltage VDD.
[0044] 2) During the low level period of pulse signal Clk0, such as Figure 3 In stage b shown, the first PMOS transistor P1 is turned off and the second PMOS transistor P2 is turned on, introducing ground potential to one end of the control signal Vout output to the charge pump capacitor C0. During this period, the first signal Clk1 changes from high level to low level. When the first signal Clk1 is still high level, the first signal Clk1, in conjunction with the ground potential, discharges the charge pump capacitor C0, pulling the control signal Vout low.
[0045] 3) During the low level period of pulse signal Clk0, such as Figure 3As shown in stage b, after a delay of time t0, the first signal Clk1 jumps from high level to low level following the pulse signal Clk0. At this time, the charge pump capacitor C0 is activated, causing the control signal Vout, which was already pulled down by a certain amount (such as to VDD / 2), to jump down, directly pulling the control signal Vout down to a negative voltage.
[0046] 4) Thus, within multiple cycles of the pulse signal Clk0, the corresponding control signal generated is a pulse signal of power supply voltage VDD - negative voltage. This control signal can provide both positive and negative voltages, so that the gate voltage of the NMOS transistor is lower than the ground potential when the control signal is used to turn off the NMOS transistor, ensuring reliable turn-off of the NMOS transistor in complex electromagnetic environments such as X-rays and γ-rays.
[0047] The capacitance value of the charge pump capacitor C0 is proportional to the magnitude of the control signal Vout and can be adjusted as needed, without limitation here. In order to ensure that the control signal Vout is pulled down to a negative voltage, the amplitude of the first signal Clk1 changing from high level to low level, the magnitude of the power supply voltage VDD, and the delay lag time t0 must satisfy a certain relationship, which will not be elaborated here.
[0048] Secondly, based on the design concept of the negative pressure pulse control signal generation circuit mentioned above, such as Figure 4 As shown, the present invention also provides a method for generating a negative pressure pulse control signal, which includes the following steps:
[0049] S1. Provide a charge pump capacitor, connect a first signal to one end of it, and connect a load to the other end of it to output a control signal to the load;
[0050] S2, during the first half-cycle of the first signal, i.e. Figure 3 In stage a shown, the first signal jumps from low level to high level, introduces power supply voltage to one end of the charge pump capacitor to output the control signal, charges the charge pump capacitor, and pulls the control signal high to the power supply voltage.
[0051] S3, during the second half-cycle of the first signal, i.e. Figure 3 In stage b shown, the first signal jumps from high level to low level, introduces ground potential to one end of the charge pump capacitor that outputs the control signal, discharges the charge pump capacitor, and pulls the control signal low.
[0052] S4, during the second half-cycle of the first signal, i.e. Figure 3 In stage b shown, when the first signal changes from high level to low level, the charge pump capacitor is activated, causing the control signal to change accordingly and pull the control signal down to a negative voltage.
[0053] In detail, in steps S2 to S4, through the process of "first charging to pull up to the power supply voltage, then discharging to pull down part of it, and then the charge pump switching to pull down to the negative voltage", a pulse control signal from the power supply voltage to the negative voltage can be generated. This control signal can provide both positive voltage (power supply voltage) and negative voltage, so that the gate voltage of the NMOS transistor when the control signal is used to turn off is lower than the ground potential, ensuring the reliable turn-off of the NMOS transistor switch in complex electromagnetic environments such as X-rays and γ-rays.
[0054] In summary, the negative voltage pulse control signal generation circuit and method provided by this invention first introduces a power supply voltage and a high level of a first signal to charge the charge pump capacitor and pulls the control signal high to the power supply voltage. Then, a ground potential is introduced to discharge the charge pump capacitor and pull the control signal low. After a certain delay, when the first signal jumps from a high level to a low level, the charge pump capacitor starts, causing the control signal to jump accordingly and pull the control signal low to a negative voltage. This results in a negative voltage pulse in the control signal, effectively solving the leakage problem of various analog switches in existing analog-to-digital converter designs when exposed to X-rays, gamma rays, or when the input signal has a negative overshoot. It also avoids conversion errors in charge-type analog-to-digital converters in complex radiation and electromagnetic environments. Furthermore, the overall circuit structure is simple and can be implemented using conventional CMOS technology without the need for special processes such as dielectric isolation or substrate floating. This reduces design difficulty and manufacturing costs while effectively improving the reliability of the charge-type analog-to-digital converter.
[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A negative pressure pulse control signal generation circuit, characterized in that, include: A logic shaping and delay module receives a pulse signal, performs logic shaping and delay processing on the pulse signal, and obtains and outputs a first signal, a second signal, and a third signal. The logic shaping and delay module includes a first logic shaping unit, a second logic shaping unit, and a delay unit. The delay unit is connected between the first logic shaping unit and the second logic shaping unit. The first logic shaping unit performs logic shaping on the pulse signal and obtains and outputs the second signal, the third signal, and a fourth signal. The delay unit delays the fourth signal and obtains and outputs a fifth signal. The second logic shaping unit performs logic shaping on the fifth signal and obtains and outputs the first signal. A charge pump capacitor, one end of which is connected to the first signal and the other end of which is connected to the load, outputs a control signal to the load; The charge-discharge control module is connected to one end of the charge pump capacitor that outputs the control signal, and performs charge-discharge processing on the charge pump capacitor under the control of the second signal and the third signal; Under the control of the second signal and the third signal, the power supply voltage and the high level of the first signal are first introduced to charge the charge pump capacitor, and then the ground potential is introduced to discharge the charge pump capacitor, pulling the control signal low. After a certain delay, the first signal changes from high level to low level, the charge pump capacitor is activated, and the control signal changes accordingly, pulling the control signal low to a negative voltage.
2. The negative pressure pulse control signal generation circuit according to claim 1, characterized in that, The first logic shaping unit includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the pulse signal. The first inverter, the second inverter, and the third inverter are connected in series. The output terminal of the first inverter outputs the second signal, the output terminal of the second inverter outputs the third signal, and the output terminal of the third inverter outputs the fourth signal.
3. The negative pressure pulse control signal generation circuit according to claim 2, characterized in that, The delay unit includes a first resistor and a first capacitor. One end of the first resistor is connected to the output terminal of the third inverter, and the other end of the first resistor is connected to one end of the first capacitor. The other end of the first capacitor is grounded, and the first capacitor is connected to one end of the first resistor to output the fifth signal.
4. The negative pressure pulse control signal generation circuit according to claim 3, characterized in that, The second logic shaping unit includes a fourth inverter, a fifth inverter, and a sixth inverter. The input terminal of the fourth inverter is connected to one end of the first capacitor connected to the first resistor. The fourth inverter, the fifth inverter, and the sixth inverter are connected in series. The output terminal of the sixth inverter outputs the first signal.
5. The negative pressure pulse control signal generating circuit according to claim 1 or 4, characterized in that, The first signal is the in-phase delayed signal of the pulse signal, the second signal is the out-of-phase signal of the pulse signal, and the third signal is the in-phase signal of the pulse signal.
6. The negative pressure pulse control signal generation circuit according to claim 1, characterized in that, The charge / discharge control module includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the gate of the first PMOS transistor is connected to the second signal, the drain of the first PMOS transistor is connected to one end of the charge pump capacitor that outputs the control signal, the source of the second PMOS transistor is connected to one end of the charge pump capacitor that outputs the control signal, the gate of the second PMOS transistor is connected to the third signal, and the drain of the second PMOS transistor is grounded.
7. A method for generating a negative pressure pulse control signal based on the negative pressure pulse control signal generation circuit according to any one of claims 1-6, characterized in that, include: A charge pump capacitor is provided, with a first signal connected to one end and a load connected to the other end, so as to output a control signal to the load; During the first half-cycle of the first signal, the first signal changes from low level to high level, introduces a power supply voltage to one end of the charge pump capacitor that outputs the control signal, charges the charge pump capacitor, and pulls the control signal high to the power supply voltage. During the second half-cycle of the first signal, the first signal changes from high level to low level, introducing ground potential to one end of the charge pump capacitor that outputs the control signal, discharging the charge pump capacitor and pulling the control signal low; During the second half-cycle of the first signal, when the first signal changes from high level to low level, the charge pump capacitor is activated, causing the control signal to change accordingly and pull the control signal down to a negative voltage.