Chain programmable delay elements

Abstract

Delay elements and multiplexers are present in programmable delay elements. Each programmable delay element has a chain of delay elements for producing successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer for selecting between an input clock and a delay element output in the chain of delay elements to produce an offset clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer for selecting between a clock comprising a first clock and a second clock from one of the delay elements of another programmable delay element to produce a clock of the programmable delay element.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 144,880, filed February 2, 2021, entitled “CHAINED PROGRAMMABLE DELAY ELEMENTS”, which is incorporated herein by reference. Technical Field

[0003] The technical field of this disclosure is broadly related to electronic circuits having delay elements and clock signals, and more narrowly related to field-programmable gate arrays (FPGAs) having delay elements and clock signals. Background Technology

[0004] Programmable delay elements (PDEs) are commonly used in modern field-programmable gate arrays (FPGAs) to delay clock signals by a configurable amount. PDEs can be used to satisfy set-up and hold constraints without shortening or lengthening paths. A PDE can be used to skew the clock forward on the launch clock of the data path, which improves the hold margin on that data path. Conversely, a PDE can be used to skew the clock forward on the capture clock of the data path, which improves the setup margin.

[0005] To achieve maximum flexibility, in some implementations, each flip-flop (FF) has its own programmable delay parameter (PDE), which has a wide range of programmable delay values. However, to achieve a minimum area, the PDE is amortized, causing multiple FFs to share a PDF, and the PDF may only have a few carefully selected programmable delay values. FPGA architects must weigh clock skew flexibility against silicon area. Summary of the Invention

[0006] This document describes embodiments of electronic circuit devices, FPGAs, a method for operating integrated circuits, a CAD system, a CAD tool, and a computer-readable medium having instructions.

[0007] One embodiment is an electronic circuit device. The device has delay elements and multiplexers in programmable delay elements (PDEs). Each PDE has a subset of delay elements and a subset of multiplexers. Each PDE has a chain of delay elements for generating successive delays in the clock of the PDE. Each PDE has a first multiplexer for selecting between an input clock and the outputs of delay elements in the chain of delay elements to generate an offset clock output for that PDE. Each PDE in at least the subset of PDEs has a second multiplexer. The second multiplexer is used to select between clocks to generate a clock for the chain of delay elements of that PDE. The clock selected by the second multiplexer includes a first clock as the input clock for each PDE in the PDE, and a second clock from one of the delay elements of another PDE in the PDE.

[0008] One embodiment is a method of operating an integrated circuit having multiplexers and delay elements to provide an offset clock. The method includes: generating successive delays of clocks in each of a plurality of programmable delay elements (PDEs) via a delay element chain. Each PDE has a subset of multiplexers and delay elements of the integrated circuit. The method includes: selecting between at least a first clock and a second clock via a second multiplexer to generate a clock for the delay element chain of the PDE in each PDE of at least the subset of PDEs. The second clock originates from one of the delay elements of another PDE. The method includes: selecting between an input clock and the output of a delay element in the delay element chain via a first multiplexer to generate an offset clock output for the PDE in each PDE.

[0009] One embodiment is a tangible, non-transitory computer-readable medium. Instructions are provided on the medium that, when executed by a processor, cause the processor to perform a method. The method includes: programming a field-programmable gate array (FPGA) to generate successive delays of clocks in each of a plurality of programmable delay elements (PDEs) via a chain of delay elements. Each PDE has a multiplexer of an integrated circuit and a subset of delay elements. The method includes: programming the FPGA to select between at least a first clock and a second clock in each PDE of at least the subset of PDEs via a second multiplexer, thereby generating a clock for the chain of delay elements of the PDE. The second clock originates from one of the delay elements of another PDE. The method includes: programming the FPGA to select between an input clock and the output of a delay element in the chain of delay elements via a first multiplexer, thereby generating an offset clock output of the PDE in each PDE. Attached Figure Description

[0010] The embodiments described herein will be more fully understood through the detailed description given below and the accompanying drawings of various embodiments of the invention. However, these embodiments should not be construed as limiting the invention to the specific embodiments, but are merely for explanation and understanding.

[0011] Figure 1 An implementation with four PDEs chanding is shown to provide four offset clocks with a unidirectional chain.

[0012] Figure 2 An implementation with four PDEs is shown to provide four offset clocks with a bidirectional chain.

[0013] Figure 3 An implementation with four PDEs is shown to provide four offset clocks with a cyclic bidirectional chain.

[0014] Depend on Figures 4A-4F Example delay elements that can be used in various embodiments of PDE are shown.

[0015] Figure 5 This illustration shows a hierarchical delay element chain that provides an offset clock to the hierarchical structure of the clock circuit in an embodiment of the PDE in an FPGA programmed using a CAD system with CAD tools.

[0016] Figure 6 This is a flowchart of an operation method for an electronic circuit device, which can be practiced using the embodiments described herein or the embodiments described herein. Detailed Implementation

[0017] In the following description, numerous details are set forth to provide a more thorough explanation of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without these specific details or with modifications thereof. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the invention.

[0018] The terms “multiplexer” and “mux” are used interchangeably herein for a circuit that selects from multiple inputs and drives an output based on that selection. In various embodiments, the output driver of the multiplexer or multiplexer-based circuit may be integrated with or distinguished from the multiplexer. The term “clock” herein is used for clock signals applied to a symbolic representation of electronic circuitry (e.g., circuit diagrams or CAD (computer-aided design) database), a single clock, clock pairs of clocks (e.g., commonly referred to as clock, clk, ck, c, etc.) and inverted clocks (e.g., commonly referred to as clockn, clkn, cn, nclock, clkbar, etc.), clock inputs, clock outputs, clock lines or clock signal lines, or the physical implementation of a clock in the physical implementation of an electronic circuit (e.g., integrated circuit (IC), FPGA, printed circuit board, device, etc.), as the context suggests.

[0019] In the embodiments described herein, a method is provided for linking programmable delay elements (PDEs) to generate multiple offset clocks that can share the cost of having multiple discrete offset values ​​and a higher maximum offset, and an apparatus having linked PDEs to generate multiple offset clocks.

[0020] The embodiments described herein include a novel linking scheme for PDEs that enables support for a greater number of latency values ​​and also achieves a higher maximum latency value. In one embodiment, each PDE can support M discrete latency values. In this case, a chain of N PDEs can support up to M*N latency values ​​and can drive up to N different clock lines. These clock lines share the linked PDEs, such that the area cost of linking N PDEs together is amortized.

[0021] Different linking strategies result in different clock flexibility. In one embodiment, when a clock lacks linking capability, a simple unidirectional chain (see...) Figure 1 This allows a clock to benefit to the fullest extent from link flexibility. Doubly linked (see...) Figure 2 This allows for greater link flexibility. A circular chain means that each generated clock has the same amount of link flexibility. (See Circular Chains) Figure 3 It can be unidirectional or bidirectional. Hierarchical chains (see...) Figure 5 It can also be used to obtain a higher maximum offset value.

[0022] Additionally, in one embodiment, M and N are modifiable. In such a case, M and N are modified to obtain different numbers of offset clocks and different numbers of discrete delay values.

[0023] Figure 1An embodiment with four PDEs 102, 104, 106, and 108 linked together via a unidirectional chain is shown. Each PDE has multiple delay elements and a multiplexer that selects between an input clock and various clock delays generated by the outputs of the delay elements to produce an offset clock as the output of that PDE. (Refer to...) Figure 1 As the output of PDE 102 generated by the leftmost multiplexer 112 (e.g., a 4:1 multiplexer), the offset clock on the left side of the diagram can have delay values ​​of 0ps, 50ps, 125ps, and 250ps relative to the input clock 110 labeled clk. These successive delay values ​​are generated by delay elements 120, 122, and 124 in a chain of consecutive delay elements in PDE 102. That is, multiplexer 112 can select from the zero-delay input clock 110, a first clock delay generated by the first delay element 120, a second clock delay generated by the second delay element 122, and a third clock delay generated by the third delay element 124. The 250ps output generated by the last delay element 124 in the chain of delay elements 120, 122, 124 drives the 2:1 multiplexer 126 in the next consecutive PDE 104 depicted on the right side of the figure, thereby providing more possible delay values ​​(0ps, 50ps, 125ps, 250ps, 300ps, 375ps, 500ps) for the second offset clock as the output of the multiplexer 114 of PDE 104.

[0024] The rightmost clock, which serves as the fourth offset clock for the output of PDE 108 from multiplexer 118 of PDE 108, can be offset by up to 1000 ps. This maximum possible delay value of the offset clock in the unidirectional delay element chain is selected when each of the output multiplexers 112, 114, 116, and 118 of all PDEs 102, 104, 106, and 108 selects the maximum clock delay for PDEs 102, 104, 106, and 108, and each of the input multiplexers 126, 134, and 142 of PDEs 104, 106, and 108 with input multiplexers selects the maximum clock delay from the previous PDF. Figure 1 In the embodiments, the input multiplexers 126, 134, and 142 are all 2:1 multiplexers, each receiving the input clock 110 and the maximum clock delay from the previous PDE as inputs. For example, they receive the output of the delay element 124 in the first PDE 102 as input to the second PDE 104, the output of the delay element 132 in the second PDE 104 as input to the third PDE 106, and the output of the delay element 140 in the third PDE 106 as input to the fourth PDE 108.

[0025] Further embodiments of the PDE are summarized as output multiplexers of various sizes, input multiplexers of various sizes, various numbers of delay elements in delay chains, various numbers of PDEs connected together within a programmable clock circuit, various connections of various delay elements of various PDEs to input multiplexers of other PDEs and to output multiplexers in PDEs, and adjustments for various delay values. Various delay elements in various circuits and techniques are possible (see some examples in Figure 4). Further embodiments of the PDE are summarized as various directions and options for linking delay elements (see... Figure 2 and Figure 3 And consider its applicability Figure 1 Those changes).

[0026] Figure 2 Another embodiment is shown with four PDEs 202, 204, 206, and 208 linked together using a doubly linked chain. This provides greater flexibility compared to having a unidirectional chain, because in the unidirectional chain embodiment, the leftmost PDE 102 lacks an input clock multiplexer and is limited by adding successive delays to the input clock 110 (see...). Figure 1 And the offset is 250ps. In contrast, in Figure 2 In the bidirectional chain embodiment, the two middle PDEs 204 and 206 can be offset by up to 750 ps, ​​while the left PDE 202 and the right PDE 208 can be offset by up to 1000 ps. A direction is selected to link the delay elements. When each output multiplexer 112, 114, 116, and 118 of all PDEs 202, 204, 206, and 208 selects the maximum clock delay for PDEs 202, 204, 206, and 208, and each input multiplexer 126, 134, and 142 of PDEs 204, 206, and 208 selects the maximum clock delay from the left PDE, the largest possible delay value for the offset clock output of the rightmost PDE 208 is selected. By selecting opposite directions to link the delay elements, when each output multiplexer 112, 114, 116, 118 of all PDEs 202, 204, 206, 208 selects the maximum clock delay for PDEs 202, 204, 206, 208, and each input multiplexer 210, 126, 134, 142 of PDEs 202, 204, 206, 208 selects the maximum clock delay from the PDE on the right, the largest possible delay value of the offset clock is selected for the offset clock output of the leftmost PDE 202. Therefore, there are two opposite directions for linking the delay elements, making this embodiment bidirectional.

[0027] exist Figure 2In the embodiment, the input multiplexers 210 and 142 in the leftmost PDE 202 and the rightmost PDE 208 are each 2:1 multiplexers. Each receives the input clock 110 and the maximum clock delay from the adjacent PDE as input. For example, it receives the output of the delay element 132 in the second PDE 204 as input to the first PDE 202, and receives the output of the delay element 140 in the third PDE 206 as input to the fourth PDE 208. The input multiplexers 210 and 142 of the two middle PDEs 204 and 206 are each 3:1 multiplexers. Each receives an input clock 110 and the maximum clock delay from each of the two adjacent PDEs in both directions as inputs. For example, it receives the output of delay element 124 in the first PDE 202 and the output of delay element 140 in the third PDE 206 as inputs to the second PDE 204, and receives the output of delay element 132 in the second PDE 204 and the output of delay element 148 in the fourth PDE 208 as inputs to the third PDE 206.

[0028] Figure 3 Another embodiment of four PDEs 302, 304, 306, and 308 linked together is shown. Figure 3 The embodiment of the chain structure in the middle has a higher degree of complexity than... Figure 2 The chain structure shown offers greater flexibility. In one embodiment, this is achieved by creating a link between the leftmost and rightmost PDEs, resulting in a loop structure. Figure 3 As shown, this loop structure can be implemented in a bidirectional embodiment, or using... Figure 1 Multiple aspects of the illustrated embodiments are implemented in a unidirectional embodiment.

[0029] exist Figure 3 In the illustrated bidirectional loop embodiment, each input multiplexer 310, 126, 134, 142 in PDEs 302, 304, 306, 308 is a 3:1 multiplexer selected from an input clock 110 and the maximum delay from the chain of delay elements in the left and right adjacent PDEs (thus allowing the loop circuit to surround the end or leftmost and rightmost PDEs in the architecture). The input multiplexers 310, 126, 134, 142 in a given PDE 302, 304, 306, 308 produce the selected clock for that PDE, and the chain of delay elements in that PDE produces successive delays to that clock. Similar to other embodiments, output multiplexers 112, 114, 116, 118 are selected from the input clock of the PDE and the delay and delay element outputs in the chain to produce offset clock outputs for PDEs 302, 304, 306, 308.

[0030] In a unidirectional loop embodiment, each input multiplexer in the PDE is a 2:1 multiplexer that selects between the input clock 110 and the maximum delay from the chain of delay elements in the adjacent PDE on the left, thereby again allowing around-adjacent, such that in this case, the leftmost PDE receives the maximum delay from the rightmost PDE as input.

[0031] In another unidirectional cyclic embodiment, each of the input multiplexers in the PDE is a 2:1 multiplexer that selects between the input clock 110 and the maximum delay from the chain of delay elements in the adjacent PDE on the right, thereby again allowing around-adjacent, such that in this case, the rightmost PDE receives the maximum delay from the leftmost PDE as input.

[0032] Figures 4A-4F Example delay elements that can be used in various embodiments of a PDE are shown. These and other example delay elements can be implemented as transistor circuits in various transistor and integrated circuit technologies. These and other delay elements can be used in clock generation and clock buffering in known circuits as standard, and are used herein as such Figures 1-3 The delay element in the embodiments and variations of the PDE shown.

[0033] Figure 4A Non-inverting buffer 402 and inverting buffer or inverter 404 are shown. These and other circuits can be tuned to achieve buffer delays using transistor size, intrinsic or extrinsic impedance, voltage-controlled delays, and other timing control and circuit design techniques.

[0034] Figure 4B A non-overlapping clock and inverting clock generator is shown, formed by a cross-coupled NOR gate 406 followed by an inverting buffer or inverter 404. A non-inverting buffer can also be used.

[0035] Figure 4C A non-overlapping clock and inverting clock generator is shown, formed by a cross-coupled NAND gate 408 followed by an inverting buffer or inverter 404. A non-inverting buffer can also be used.

[0036] Figure 4D An RC delay circuit is shown, consisting of a resistor 410 and a capacitor 142 connected in series and connected at a junction between the resistor 410 and the capacitor 412 to a Schmitt trigger 414 (which is an amplifier with hysteresis). Schmitt triggers (inverting or non-inverting) are easily designed in electronic circuits.

[0037] Figure 4EAnother RC delay circuit is shown, consisting of a variable resistor 416 and a variable capacitor 418 connected in series, and connected at the junction between the resistor 416 and the capacitor 418 to an amplifier or non-inverting buffer 402. In variations, an inverter 404, a Schmitt trigger 414, or other amplifiers may be used. A variable resistor 416 and a fixed capacitor, or a fixed resistor and a variable capacitor, may be used. The variable resistor 416 and / or the variable capacitor 418 may be laser trimming circuit components, or may be varied by active circuitry under voltage control, switching, or other techniques.

[0038] Figure 4F An operational amplifier is shown that can be temporarily used as a buffer or non-inverting buffer through easily designed appropriate connections and support circuitry. The delay control circuitry for the operational amplifier is readily designed for both tuned and controlled versions.

[0039] Figure 5 An embodiment is shown in which a hierarchical delay element chain with an offset clock is provided to a hierarchical structure 524 of a clock circuit in an FPGA 500 programmed by a CAD system 530 using CAD tool 526. In an operational scenario, a user 532 interacts with the CAD system 530, which has a CAD tool 526 executed by a processor 528. The user 532 instructs the CAD system 530 to program the FPGA 500, for example, according to a CAD database provided or developed by the user through the CAD tool 526. Figure 5 In the embodiments shown, for example, as described herein by means of programmable delay elements, the FPGA 500 is programmed to generate successive delays of clocks and to generate clocks for various clock circuits.

[0040] Continue to refer to Figure 5The FPGA prior to programming has available programmable delay elements 504, 505, 506, for example, as hard circuitry in an unprogrammed FPGA. Optionally, in a further embodiment, programming the FPGA configures various circuits to form a PDE. In both cases, the programmed FPGA 500 has various clock circuits, depending on a user-provided or developed design. In this embodiment, the clock circuits have a hierarchical structure 524. For example, there are individual clock circuits 518, each of which has a clock. There are groups 520 of clock control circuits 518, and each group 520 has a designated clock. Furthermore, there is a master clock circuit 522 that operates entirely by a designated master clock (e.g., a global or system clock, or possibly a spine clock) or possibly multiple master clocks (e.g., a high-speed clock, a low-speed clock, a logic clock, an RF clock, a PLL clock, etc.). Part of the programming process for FPGA 500 involves CAD tool 526 specifying routing connection 510, which routes various optional delay clocks from PDEs 504, 505, and 506 to the hierarchical structure 524 of the clock circuit. Another part of the programming process for FPGA 500 involves CAD tool 526 specifying selection logic 508, which selects from PDEs 504, 505, and 506 within the programmed FPGA 500 various optional delay clocks for routing connection 510 of the hierarchical structure 524 leading to the clock circuit. It should be understood that a sufficient number of PDEs are required in the group or set of programmable delay elements 502 to meet the need to provide a number of different delayed clocks to the hierarchical structure 524 of the clock circuit. These delayed clocks include one or more independent clocks 512, each of which is provided to one or more independent clock circuits 518; one or more group clocks 514, each of which is provided to one or more groups of clock circuits 520; and one or more master clocks, each of which is provided to the master clock circuit 522. In other hierarchical structures, multiple clocks may exist.

[0041] Figure 6 This is a flowchart of an operation method for an electronic circuit device, which can be used or practiced using the embodiments described herein.

[0042] In action 602, in each programmable delay element (PDE), a successive delay of the clock is generated through a chain of delay elements. For example, in an electronic circuit with multiple PDEs, each PDE has a chain of delay elements, and these delay elements generate a successive delay of the clock of the PDE.

[0043] In action 604, within at least a subset of PDEs, a second multiplexer selects between a first clock (e.g., the input clock of the PDE) and a second clock from a delay element of another PDE to generate a clock for the delay element chain of the PDE. For example, in an electronic circuit with multiple PDEs, each PDE in the subset has a second multiplexer for that PDE. The second multiplexer selects between a first clock and a second clock to generate a clock for the PDE. The second clock comes from another PDE. The clock thus generated is applied to the delay element chain in the PDE in action 602.

[0044] In action 606, within each PDE, a first multiplexer selects between the input clock and delay elements in the delay element chain to produce an offset clock output for the PDE. For example, in an electronic circuit with multiple PDEs, each PDE has a first multiplexer for that PDE. The first multiplexer selects between a first clock and successive delays and delay elements to produce an offset clock output.

[0045] In various embodiments, using the method described above, by linking a delayed clock from one PDE to another, a group of PDEs can produce a variety of offset clock outputs with a delay selection range greater than that available from a single PDE or a group of PDEs without clock linking.

[0046] Some of the detailed descriptions above pertain to the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the field of data processing most effectively communicate their work to others in the field. Here, an algorithm is generally considered a self-consistent sequence of steps that produces a desired result. These steps require physical manipulation of physical quantities. Typically, though not always necessary, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has been shown that, primarily for general reasons, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, and numbers.

[0047] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise explicitly stated in the discussion below, it should be understood that throughout this specification, discussions using terms such as “processing” or “calculating with a computer” or “computing” or “determining” or “displaying” refer to the actions and processing of a computer system or similar electronic computing device, which manipulates data represented as physical (electronic) quantities in the registers and memory of the computer system and converts that data into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display devices.

[0048] The present invention also relates to means for performing the operations described herein. Such means may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions and each connected to a bus of a computer system.

[0049] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will become apparent from the description below. Furthermore, this invention is not described with reference to any particular programming language. It will be understood that the teachings of this invention as described herein can be implemented using various programming languages.

[0050] Machine-readable media include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include read-only memory (“ROM”); random access memory (“RAM”); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.); and so on.

[0051] However, after reading the foregoing description, many changes and modifications to the invention will undoubtedly become apparent to those skilled in the art, and it should be understood that any particular embodiment shown and described by way of illustration is in no way intended to be limiting. Therefore, the mention of details of various embodiments is not intended to limit the scope of the claims, which themselves only recite those features deemed essential to the invention.

Claims

1. An electronic circuit arrangement comprising: a plurality of delay elements; a plurality of multiplexers; the plurality of delay elements and the plurality of multiplexers are located in a plurality of PDEs (programmable delay elements), the plurality of PDEs comprising a first PDE and a second PDE, wherein each PDE has a subset of the plurality of delay elements and a subset of the plurality of multiplexers, the first PDE has a first chain of delay elements comprising a first delay element and a second delay element for producing a successive delay of a first clock of the first PDE, and the first PDE has a first multiplexer for selecting between the first clock as an input clock of the first PDE and an output of a delay element in the first chain of delay elements to produce a first offset clock output of the first PDE; and the second PDE has a second chain of delay elements comprising a third delay element and a fourth delay element and a second multiplexer for selecting between a plurality of clocks to produce a second clock of the second chain of delay elements of the second PDE, the plurality of clocks comprising the first clock as an input clock of the second PDE and a third clock from the second delay element of the first PDE.

2. The electronic circuit arrangement of claim 1, wherein: each of the plurality of PDEs comprises three delay elements in the chain of delay elements and a four-input multiplexer as the first multiplexer for producing an offset clock output of a PDE by selecting between the first clock and an output of each of the three delay elements; and the plurality of PDEs are located in a field programmable gate array (FPGA).

3. The electronic circuit arrangement of claim 1, wherein: the plurality of PDEs comprises the first PDE with the first chain of delay elements for producing a successive delay of the first clock and the first multiplexer of the first PDE for producing an offset clock output of the first PDE by selecting between the first clock and an output of each delay element of the first chain of delay elements; and each successive PDE in the plurality of PDEs after the first PDE has a chain of delay elements, the second multiplexer of the successive PDE for producing a clock of the successive PDE by selecting between the first clock and a maximum delay clock located at an end of a chain of delay elements of a previous PDE, and the first multiplexer of the successive PDE for producing an offset clock output of the successive PDE by selecting between the first clock and an output of each delay element in the chain of delay elements of the successive PDE, such that the plurality of PDEs comprise unidirectional chains of delay elements.

4. The electronic circuit arrangement of claim 1, wherein: the first PDE having: the first chain of delay elements; the second multiplexer of the first PDE for generating the first clock of the first PDE by selecting between the input clock of the first PDE and a maximum delay located at the end of a chain of delay elements of a lower one of the plurality of intermediate PDEs; and the first multiplexer of the first PDE for generating the first offset clock output of the first PDE by selecting between the first clock and the output of each delay element in the first chain of delay elements of the first PDE; each of the plurality of intermediate PDEs having: a chain of delay elements; the second multiplexer of the intermediate PDE for generating a clock of the intermediate PDE by selecting between the first clock and a maximum delay clock located at the end of a chain of delay elements of a preceding PDE; and the first multiplexer of the intermediate PDE for generating an offset clock of the intermediate PDE by selecting between the first clock and the output of each delay element in the chain of delay elements of the intermediate PDE; and the last PDE having: a chain of delay elements; the second multiplexer of the last PDE for generating a clock of the last PDE by selecting between the first clock and a maximum delay located at the end of a chain of delay elements of a higher one of the plurality of intermediate PDEs; and the first multiplexer for generating an offset clock output of the last PDE by selecting between the first clock and the output of each delay element in the chain of delay elements of the last PDE, such that the plurality of PDEs comprises a bidirectional chain of delay elements.

5. The electronic circuit arrangement of claim 1, wherein: each of the plurality of PDEs having: a chain of delay elements; the second multiplexer of the PDE for generating a clock of the PDE by selecting between the first clock and a maximum delay clock located at the end of a chain of delay elements of a preceding PDE; and the first multiplexer of the PDE for generating an offset clock output of the PDE by selecting between the first clock and the output of each delay element in the chain of delay elements of the PDE, such that the plurality of PDEs comprises a unidirectional circular chain of delay elements.

6. The electronic circuit arrangement of claim 1, wherein: each of the plurality of PDEs having: a chain of delay elements; the second multiplexer of the PDE for generating a clock of the PDE by selecting between the first clock, a maximum delay clock located at the end of a chain of delay elements of another first PDE, and a maximum delay clock located at the end of a chain of delay elements of another second PDE; and the first multiplexer of the PDE to produce an offset clock output of the PDE by selecting between the first clock and an output of each delay element in a chain of delay elements of the PDE, such that the plurality of PDEs includes a bi-directional circular chain of delay elements.

7. The electronic circuit arrangement of claim 1, further comprising: selection logic to control the plurality of multiplexers to select a plurality of delays for routing one or more independent clocks to independent clock circuits, one or more group clocks to groups of clock circuits, and one or more master clocks to a plurality of clock circuits from delay elements and offset clock outputs of PDEs, such that the plurality of PDEs includes a hierarchical chain of delay elements providing offset clocks to clock circuits in a hierarchical structure.

8. A method of operating an integrated circuit having multiplexers and delay elements to provide offset clocks, the method comprising: producing successive delays of a clock in each of a plurality of programmable delay elements, PDEs, having a subset of the multiplexers and delay elements of the integrated circuit, the plurality of PDEs including a first PDE and a second PDE, the first PDE having a first chain of delay elements including a first delay element and a second delay element to produce successive delays of a first clock of the first PDE and a first multiplexer, the second PDE having a second chain of delay elements including a third delay element and a fourth delay element and a second multiplexer; in the second PDE, selecting by the second multiplexer between the first clock as an input clock of the second PDE and a third clock from the second delay element of the first PDE to produce a second clock of the second chain of delay elements of the second PDE; and in each of the plurality of PDEs, selecting by the first multiplexer between the first clock as an input clock of the first PDE and an output of a delay element in the first chain of delay elements to produce a first offset clock output of the first PDE.

9. The method of claim 8, wherein: producing the successive delays by the chain of delay elements includes producing the successive delays by three delay elements; and selecting by the first multiplexer includes selecting by a four-input multiplexer between the first clock and an output of each of the three delay elements to produce an offset clock output of the PDE.

10. The method of claim 8, wherein: selecting by the first multiplexer in the first PDE of the plurality of PDEs includes selecting between the first clock and an output of each delay element of the first chain of delay elements to produce the first offset clock output of the first PDE; producing the successive delays of the clock in the first PDE includes producing the successive delays of the first clock by the first chain of delay elements; and selecting by the first multiplexer in each of the plurality of PDEs includes selecting between the first clock and an output of each delay element of the first chain of delay elements to produce an offset clock output of the PDE. selecting, in each successive PDE in the plurality of PDEs after the first PDE, by the second multiplexer includes selecting between the first clock and the third clock that is a maximum delay clock located at the end of a delay element chain of a preceding PDE to produce a clock of the successive PDE; and selecting, in each successive PDE in the plurality of PDEs after the first PDE, by the first multiplexer includes selecting between the first clock and an output of each delay element of the delay element chain in the successive PDE to produce a skewed clock output of the successive PDE, such that the plurality of PDEs includes a unidirectional delay element chain.

11. The method of claim 8, wherein: selecting, in the first PDE in the plurality of PDEs, by the second multiplexer includes selecting between the first clock and a maximum delay located at the end of a delay element chain of a lower one of the plurality of intermediate PDEs to produce a clock of the first PDE; selecting, in the first PDE, by the first multiplexer includes selecting between the first clock and an output of each delay element of the delay element chain in the first PDE to produce a skewed clock output of the first PDE; selecting, in each PDE of the plurality of intermediate PDEs, by the second multiplexer includes selecting between the first clock, a maximum delay clock located at the end of a delay element chain of a preceding PDE, and a maximum delay clock located at the end of a delay element chain of a succeeding PDE to produce a clock of the PDE; selecting, in each PDE of the plurality of intermediate PDEs, by the first multiplexer includes selecting between the first clock and an output of each delay element of the delay element chain in the PDE to produce a skewed clock output of the PDE; selecting, in the last PDE in the plurality of PDEs, by the second multiplexer includes selecting between the first clock and a maximum delay located at the end of a delay element chain of a higher one of the plurality of intermediate PDEs to produce a clock of the last PDE; and selecting, in the last PDE, by the first multiplexer includes selecting between the first clock and an output of each delay element of the delay element chain in the last PDE to produce a skewed clock output of the last PDE, such that the plurality of PDEs includes a bidirectional delay element chain.

12. The method of claim 8, wherein: selecting, in each PDE in the plurality of PDEs, by the second multiplexer includes selecting between the first clock and a maximum delay clock located at the end of a delay element chain of a preceding PDE to produce a clock of the PDE; and selecting, in each PDE in the plurality of PDEs, by the first multiplexer includes selecting between the first clock and an output of each delay element of the delay element chain in the PDE to produce a skewed clock output of the PDE. selecting, in each of the plurality of PDEs, by the first multiplexer, comprises selecting between the first clock and an output of each delay element of a chain of delay elements in the PDE to produce an offset clock output of the PDE, such that the plurality of PDEs comprise a unidirectional circular chain of delay elements.

13. The method of claim 8, wherein: selecting, in each of the plurality of PDEs, by the second multiplexer, comprises selecting between the first clock, a maximum delayed clock located at an end of a chain of delay elements of another first PDE, and a maximum delayed clock located at an end of a chain of delay elements of another second PDE to produce a clock of the PDE; and selecting, in each of the plurality of PDEs, by the first multiplexer, comprises selecting between the first clock and an output of each delay element of a chain of delay elements to produce an offset clock output of the PDE, such that the plurality of PDEs comprise a unidirectional circular chain of delay elements.

14. The method of claim 8, further comprising: operating the PDEs by selection logic to select a plurality of delays for routing one or more independent clocks to independent clock circuits, one or more group clocks to groups of clock circuits, and one or more master clocks to a plurality of clock circuits from delay elements and offset clock outputs of the PDEs, such that the plurality of PDEs comprise a hierarchical chain of delay elements providing offset clocks to clock circuits in a hierarchical structure.

15. A tangible, non-transitory computer-readable medium having instructions thereon that, when executed by a processor, cause the processor to perform a method comprising: programming a field programmable gate array (FPGA) to: in each of a plurality of programmable delay elements (PDEs) having a multiplexer and a subset of delay elements of the FPGA, produce a successive delay of a clock by a chain of delay elements, the plurality of PDEs comprising a first PDE and a second PDE, the first PDE having a first chain of delay elements comprising a first delay element and a second delay element to produce a successive delay of a first clock of the first PDE and a first multiplexer, the second PDE having a second chain of delay elements comprising a third delay element and a fourth delay element and a second multiplexer; in the second PDE, select, by the second multiplexer, between the first clock as an input clock of the second PDE and a third clock from the second delay element of the first PDE to produce a second clock of the second chain of delay elements of the second PDE; and in each of the plurality of PDEs, select, by the first multiplexer, between the first clock as an input clock of the first PDE and a delay element output in the first chain of delay elements to produce a first offset clock output of the first PDE.

16. The computer readable medium of claim 15, wherein programming the FPGA comprises: selecting, in the first PDE of the plurality of PDEs, by the first multiplexer comprises selecting between the first clock and an output of each delay element of the chain of delay elements in the first PDE to produce the first offset clock output of the first PDE; producing successive delays of the first clock in the first PDE comprises producing successive delays of the first clock by the chain of delay elements in the first PDE; selecting, in each successive PDE of the plurality of PDEs after the first PDE, by the second multiplexer comprises selecting between the first clock and the third clock as the maximum delayed clock at the end of the chain of delay elements of the preceding PDE to produce a clock of the successive PDE; and selecting, in each successive PDE of the plurality of PDEs after the first PDE, by the first multiplexer comprises selecting between the first clock and an output of each delay element of the chain of delay elements in the successive PDE to produce an offset clock output of the successive PDE, such that the plurality of PDEs comprise a chain of unidirectional delay elements.

17. The computer readable medium of claim 15, wherein programming the FPGA comprises: selecting, in the first PDE of the plurality of PDEs, by the second multiplexer comprises selecting between the first clock and a maximum delay at the end of the chain of delay elements in a lower one of the plurality of intermediate PDEs to produce a clock of the first PDE; selecting, in the first PDE, by the first multiplexer comprises selecting between the first clock and an output of each delay element of the chain of delay elements in the first PDE to produce an offset clock output of the first PDE; selecting, in each PDE of the plurality of intermediate PDEs, by the second multiplexer comprises selecting between the first clock, a maximum delayed clock at the end of the chain of delay elements of the preceding PDE, and a maximum delayed clock at the end of the chain of delay elements of the next PDE to produce a clock of the PDE; selecting, in each PDE of the plurality of intermediate PDEs, by the first multiplexer comprises selecting between the first clock and an output of each delay element of the chain of delay elements in the PDE to produce an offset clock output of the PDE; selecting, in the last PDE of the plurality of PDEs, by the second multiplexer comprises selecting between the first clock and a maximum delay at the end of the chain of delay elements in a higher one of the plurality of intermediate PDEs to produce a clock of the last PDE; and selecting, in the last PDE, by the first multiplexer includes selecting between the first clock and an output of each delay element of a chain of delay elements in the last PDE to produce an offset clock output of the last PDE, such that the plurality of PDEs includes a unidirectional chain of delay elements.

18. The computer readable medium of claim 15, wherein programming the FPGA includes: selecting, in each PDE of the plurality of PDEs, by the second multiplexer includes selecting between the first clock and a maximum delay clock located at an end of a chain of delay elements of a preceding PDE to produce a clock of the PDE; and selecting, in each PDE of the plurality of PDEs, by the first multiplexer includes selecting between the first clock and an output of each delay element of a chain of delay elements in the PDE to produce an offset clock output of the PDE, such that the plurality of PDEs includes a unidirectional chain of delay elements.

19. The computer readable medium of claim 15, wherein programming the FPGA includes: selecting, in each PDE of the plurality of PDEs, by the second multiplexer includes selecting between the first clock, a maximum delay clock located at an end of a chain of delay elements of another first PDE, and a maximum delay clock located at an end of a chain of delay elements of another second PDE to produce a clock of the PDE; and selecting, in each PDE of the plurality of PDEs, by the first multiplexer includes selecting between the first clock and an output of each delay element of a chain of delay elements to produce an offset clock output of the PDE, such that the plurality of PDEs includes a bidirectional chain of delay elements.

20. The computer readable medium of claim 15, wherein the instructions further cause the processor to further program the FPGA to: operate PDEs by selection logic to select a plurality of delays from delay elements and offset clock outputs of PDEs for routing one or more independent clocks to independent clock circuits, routing one or more PDE clocks to PDEs of clock circuits, and routing one or more master clocks to a plurality of clock circuits, such that the plurality of PDEs includes a hierarchical chain of delay elements that provides offset clocks to clock circuits in a hierarchical structure.

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