Method and apparatus for measuring clock jitter, terminal and storage medium

Abstract

The application provides a clock jitter measurement method, device, terminal and storage medium. The method comprises: obtaining sampling data obtained by coherent sampling of a target analog-to-digital conversion circuit on a point frequency signal; selecting any sampling point except an extreme value point as a first sampling point from the sampling data, and taking the sampling serial number of the first sampling point in a first sampling period as a first sampling serial number; selecting any sampling serial number between the first sampling serial number and the first extreme value point serial number as a second sampling serial number; calculating the ratio of the time difference between the first sampling serial number and the second sampling serial number to the difference between the quantization values; calculating the standard deviation of each quantization value corresponding to the first sampling serial number or the second sampling serial number; and calculating the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and the standard deviation. The application can measure the clock jitter performance of the target analog-to-digital conversion circuit without using a complex device, and the measurement precision is the same as the quantization value precision.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a method, apparatus, terminal, and storage medium for measuring clock jitter. Background Technology

[0002] Clock jitter refers to the non-accumulating, random-direction, and random-amplitude deviation of the actual clock relative to the ideal clock edge. Clock jitter performance is a crucial performance indicator for analog-to-digital converters (ADCs). In measurement systems based on coherent sampling, the signal-to-noise ratio (SNR) of the ADC output data significantly impacts the system's measurement resolution and sensitivity. Since the SNR of an ADC is greatly affected by clock jitter performance, accurately evaluating the clock jitter performance of the ADC is of paramount importance for the precise and efficient assessment of its SNR in measurement systems.

[0003] Currently, phase noise meters can measure clock jitter performance with accuracy at picosecond and below, but they are costly. Simple coherent measurement methods require clock jitter measurement of analog-to-digital converter circuits based on sawtooth waves, but generating standard sawtooth waves is difficult, resulting in low measurement accuracy. Summary of the Invention

[0004] This invention provides a method, apparatus, terminal, and storage medium for measuring clock jitter, in order to solve the problem of reducing the cost of accurately measuring the clock jitter performance of analog-to-digital conversion circuits.

[0005] In a first aspect, the present invention provides a method for measuring clock jitter, comprising:

[0006] Acquire the sampling data obtained by the target analog-to-digital converter circuit coherently sampling the point frequency signal;

[0007] Select any sampling point other than the extreme point from the sampled data as the first sampling point, and take the sampling number of the first sampling point in the first sampling period as the first sampling number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling number of the first extreme point after the first sampling number in the first sampling period, and take it as the first extreme point number; select any sampling number between the first sampling number and the first extreme point number as the second sampling number;

[0008] Select a quantized value from the quantized values ​​corresponding to the first sampling number in the sampled data as the quantized value of the first sampling number, and select a quantized value from the quantized values ​​corresponding to the second sampling number in the sampled data as the quantized value of the second sampling number;

[0009] The time interval between the first sampling number and the second sampling number within the same sampling period is taken as the time difference between the first sampling number and the second sampling number;

[0010] Calculate the ratio of the time difference between the first and second sampling numbers to the difference in quantization values;

[0011] Calculate the standard deviation of each quantization value corresponding to the first or second sampling number; and calculate the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and standard deviation.

[0012] In one possible implementation, the standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio and the standard deviation, including:

[0013] The standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio, standard deviation, and a first preset formula; the first preset formula is:

[0014]

[0015] Among them, Clock jitter Δt represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit, ΔADC represents the time difference between the first and second sampling numbers, σ represents the difference in quantization values ​​between the first and second sampling numbers, and σ represents the standard deviation.

[0016] In one possible implementation, the sampled data includes a statistical histogram, where the horizontal axis represents the quantified value and the vertical axis represents the frequency of occurrence.

[0017] Select a quantized value from the quantized values ​​corresponding to the first sampling sequence number in the sampled data as the quantized value of the first sampling sequence number, including:

[0018] Based on the statistical histogram, the quantization value with the highest frequency of occurrence in the quantization value corresponding to the first sampling number in the sampled data is determined, and this quantization value is used as the quantization value of the first sampling number.

[0019] In one possible implementation, the sampled data includes a statistical histogram, where the horizontal axis represents the quantified value and the vertical axis represents the frequency of occurrence.

[0020] Calculate the standard deviation of each quantized value corresponding to the first or second sampling number, including:

[0021] Calculate the full width and height of the statistical histogram corresponding to the first or second sampling number;

[0022] The standard deviation of each quantization value corresponding to the first or second sampling number is calculated based on the full width at half maximum (FWHM).

[0023] In one possible implementation, after calculating the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and standard deviation, the method further includes:

[0024] The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC.

[0025] In one possible implementation, the signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC, including:

[0026] The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC and a second preset formula; the second preset formula is:

[0027] SNR=-20log(2πf IN Clock jitter )

[0028] Where SNR represents the signal-to-noise ratio of the target analog-to-digital converter circuit, f IN Clock represents the frequency of a point frequency signal. jitter This represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit.

[0029] Secondly, the present invention provides a clock jitter measuring device, comprising:

[0030] The acquisition module is used to acquire the sampling data obtained by the target analog-to-digital converter circuit coherently sampling the point frequency signal;

[0031] The sequence number determination module is used to select any sampling point other than the extreme point from the sampled data as the first sampling point, and use the sampling sequence number of the first sampling point in the first sampling period as the first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and use it as the first extreme point sequence number; and select any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as the second sampling sequence number.

[0032] The quantization value selection module is used to select a quantization value from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number, and to select a quantization value from the quantization values ​​corresponding to the second sampling number in the sampled data as the quantization value of the second sampling number.

[0033] The time difference calculation module is used to take the time interval between the first sampling number and the second sampling number within the same sampling period as the time difference between the first sampling number and the second sampling number.

[0034] The ratio calculation module is used to calculate the ratio of the time difference between the first sampling number and the second sampling number to the difference in the quantization value;

[0035] The standard deviation calculation module is used to calculate the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number; and to calculate the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and the standard deviation.

[0036] Thirdly, the present invention provides a terminal including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the clock jitter measurement method as shown in the first aspect above or any possible implementation of the first aspect.

[0037] Fourthly, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the clock jitter measurement method as shown in the first aspect or any possible implementation thereof.

[0038] This invention provides a method, apparatus, terminal, and storage medium for measuring clock jitter. The method includes: acquiring sampling data obtained by coherently sampling a point-frequency signal by a target analog-to-digital converter circuit; selecting any sampling point other than extreme points from the sampling data as a first sampling point, and using the sampling sequence number of the first sampling point in a first sampling period as a first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determining the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and using it as the first extreme point sequence number; selecting any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as a second sampling sequence number; and from the first... The sampling sequence number selects a quantized value from the corresponding quantized values ​​in the sampled data as the quantized value of the first sampling sequence number, and selects a quantized value from the corresponding quantized values ​​in the sampled data as the quantized value of the second sampling sequence number. The time interval between the first and second sampling sequence numbers within the same sampling period is taken as the time difference between the first and second sampling sequence numbers. The ratio of the time difference between the first and second sampling sequence numbers to the difference in quantized values ​​is calculated. The standard deviation of each quantized value corresponding to the first or second sampling sequence number is calculated. Based on the ratio and standard deviation, the standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated. This invention transforms the distribution of quantized values ​​of the sampled data into the distribution of clock jitter of the target analog-to-digital converter circuit by using the ratio of the time change of two phases to the change of quantized values ​​in the sampling period. This allows for the measurement of the clock jitter performance of the target analog-to-digital converter circuit without the need for complex devices, and the measurement accuracy is the same as the quantization accuracy. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating the implementation of the clock jitter measurement method provided in this embodiment of the invention.

[0041] Figure 2 This is a statistical histogram of sampling data provided in one embodiment of the present invention;

[0042] Figure 3 This is a statistical histogram of sampling data provided in another embodiment of the present invention;

[0043] Figure 4 This is a statistical histogram of sampling data provided in another embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the clock jitter measuring device provided in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of the terminal provided in an embodiment of the present invention. Detailed Implementation

[0046] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0048] See Figure 1 The flowchart illustrating the implementation of the clock jitter measurement method provided in this embodiment of the invention is described in detail below:

[0049] Step 101: Obtain the sampling data obtained by the target analog-to-digital converter circuit coherently sampling the point frequency signal;

[0050] In this embodiment, the commonly used sampling methods for ADCs are oversampling, quadrature sampling, and bandpass sampling. Bandpass sampling is the primary sampling method for intermediate frequency (IF) or radio frequency (RF) signals. When the signal to be processed is a high-frequency bandpass signal, although the frequency of the sampled signal is very high, the signal to be processed is relatively narrow relative to the carrier frequency. For such signals, bandpass sampling can significantly reduce the sampling frequency and simultaneously perform spectrum shifting. Therefore, bandpass sampling not only reduces the signal sampling rate but also reduces the workload of backend data processing, effectively improving data processing efficiency. This embodiment can measure the ADC clock jitter performance during bandpass sampling, as well as the ADC clock jitter performance under other sampling methods. To obtain more sampled values ​​for each sampling point, this embodiment makes the frequency of the point frequency signal coherent with the sampling frequency of the target analog-to-digital converter circuit, so that the number of sampling points and the phase of each sampling point are fixed in each sampling cycle, facilitating centralized analysis.

[0051] Step 102: Select any sampling point other than the extreme point from the sampled data as the first sampling point, and take the sampling number of the first sampling point in the first sampling period as the first sampling number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling number of the first extreme point after the first sampling number in the first sampling period, and take it as the first extreme point number; select any sampling number between the first sampling number and the first extreme point number as the second sampling number.

[0052] In this embodiment, to establish the correspondence between ADC quantization value jitter and ADC clock jitter, it is necessary to utilize the characteristic that the sinusoidal portion between the first and second sampling numbers within the same period can be approximately linear. Therefore, there should be no extreme points between the first and second sampling numbers within the same period, and the number of sampling numbers between the first and second sampling numbers should be as small as possible. When the corresponding positions of the first and second sampling numbers on the point-frequency signal curve should be in a monotonically increasing or decreasing interval, and the first and second sampling numbers are adjacent, local linearization processing can be applied to the sinusoidal portion between the first and second sampling numbers within the same period.

[0053] Furthermore, the frequency of the point-frequency signal is coherent with the sampling frequency, assuming Where f IN f is the frequency of the point frequency signal. sample Let be the sampling frequency. Then the time interval between the nth sampling point and the (n+1)th sampling point is: T sample T is the period of the sampling clock. INLet n be the period of the point frequency signal. It can be seen that the nth sampling point and the (n+1)th sampling point do not fall in the same period of the point frequency signal. However, by statistically analyzing the sampled data and mapping each sampling point to a periodic sine curve, we can obtain 5 sampling numbers. Based on these sampling numbers and the corresponding ADC quantization values, we can still use the method provided in this embodiment to measure the jitter performance of the ADC clock.

[0054] Step 103: Select a quantization value from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number, and select a quantization value from the quantization values ​​corresponding to the second sampling number in the sampled data as the quantization value of the second sampling number.

[0055] In this embodiment, the quantization value refers to the numerical value obtained by the ADC after sampling and quantizing the point-frequency signal, which is used to represent the amplitude of the sampled data. The target ADC will sample the point-frequency signal for multiple cycles, obtaining a large amount of sampled data. Therefore, each sampling sequence number will correspond to multiple quantization values, and one quantization value needs to be selected from these quantization values ​​for subsequent calculations.

[0056] Step 104: The time interval between the first sampling number and the second sampling number within the same sampling period is taken as the time difference between the first sampling number and the second sampling number.

[0057] In this embodiment, the clock jitter of the target ADC is an unknown quantity, so an ideal time interval is used as the time interval between the first sampling sequence number and the second sampling sequence number within the same sampling period.

[0058] Step 105: Calculate the ratio of the time difference between the first sampling number and the second sampling number to the difference in the quantization value.

[0059] In this embodiment, the ratio of the time difference to the difference of the quantization value can reflect the change in sampling time corresponding to each minute change in the quantization value, thereby corresponding the jitter of the quantization value to the jitter of the sampling clock.

[0060] Step 106: Calculate the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number; and calculate the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and standard deviation.

[0061] In this embodiment, the standard deviation of each quantization value corresponding to the first sampling number can reflect the dispersion of each quantization value corresponding to the first sampling number. The ratio of the time difference between the first sampling number and the second sampling number to the difference of the quantization value can reflect the rate of change of time with the quantization value at the position of the first sampling number. This characteristic also applies to the second sampling number. Therefore, based on this ratio, the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number can be converted into the standard deviation of each sampling time corresponding to the first sampling number or the second sampling number, thereby obtaining the dispersion of the sampling time of the target ADC, i.e., the clock jitter performance.

[0062] In some embodiments, calculating the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and standard deviation includes:

[0063] The standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio, standard deviation, and a first preset formula; the first preset formula is:

[0064]

[0065] Among them, Clock jitter Δt represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit, ΔADC represents the time difference between the first and second sampling numbers, σ represents the difference in quantization values ​​between the first and second sampling numbers, and σ represents the standard deviation.

[0066] In this embodiment, This represents the time variation corresponding to the micro-component of each quantized value. Multiplying this by the standard deviation of each quantized value corresponding to the first sampling number gives the standard deviation of the sampling time corresponding to the first sampling number.

[0067] In some embodiments, the sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence;

[0068] Select a quantized value from the quantized values ​​corresponding to the first sampling sequence number in the sampled data as the quantized value of the first sampling sequence number, including:

[0069] Based on the statistical histogram, the quantization value with the highest frequency of occurrence in the quantization value corresponding to the first sampling number in the sampled data is determined, and this quantization value is used as the quantization value of the first sampling number.

[0070] In this embodiment, the quantization value that appears most frequently can be considered as the quantization value corresponding to that sampling sequence number when the target ADC has no clock jitter. The quantization value of the second sampling sequence number is selected using the same steps. Based on the quantization value selected in this step, a more accurate ratio of the time difference between the first and second sampling sequences to the difference in quantization values ​​can be calculated.

[0071] In some embodiments, the sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence;

[0072] Calculate the standard deviation of each quantized value corresponding to the first or second sampling number, including:

[0073] Calculate the full width and height of the statistical histogram corresponding to the first or second sampling number;

[0074] The standard deviation of each quantization value corresponding to the first or second sampling number is calculated based on the full width at half maximum (FWHM).

[0075] In this embodiment, when the target ADC experiences clock jitter and the first sampling sequence does not correspond to an extreme point of the sine signal, the statistical histogram corresponding to the first sampling sequence approximates a normal distribution. Based on the full width at half maximum (FWHM) of a normal distribution ≈ 2.355 × standard deviation, the standard deviation of each quantization value corresponding to the first sampling sequence can be calculated.

[0076] In some embodiments, after calculating the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and standard deviation, the method further includes:

[0077] The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC.

[0078] In this embodiment, after determining the clock jitter performance of the target ADC, the signal-to-noise ratio of the target ADC sampling data can be calculated based on the frequency of the point frequency signal.

[0079] In some embodiments, calculating the signal-to-noise ratio of the target analog-to-digital converter (ADC) based on the standard deviation of the clock jitter of the target ADC includes:

[0080] The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC and a second preset formula; the second preset formula is:

[0081] SNR=-20log(2πf IN Clock jitter )

[0082] Where SNR represents the signal-to-noise ratio of the target analog-to-digital converter circuit, f IN Clock represents the frequency of a point frequency signal. jitter This represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit.

[0083] In one specific embodiment, a high-precision radio frequency signal source generates a 500MHz point frequency signal, and the target ADC operates in "bandpass sampling mode" to sample this point frequency signal, with a sampling clock frequency of 116.16MHz. Coherent sampling requires three conditions to be met:

[0084] (1) The sampled signal should be a complete periodic signal;

[0085] (2) "Fin / Fs=M / N", where Fin is the frequency of the sampled signal, Fs is the sampling frequency, M is the number of periods sampled by the sampled signal, and N is the number of sampling points;

[0086] (3) M and N are integers and are prime numbers to avoid repeated sampling.

[0087] In this embodiment, the frequency Fin of the signal to be sampled is 500MHz; the sampling clock frequency Fs is 116.16MHz; M is 99; and N is 23.

[0088] Figure 2 This is a statistical histogram of the sampled data obtained after simulating sampling of the point-frequency signal using the target ADC based on the above parameters, under ideal conditions where the target ADC has no clock jitter. Figure 2 It can be seen that, under ideal conditions, there are 23 sampling points in a complete signal cycle. If the input signal, sampling clock and the sampling process of the target ADC are all ideal, then the statistical histogram of the ADC sampling data is a bar chart with 23 equal height bars.

[0089] The effective value of the clock jitter of the target ADC is set to 1 picosecond, and after simulating sampling of the point frequency signal using the target ADC based on the above parameters, the following results are obtained: Figure 3 The statistical histogram of the sampled data is shown below. Figure 3 It can be seen that after adding clock jitter, the statistical histogram of the sampled data will become wider and shorter at each sampling point, and the statistical count near the maximum and minimum values ​​will be greater than the statistical count near the zero point.

[0090] Since the slope of the sine wave signal at the "π / 4" position is 1, the clock jitter of the target ADC is 1:1 with the jitter of the quantized value of the sampled data. In this embodiment, the statistical histogram of the sampled data near the "π / 4" position is taken as the research object, and the clock jitter performance of the target ADC is calculated using the measurement method provided in this application. The specific steps are as follows:

[0091] (1) When the frequency of the point frequency signal is 500MHz, its signal period is 2ns. If the signal is sampled at 23 equal intervals, the time difference between adjacent sampling points is "2ns / 23". Therefore, it can be found that... Figure 3The position of "π / 4" is found between the two bars with an x-axis of 1 and 1.5 (but it does not correspond to the bar with an x-axis between 1 and 1.5, whose quantization value is not specified). Therefore, the sampling number corresponding to the bar with an x-axis of 1 is taken as the first sampling number, and the sampling number corresponding to the bar with an x-axis of 1.5 is taken as the second sampling number. Based on the statistical histograms of the first and second sampling numbers, the quantization value of the first sampling number is determined to be 9694, and the quantization value of the second sampling number is 13633. Since the two sampling numbers are adjacent, the time difference between them in the same sampling period is "2ns / 23". Then, the ratio of the time difference between the first and second sampling numbers to the difference in quantization value can be calculated as "2ns / (23×(13633-9694))=2.2076×10-5ns".

[0092] (2) Figure 4 For example, the statistical histogram of the sampled data corresponding to the first sampling number, such as Figure 4 As shown, the full width at half maximum (FWHM) of this statistical histogram is "FWHM = 9747 - 9634 = 113". The standard deviation σ of this statistical histogram can be calculated using the formula "FWHM = 2.355σ".

[0093] (3) Substitute the above ratios and standard deviations into the formula:

[0094]

[0095] The calculated standard deviation of the clock jitter is 1.06 picoseconds, which is basically consistent with the set 1 picosecond clock jitter.

[0096] (4) Substitute the standard deviation of clock jitter into the signal-to-noise ratio calculation formula:

[0097] SNR=-20log(2πf IN Clock jitter )

[0098] The signal-to-noise ratio of the target ADC was calculated to be 49.55 dB.

[0099] As can be seen from the above, the accuracy of the clock jitter measurement method provided in this embodiment can reach 0.01 picoseconds.

[0100] The clock jitter measurement method provided in this embodiment of the invention includes: acquiring sampling data obtained by coherently sampling a point-frequency signal by a target analog-to-digital converter circuit; selecting any sampling point other than extreme points from the sampling data as a first sampling point, and using the sampling sequence number of the first sampling point in the first sampling period as the first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determining the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and using it as the first extreme point sequence number; selecting any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as a second sampling sequence number; and selecting the sampling data from the first sampling sequence number in the sampling period... A quantized value is selected from the corresponding quantized values ​​in the data as the quantized value of the first sampling sequence number. A quantized value is selected from the corresponding quantized values ​​of the second sampling sequence number in the sampled data as the quantized value of the second sampling sequence number. The time interval between the first and second sampling sequences within the same sampling period is taken as the time difference between the first and second sampling sequences. The ratio of the time difference between the first and second sampling sequences to the difference in quantized values ​​is calculated. The standard deviation of each quantized value corresponding to the first or second sampling sequence number is calculated. Based on the ratio and standard deviation, the standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated. This invention transforms the distribution of quantized values ​​in the sampled data into the distribution of clock jitter in the target analog-to-digital converter circuit by using the ratio of the time change of two phases to the change of quantized values ​​in the sampling period. This allows for the measurement of the clock jitter performance of the target analog-to-digital converter circuit without the need for complex devices, and the measurement accuracy is the same as the quantization accuracy.

[0101] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0102] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0103] Figure 5 A schematic diagram of the clock jitter measuring device provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0104] like Figure 5 As shown, the clock jitter measuring device 5 includes:

[0105] The acquisition module 51 is used to acquire the sampling data obtained by the target analog-to-digital conversion circuit coherently sampling the point frequency signal;

[0106] The sequence number determination module 52 is used to select any sampling point other than the extreme point from the sampled data as the first sampling point, and use the sampling sequence number of the first sampling point in the first sampling period as the first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and use it as the first extreme point sequence number; and select any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as the second sampling sequence number.

[0107] The quantization value selection module 53 is used to select a quantization value from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number, and to select a quantization value from the quantization values ​​corresponding to the second sampling number in the sampled data as the quantization value of the second sampling number.

[0108] The time difference calculation module 54 is used to take the time interval between the first sampling number and the second sampling number within the same sampling period as the time difference between the first sampling number and the second sampling number.

[0109] The ratio calculation module 55 is used to calculate the ratio of the time difference between the first sampling number and the second sampling number to the difference of the quantization value;

[0110] The standard deviation calculation module 56 is used to calculate the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number; and to calculate the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and the standard deviation.

[0111] In some embodiments, the standard deviation calculation module 56 is specifically used for:

[0112] The standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio, standard deviation, and a first preset formula; the first preset formula is:

[0113]

[0114] Among them, Clock jitter Δt represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit, ΔADC represents the time difference between the first and second sampling numbers, σ represents the difference in quantization values ​​between the first and second sampling numbers, and σ represents the standard deviation.

[0115] In some embodiments, the sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence;

[0116] The quantization value selection module 53 is specifically used for:

[0117] Based on the statistical histogram, the quantization value with the highest frequency of occurrence in the quantization value corresponding to the first sampling number in the sampled data is determined, and this quantization value is used as the quantization value of the first sampling number.

[0118] In some embodiments, the sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence;

[0119] The standard deviation calculation module 56 is specifically used for:

[0120] Calculate the full width and height of the statistical histogram corresponding to the first or second sampling number;

[0121] The standard deviation of each quantization value corresponding to the first or second sampling number is calculated based on the full width at half maximum (FWHM).

[0122] In some embodiments, the standard deviation calculation module 56 is further configured to:

[0123] After calculating the standard deviation of the clock jitter of the target analog-to-digital converter (ADC) based on the ratio and standard deviation, the signal-to-noise ratio (SNR) of the target ADC is calculated based on the standard deviation of the clock jitter of the target ADC.

[0124] In some embodiments, the standard deviation calculation module 56 is specifically used for:

[0125] The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC and a second preset formula; the second preset formula is:

[0126] SNR=-20log(2πf IN Clock jitter )

[0127] Where SNR represents the signal-to-noise ratio of the target analog-to-digital converter circuit, f IN Clock represents the frequency of a point frequency signal. jitter This represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit.

[0128] The clock jitter measurement device provided in this embodiment of the invention includes: an acquisition module 51, used to acquire sampling data obtained by coherent sampling of a point-frequency signal by a target analog-to-digital converter circuit; a sequence number determination module 52, used to select any sampling point other than an extreme point from the sampling data as a first sampling point, and use the sampling sequence number of the first sampling point in a first sampling period as the first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and use it as the first extreme point sequence number, and select any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as a second sampling sequence number; and a quantization value selection module 53, used to select the quantization value from the first sampling sequence number in the sampling data. The system selects a quantized value from the corresponding quantized values ​​in the sampled data as the quantized value of the first sampling sequence number, and selects a quantized value from the corresponding quantized values ​​of the second sampling sequence number as the quantized value of the second sampling sequence number. A time difference calculation module 54 is used to take the time interval between the first and second sampling sequences within the same sampling period as the time difference between the first and second sampling sequences. A ratio calculation module 55 is used to calculate the ratio of the time difference between the first and second sampling sequences to the difference in quantized values. A standard deviation calculation module 56 is used to calculate the standard deviation of each quantized value corresponding to the first or second sampling sequence number; and calculates the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and standard deviation. This invention transforms the distribution of quantized values ​​in the sampled data into the distribution of clock jitter in the target analog-to-digital converter circuit by using the ratio of the time change of two phases to the change of quantized values ​​in the sampling period. This allows for the measurement of the clock jitter performance of the target analog-to-digital converter circuit without the need for complex devices, and the measurement accuracy is the same as the quantization accuracy.

[0129] Figure 6 This is a schematic diagram of a terminal provided in an embodiment of the present invention. For example... Figure 6 As shown, the terminal 6 in this embodiment includes: a processor 60, a memory 61, and a computer program 62 stored in the memory 61 and executable on the processor 60. When the processor 60 executes the computer program 62, it implements the steps in the various clock jitter measurement method embodiments described above, for example... Figure 1 Steps 101 to 106 are shown. Alternatively, when the processor 60 executes the computer program 62, it implements the functions of each module in the above-described device embodiments, for example... Figure 5 The functions of modules 51 to 56 are shown.

[0130] For example, the computer program 62 can be divided into one or more modules, which are stored in the memory 61 and executed by the processor 60 to complete the present invention. The one or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 62 in the terminal 6. For example, the computer program 62 can be divided into... Figure 5 Modules 51 to 56 are shown.

[0131] The terminal 6 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The terminal 6 may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will understand that... Figure 6 This is merely an example of terminal 6 and does not constitute a limitation on terminal 6. It may include more or fewer components than shown, or combine certain components, or different components. For example, the terminal may also include input / output devices, network access devices, buses, etc.

[0132] The processor 60 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0133] The memory 61 can be an internal storage unit of the terminal 6, such as a hard disk or memory of the terminal 6. The memory 61 can also be an external storage device of the terminal 6, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the terminal 6. Furthermore, the memory 61 can include both internal storage units and external storage devices of the terminal 6. The memory 61 is used to store the computer program and other programs and data required by the terminal. The memory 61 can also be used to temporarily store data that has been output or will be output.

[0134] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0135] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0136] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0137] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0138] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0140] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various clock jitter measurement method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc. It should be noted that the content contained in the computer-readable medium may be appropriately added to or subtracted from the content as required by the legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium may not include electrical carrier signals and telecommunication signals.

[0141] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for measuring clock jitter, characterized in that, include: Acquire the sampling data obtained by the target analog-to-digital converter circuit coherently sampling the point frequency signal; Select any sampling point other than the extreme point from the sampled data as the first sampling point, and take the sampling number of the first sampling point in the first sampling period as the first sampling number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling number of the first extreme point after the first sampling number in the first sampling period, and take it as the first extreme point number; select any sampling number between the first sampling number and the first extreme point number as the second sampling number; A quantization value is selected from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number, and a quantization value is selected from the quantization values ​​corresponding to the second sampling number in the sampled data as the quantization value of the second sampling number. The time interval between the first sampling number and the second sampling number within the same sampling period is taken as the time difference between the first sampling number and the second sampling number; Calculate the ratio of the time difference between the first sampling number and the second sampling number to the difference in the quantization value; Calculate the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number; and calculate the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and the standard deviation; The calculation of the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and the standard deviation includes: The standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio, the standard deviation, and the first preset formula; the first preset formula is: in, This represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit. This represents the time difference between the first sampling number and the second sampling number. This represents the difference in quantization values ​​between the first sampling number and the second sampling number. This represents the standard deviation of each quantized value corresponding to the first sampling number or the second sampling number.

2. The method for measuring clock jitter according to claim 1, characterized in that, The sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence. The step of selecting a quantization value from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number includes: Based on the statistical histogram, the quantization value that appears most frequently among the corresponding quantization values ​​of the first sampling number in the sampled data is determined, and this quantization value is used as the quantization value of the first sampling number.

3. The method for measuring clock jitter according to claim 1, characterized in that, The sampling data includes a statistical histogram, where the horizontal axis of the statistical histogram represents the quantified value and the vertical axis represents the frequency of occurrence. The calculation of the standard deviation of each quantized value corresponding to the first sampling number or the second sampling number includes: Calculate the full width and height of the statistical histogram corresponding to the first sampling number or the second sampling number; The standard deviation of each quantization value corresponding to the first sampling number or the second sampling number is calculated based on the full width at half maximum (FWHM).

4. The method for measuring clock jitter according to any one of claims 1 to 3, characterized in that, After calculating the standard deviation of the clock jitter of the target analog-to-digital converter circuit based on the ratio and the standard deviation, the method further includes: The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC.

5. The method for measuring clock jitter according to claim 4, characterized in that, The calculation of the signal-to-noise ratio of the target analog-to-digital converter (ADC) based on the standard deviation of the clock jitter of the target ADC includes: The signal-to-noise ratio of the target analog-to-digital converter (ADC) is calculated based on the standard deviation of the clock jitter of the target ADC and a second preset formula; the second preset formula is: in, This represents the signal-to-noise ratio of the target analog-to-digital conversion circuit. This indicates the frequency of the point frequency signal. The standard deviation of the clock jitter of the target analog-to-digital converter circuit is represented.

6. A device for measuring clock jitter, characterized in that, include: The acquisition module is used to acquire the sampling data obtained by the target analog-to-digital converter circuit performing bandpass sampling on the point frequency signal; The sequence number determination module is used to select any sampling point other than the extreme point from the sampled data as the first sampling point, and use the sampling sequence number of the first sampling point in the first sampling period as the first sampling sequence number; the first sampling period is the sampling period in which the first sampling point is located; determine the sampling sequence number of the first extreme point after the first sampling sequence number in the first sampling period, and use it as the first extreme point sequence number; and select any sampling sequence number between the first sampling sequence number and the first extreme point sequence number as the second sampling sequence number. The quantization value selection module is used to select a quantization value from the quantization values ​​corresponding to the first sampling number in the sampled data as the quantization value of the first sampling number, and to select a quantization value from the quantization values ​​corresponding to the second sampling number in the sampled data as the quantization value of the second sampling number. The time difference calculation module is used to take the time interval between the first sampling number and the second sampling number within the same sampling period as the time difference between the first sampling number and the second sampling number; The ratio calculation module is used to calculate the ratio of the time difference between the first sampling number and the second sampling number to the difference of the quantization value; The standard deviation calculation module is used to calculate the standard deviation of each quantization value corresponding to the first sampling number or the second sampling number; and to calculate the standard deviation of the clock jitter of the target analog-to-digital conversion circuit based on the ratio and the standard deviation. The standard deviation calculation module is specifically used for: The standard deviation of the clock jitter of the target analog-to-digital converter circuit is calculated based on the ratio, the standard deviation, and the first preset formula; the first preset formula is: in, This represents the standard deviation of the clock jitter of the target analog-to-digital converter circuit. This represents the time difference between the first sampling number and the second sampling number. This represents the difference in quantization values ​​between the first sampling number and the second sampling number. This represents the standard deviation of each quantized value corresponding to the first sampling number or the second sampling number.

7. A terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the clock jitter measurement method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the clock jitter measurement method as described in any one of claims 1 to 5.

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