A program execution method, system, device and storage medium

Abstract

The present invention discloses a program execution method, comprising the following steps: obtaining a program to be executed; dividing the program to be executed into a plurality of first subprograms suitable for execution in a CPU and a plurality of second subprograms suitable for a hardware accelerator, and judging whether there is a second subprogram that can be further divided; in response to the existence of a second subprogram that can be further divided, continuing to divide the second subprogram into a plurality of third subprograms suitable for execution in a CPU and a plurality of fourth subprograms suitable for a hardware accelerator, and judging whether there is a fourth subprogram that can be further divided; in response to the absence of a fourth subprogram, generating a multi-layer CPU and hardware accelerator architecture according to a plurality of first subprograms, a plurality of second subprograms, a plurality of third subprograms, and a plurality of fourth subprograms; respectively executing the first subprogram, the second subprogram, the third subprogram, and the fourth subprogram using the multi-layer CPU and hardware accelerator architecture. The present invention also discloses a system, a computer device, and a readable storage medium.

Description

Technical Field

[0001] The present invention relates to the field of software and hardware collaborative design, and in particular to a program execution method, system, device and storage medium. Background Art

[0002] In general, hardware-software co-design means that for a certain program code, the part suitable for CPU execution and the part suitable for hardware accelerator (such as GPU or ASIC, PCI interface smart network card, etc.) execution are divided, and the parts are executed by CPU and hardware accelerator respectively. In modern computer systems, CPU is the main controller and is more suitable for process control in the code. On the contrary, the part of the code that needs to calculate large amounts of data (data or images) is handed over to the hardware accelerator for execution. After the hardware accelerator completes the calculation, it will report back to the CPU. The CPU and hardware accelerator generally exchange data more efficiently through the DMA mechanism. Although there is a DMA mechanism, every time the CPU and the hardware accelerator need to communicate or exchange data through DMA, the performance of the CPU and the entire main system will still be affected due to excessive interrupt services (Interrupt) or polling (polling) in the process.

[0003] This also means that there are several principles for hardware-software co-design:

[0004] (1) Divide the program code into the most suitable ones for CPU execution and those for hardware accelerators.

[0005] (2) Reduce the number of communications between the CPU (especially the system main CPU) and the hardware accelerator as much as possible;

[0006] However, it is often difficult to clearly separate the program codes suitable for CPU execution and those suitable for hardware accelerators, and it is often found that the program codes suitable for hardware accelerators separated at the upper level may also include some codes suitable for CPU execution. Summary of the invention

[0007] In view of this, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a program execution method, comprising the following steps:

[0008] Get the program to be executed;

[0009] Splitting the program to be executed to obtain a plurality of first subprograms suitable for execution on a CPU and a plurality of second subprograms suitable for execution on a hardware accelerator, and determining whether there is any second subprogram that can be further split;

[0010] In response to the existence of the second subprogram that can be further divided, continue to divide the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further divided;

[0011] In response to not existing, generating a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines;

[0012] The first subroutine, the second subroutine, the third subroutine, and the fourth subroutine are respectively executed using the multi-layer CPU and hardware accelerator architecture.

[0013] In some embodiments, generating a multi-layer CPU and hardware accelerator architecture according to the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine further includes:

[0014] Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

[0015] In some embodiments, it also includes:

[0016] The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

[0017] In some embodiments, it also includes:

[0018] In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

[0019] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a program execution system, including:

[0020] An acquisition module configured to acquire a program to be executed;

[0021] A first segmentation module is configured to segment the program to be executed to obtain a plurality of first subprograms suitable for execution on the CPU and a plurality of second subprograms suitable for execution on the hardware accelerator, and to determine whether there is any second subprogram that can be further segmented;

[0022] a second segmentation module configured to, in response to the existence of the second subprogram that can be further segmented, continue to segment the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further segmented;

[0023] a generating module, configured to generate a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines in response to the absence of the architecture;

[0024] The execution module is configured to respectively execute the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine by utilizing the multi-layer CPU and hardware accelerator architecture.

[0025] In some embodiments, the generation module is further configured to:

[0026] Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

[0027] In some embodiments, the execution module is further configured to:

[0028] The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

[0029] In some embodiments, a third segmentation module is further included, configured to

[0030] In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

[0031] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer device, including:

[0032] at least one processor; and

[0033] A memory storing a computer program executable on the processor, wherein the processor executes the steps of any one of the program execution methods described above when executing the program.

[0034] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any one of the program execution methods described above are performed.

[0035] The present invention has one of the following beneficial technical effects: the present invention proposes a multi-layer software-hardware collaborative design process and architecture, dynamically generates a multi-layer software-hardware collaborative design architecture and circuit for different applications, so that the system performance can be maximized for the execution of each different application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A flowchart of a program execution method provided by an embodiment of the present invention;

[0038] Figure 2 A flowchart of a program execution method provided by an embodiment of the present invention;

[0039] Figure 3 A program segmentation example provided for an embodiment of the present invention;

[0040] Figure 4 Based on Figure 3 The resulting multi-layer CPU and hardware accelerator architecture;

[0041] Figure 5 Another program segmentation example provided for an embodiment of the present invention;

[0042] Figure 6 Based on Figure 5 The resulting multi-layer CPU and hardware accelerator architecture;

[0043] Figure 7 A schematic diagram of the structure of a program execution system provided by an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of the structure of a computer device provided by an embodiment of the present invention;

[0045] Fig. 9 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0047] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.

[0048] In the embodiments of the present invention, software and hardware co-design refers to the collaborative work of the CPU (executing software) and the hardware accelerator (such as GPU or ASIC, PCI interface smart network card, etc.) in modern heterogeneous computing systems to achieve maximum performance for specific applications (such as video streaming, data compression, network packet acceleration access) in heterogeneous computer systems.

[0049] According to one aspect of the present invention, an embodiment of the present invention provides a program execution method, such as Figure 1 As shown, it may include the steps of:

[0050] S1, obtain the program to be executed;

[0051] S2, dividing the program to be executed into a plurality of first subprograms suitable for execution in a CPU and a plurality of second subprograms suitable for execution in a hardware accelerator, and determining whether there is any second subprogram that can be further divided;

[0052] S3, in response to the existence of the second subprogram that can be further divided, continue to divide the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further divided;

[0053] S4, in response to not existing, generating a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines;

[0054] S5, using the multi-layer CPU and hardware accelerator architecture to respectively execute the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine.

[0055] The solution proposed by the present invention achieves system performance optimization by dynamically generating a multi-level hardware-software collaborative design architecture and circuit for different applications. That is, after the upper-level hardware-software calculation is divided, the local CPU can be added to the hardware calculation at the lower level to perform the second-level (and lower / lower-level) hardware-software collaborative calculation. In terms of the process, the CPU and hardware acceleration code are first judged and distinguished for each application, and then a multi-level hardware-software collaborative design circuit for the application is generated based on the above analysis results, so that the execution of the application can be maximized.

[0056] In addition, because different applications need to be analyzed and supported, the circuits generated by the multi-level hardware and software co-design are not necessarily the same.

[0057] In some embodiments, generating a multi-layer CPU and hardware accelerator architecture according to the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine further includes:

[0058] Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

[0059] In some embodiments, it also includes:

[0060] The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

[0061] In some embodiments, it also includes:

[0062] In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

[0063] Specifically, Figure 2 As shown, the first layer of the application can be segmented to obtain multiple first subroutines suitable for CPU execution and multiple second subroutines suitable for hardware accelerators, and then continue to determine whether the second subroutines can be further segmented into multiple third subroutines suitable for CPU execution and multiple fourth subroutines suitable for hardware accelerators, until the lowest layer of hardware acceleration code is not suitable for further segmentation. And according to the segmentation results, the corresponding software and hardware collaboration and hardware accelerator architecture of different layers are generated, so as to execute the above segmented subroutines.

[0064] For example, Figure 3 and Figure 4 As shown, the program to be executed is divided into program 1 (CPU code), program 1 (hardware acceleration code), program 2 (CPU code), and program 2 (hardware acceleration code / second-layer CPU code), among which program 2 (hardware acceleration code / second-layer CPU code) is further divided into program 2-1 (second-layer CPU code) and program 2-2 (hardware acceleration code).

[0065] Then based on the above segmentation procedure, we can get Figure 4 The multi-layer CPU and hardware accelerator architecture shown. The main CPU is responsible for all control processes, receiving and / or sending operation data to hardware accelerator 1 and hardware accelerator 2, and executing program 1 (CPU code) and program 2 (CPU code). Hardware accelerator 1 is responsible for program 1 (hardware acceleration code), hardware accelerator 2 is responsible for program 2 (hardware acceleration code / second-layer CPU code), the local CPU in hardware accelerator 2 is responsible for program 2-1 (second-layer CPU code), and the acceleration module is responsible for program 2-2 (hardware acceleration code).

[0066] Another example Figure 5 and Figure 6 As shown, when a more complex application requires third-layer software-hardware collaborative design acceleration, the program to be executed is divided into program 1 (CPU code), program 1 (hardware acceleration code), program 2 (CPU code), program 2 (hardware acceleration code / second-layer CPU code), among which program 2 (hardware acceleration code / second-layer CPU code) is further divided into program 2-1 (second-layer CPU code), program 2-2 (hardware acceleration code / third-layer CPU code), and program 2-3 (second-layer hardware acceleration code). Among them, program 2-2 (hardware acceleration code / third-layer CPU code) is further divided into program 2-2-1 (third-layer CPU code) and 2-2-2 (third-layer hardware acceleration code).

[0067] Then based on the above segmentation procedure, we can get Figure 6The multi-layer CPU and hardware accelerator architecture shown. The same main CPU is responsible for all control processes, receiving and / or sending operation data to hardware accelerator 1 and hardware accelerator 2, and executing program 1 (CPU code) and program 2 (CPU code). Hardware accelerator 1 is responsible for program 1 (hardware acceleration code), hardware accelerator 2 is responsible for program 2 (hardware acceleration code / second-layer CPU code), the local CPU in hardware accelerator 2 is responsible for program 2-1 (second-layer CPU code), hardware accelerator 2-3 in hardware accelerator 2 is responsible for program 2-3, hardware accelerator 2-2 is responsible for program 2-2, the local CPU in hardware accelerator 2-2 is responsible for program 2-2-1 (third-layer CPU code), and hardware acceleration module 2-2-2 is responsible for program 2-2-2.

[0068] The present invention proposes a multi-layer software-hardware collaborative design process and architecture, dynamically generating a multi-layer software-hardware collaborative design architecture and circuit for different application programs, so that the system can achieve maximum performance for the execution of each different application program.

[0069] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a program execution system 400, such as Figure 7 As shown, including:

[0070] An acquisition module 401 is configured to acquire a program to be executed;

[0071] A first segmentation module 402 is configured to segment the program to be executed into a plurality of first subprograms suitable for execution on a CPU and a plurality of second subprograms suitable for execution on a hardware accelerator, and determine whether there is any second subprogram that can be further segmented;

[0072] The second segmentation module 403 is configured to, in response to the existence of the second subprogram that can be further segmented, continue to segment the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further segmented;

[0073] A generating module 404 is configured to generate a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines in response to the absence of the plurality of the first subroutines;

[0074] The execution module 405 is configured to respectively execute the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine by utilizing the multi-layer CPU and hardware accelerator architecture.

[0075] In some embodiments, the generation module 404 is further configured to:

[0076] Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

[0077] In some embodiments, the execution module 405 is further configured to:

[0078] The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

[0079] In some embodiments, a third segmentation module is further included, configured to

[0080] In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

[0081] Based on the same inventive concept, according to another aspect of the present invention, Figure 8 As shown, an embodiment of the present invention further provides a computer device 501, including:

[0082] at least one processor 520; and

[0083] The memory 510 stores a computer program 511 that can be run on the processor. When the processor 520 executes the program, the processor 520 performs the steps of any of the above program execution methods.

[0084] Based on the same inventive concept, according to another aspect of the present invention, Fig. 9 As shown, an embodiment of the present invention further provides a computer-readable storage medium 601, which stores a computer program 610. When the computer program 610 is executed by a processor, the steps of any of the above program execution methods are performed.

[0085] Finally, it should be noted that a person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods.

[0086] Furthermore, it should be appreciated that the computer-readable storage medium (eg, memory) herein may be either a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0087] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0088] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0089] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0090] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0091] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0092] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A program execution method, characterized in that: The following steps are involved: Get the program to be executed; Splitting the program to be executed to obtain a plurality of first subprograms suitable for execution on a CPU and a plurality of second subprograms suitable for execution on a hardware accelerator, and determining whether there is any second subprogram that can be further split; In response to the existence of the second subprogram that can be further divided, continue to divide the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further divided; In response to not existing, generating a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines; Utilizing the multi-layer CPU and hardware accelerator architecture to respectively execute the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine; Generating a multi-layer CPU and hardware accelerator architecture according to the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine further includes: Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

2. The method according to claim 1, characterized in that Also includes: The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

3. The method according to claim 1, characterized in that Also includes: In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

4. A program execution system, characterized in that: include: An acquisition module configured to acquire a program to be executed; A first segmentation module is configured to segment the program to be executed to obtain a plurality of first subprograms suitable for execution on the CPU and a plurality of second subprograms suitable for execution on the hardware accelerator, and to determine whether there is any second subprogram that can be further segmented; a second segmentation module configured to, in response to the existence of the second subprogram that can be further segmented, continue to segment the second subprogram into a plurality of third subprograms suitable for execution on the CPU and a plurality of fourth subprograms suitable for execution on the hardware accelerator, and determine whether there is the fourth subprogram that can be further segmented; a generating module, configured to generate a multi-layer CPU and hardware accelerator architecture according to a plurality of the first subroutines, a plurality of the second subroutines, a plurality of the third subroutines, and a plurality of the fourth subroutines in response to the absence of the architecture; An execution module, configured to respectively execute the first subroutine, the second subroutine, the third subroutine, and the fourth subroutine using the multi-layer CPU and hardware accelerator architecture; The build module is also configured to: Generate a main CPU for executing the plurality of the first subprograms, a first hardware accelerator for executing the plurality of the second subprograms, and a second hardware accelerator for executing the plurality of the third subprograms and the plurality of the fourth subprograms, wherein the second hardware accelerator includes a slave CPU for executing the plurality of the third subprograms and an accelerator module for executing the plurality of the fourth subprograms.

5. The system according to claim 4, characterized in that The execution module is also configured to: The main CPU is used to be responsible for all control processes and to receive and / or send operation data to the first hardware accelerator and the second hardware accelerator.

6. The system according to claim 4, characterized in that Also includes a third segmentation module configured to In response to the fourth subprogram that can be further divided existing, the fourth subprogram is further divided into a plurality of fifth subprograms suitable for execution on the CPU and a plurality of sixth subprograms suitable for execution on the hardware accelerator.

7. A computer device comprising: at least one processor; as well as A memory storing a computer program executable on the processor, wherein the processor executes the steps of the method according to any one of claims 1 to 3 when executing the program.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are performed.

Images