A memory access method, apparatus, device and medium

Abstract

The application discloses a memory access method and device, equipment and medium, comprising: establishing a first connection between a first processor and a first OpenCAPI accelerator card; sending a memory data access request to a second processor of a second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node; obtaining memory data returned by the second processor for the access request and writing the memory data into a memory. It can be seen that the first connection between the first processor and the first OpenCAPI accelerator card is established in the computing node, and the second connection between the first computing node and the second computing node is established, so that the first processor can access the memory data of the second processor in the second computing node through the first connection and the second connection; the above technical solution realizes cache consistency between processors of different computing nodes, thereby realizing memory data sharing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory access method, device, equipment and medium. BACKGROUND

[0002] With the development of Internet technology, people's requirements for server data processing capacity are getting higher and higher. The amount of data stored by terminal users on the server is getting larger and larger, and the time required for the server to provide a response is getting shorter and shorter. The server cluster in the data center machine room is expanding, and the bandwidth requirement for data transmission within the server cluster is getting higher and higher, and the delay requirement is getting lower and lower. In the face of these demands, server designers need to design more powerful servers, one of the key points is that the memory system of the server needs to be more powerful, that is, the processor requires greater bandwidth and lower latency when accessing memory.

[0003] In the prior art, the memory capacity and computing capacity of a single node of a server are limited; while the computing capacity and memory capacity of a server cluster are greatly improved compared to the former, the processors between different server nodes cannot achieve cache consistency, the processors cannot directly access the memory of the processors in other servers, that is, memory sharing cannot be achieved, and the accessible memory capacity of a single processor cannot be essentially increased. Therefore, the processors in different nodes still perform separate computing and data storage operations, which is not conducive to improving the utilization of server resources.

[0004] In summary, how to access the memory data of the processors in other computing nodes and further achieve cache consistency between the processors of different computing nodes is a problem to be solved at present. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a memory access method, device, equipment and medium, which can access the memory data of the processors in other computing nodes and further achieve cache consistency between the processors of different computing nodes. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a memory access method applied to a first computing node in an OpenPower server, comprising:

[0007] establishing a first connection between the first processor and a first OpenCAPI acceleration card;

[0008] sending a memory data access request to a second processor of a second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node;

[0009] acquire memory data returned by the second processor in response to the access request, and write the memory data into memory.

[0010] Optionally, the establishing the first connection between the first processor and the first OpenCAPI accelerator card comprises:

[0011] establishing a third connection between the OpenCAPI bus interface of the first processor and the first SlimSAS connector of the computing board, and establishing a fourth connection between the first SlimSAS connector and a second SlimSAS connector in the first OpenCAPI accelerator card;

[0012] obtaining the first connection based on the third connection and the fourth connection.

[0013] Optionally, the memory access method further comprises:

[0014] establishing a 100G Ethernet connection between the first QSFP+ interface of the first OpenCAPI accelerator card and a second QSFP+ interface of a second OpenCAPI accelerator card in the second computing node to obtain the second connection.

[0015] Optionally, the acquiring the memory data returned by the second processor in response to the access request and writing the memory data into memory comprises:

[0016] acquiring the memory data returned by the second processor in response to the access request through the second connection by using the first field programmable gate array of the first OpenCAPI accelerator card, and writing the memory data into memory.

[0017] Optionally, the acquiring the memory data returned by the second processor in response to the access request through the second connection by using the first field programmable gate array of the first OpenCAPI accelerator card comprises:

[0018] acquiring the memory data returned by the second processor in response to the access request through the second connection by using the second field programmable gate array of the second OpenCAPI accelerator card;

[0019] acquiring the memory data returned by the second processor in response to the access request through the second connection by using the first field programmable gate array of the first OpenCAPI accelerator card.

[0020] Optionally, the writing the memory data into memory comprises:

[0021] The memory data sent by the first field programmable gate array is acquired by using the OpenCAPI bus interface, and then the memory data is written into memory by the first processor.

[0022] Optionally, the writing of the memory data into memory comprises:

[0023] The memory data stored in the first field programmable gate array is written into memory by using an internal interconnection bus.

[0024] In a second aspect, the present application discloses a memory access device applied to a first computing node in an OpenPower server, comprising:

[0025] A connection establishing module is configured to establish a first connection between a first processor and a first OpenCAPI accelerator card;

[0026] A request sending module is configured to send a memory data access request to a second processor of a second computing node by the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node;

[0027] A memory writing module is configured to acquire memory data returned by the second processor for the access request and write the memory data into memory.

[0028] In a third aspect, the present application discloses an electronic device, comprising:

[0029] A memory is configured to save a computer program;

[0030] A processor is configured to execute the computer program to realize the steps of the memory access method disclosed above.

[0031] In a fourth aspect, the present application discloses a memory access system comprising a plurality of electronic devices disclosed above.

[0032] It can be seen that the application first establishes a first connection between the first processor and the first OpenCAPI accelerator card; then sends a memory data access request to the second processor of the second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node; and finally acquires memory data returned by the second processor in response to the access request and writes the memory data into the memory. It can be seen that the application establishes a first connection between the first processor and the first OpenCAPI accelerator card in the computing node, and establishes a second connection between the first computing node and the second computing node. In this way, the first processor can access the memory data of the second processor in the second computing node through the first connection and the second connection. In this way, the OpenCAPI-based memory access method can ensure cache consistency when the processor in the first computing node and the processor in the second computing node access the same memory address, improve memory use efficiency, and thus realize memory data sharing. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0034] Figure 1 A memory access method flowchart disclosed by the present application;

[0035] Figure 2 A memory access flowchart between two two-way OpenPOWER server computing nodes disclosed by the present application;

[0036] Figure 3 A specific memory access method flowchart disclosed by the present application;

[0037] Figure 4 A topology diagram of cache consistency interconnection between five server computing nodes through OpenCAPI accelerator cards disclosed by the present application;

[0038] Figure 5 A topology diagram of cache consistency interconnection between eighteen server computing nodes through OpenCAPI accelerator cards disclosed by the present application;

[0039] Figure 6 A memory access device structure schematic diagram disclosed by the present application;

[0040] Figure 7A structure diagram of an electronic device is disclosed in the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0042] In the prior art, the memory capacity and the computing capability that can be achieved by a single node of a server are limited. The computing capability and the memory capacity of a server cluster are greatly improved compared with the former, but the cache consistency cannot be achieved between the processors in different server nodes, the processors cannot directly access the memory of the processors in other servers, that is, the memory sharing cannot be achieved, and the accessible memory capacity of a single processor cannot be essentially increased. Therefore, the processors in different nodes still perform separate computing and data storage operations, which is not conducive to improving the utilization rate of server resources. Therefore, the embodiments of the present application disclose a memory access method, device, equipment and medium, which can access the memory data of the processors in other computing nodes, and further achieve the cache consistency between the processors of different computing nodes.

[0043] Referring to Figure 1 The embodiments of the present application disclose a memory access method, which comprises the following steps:

[0044] Step S11: establishing a first connection between the first processor and the first OpenCAPI acceleration card.

[0045] In the embodiments, the establishment of the first connection between the first processor and the first OpenCAPI acceleration card can include: establishing a third connection between the OpenCAPI bus interface of the first processor and the first SlimSAS connector of the computing board, and establishing a fourth connection between the first SlimSAS connector and the second SlimSAS connector in the first OpenCAPI acceleration card; and then obtaining the first connection based on the third connection and the fourth connection. It can be understood that the first connection can include the third connection established between the OpenCAPI bus interface of the first processor and the first SlimSAS connector of the computing board, and the fourth connection established between the first SlimSAS connector and the second SlimSAS connector in the first OpenCAPI acceleration card.

[0046] Referring to Figure 2As shown, the embodiments of the present application disclose a memory access flowchart between two two-way OpenPOWER server computing nodes. In the two-way OpenPOWER server in the embodiments, each CPU (i.e. the above processor) can provide two groups of OpenCAPI bus interfaces, and two CPUs in one node can provide at most four groups of OpenCAPI bus interfaces. Taking processor 1 in the computing node 1 and processor 2 in the computing node 2 as an example, the OpenCAPI interface of the processor 1 on the computing board is connected to a SlimSAS connector which can support a 25G rate; the OpenCAPI signal between the OpenCAPI accelerator card and the computing board is transmitted through a SlimSAS cable, that is, the SlimSAS connector on the computing board and the SlimSAS connector in the OpenCAPI accelerator card transmit data through the SlimSAS cable. It should be noted that OpenCAPI is an open interconnection bus standard supporting cache coherence, and the OpenPOWER CPU can support OpenCAPI 3.0 protocol, and the support rate is 25Gbps; the OpenCAPI accelerator card is an OpenCAPI adapter card in a half-high half-long PCIe structure form, and the controller on the card is an FPGA chip; the power supply and management of the OpenCAPI accelerator card are realized through a standard PCIe interface, that is, the OpenCAPI adapter needs to occupy a half-high half-long standard PCIe slot. Generally, a conventional server can support a half-high half-long PCIe card, and the OpenCAPI accelerator card is realized by borrowing a standard PCIe form, and its power supply, management, heat dissipation and structure are relatively simple to realize, and it is not necessary to additionally develop power supply, management, heat dissipation and structure design on the server.

[0047] Step S12: sending, by the first processor, a memory data access request to a second processor of the second computing node based on the first connection and a second connection previously established between the first computing node and the second computing node.

[0048] In the embodiments, the first processor in the first computing node can send a memory data access request to the second processor in the second computing node through the first connection established between the first OpenCAPI accelerator card and the second connection previously established between the first computing node and the second computing node, to obtain corresponding memory data. The above memory access method can further include: establishing a 100G Ethernet connection between the first QSFP+ interface of the first OpenCAPI accelerator card and the second QSFP+ interface of the second OpenCAPI accelerator card in the second computing node, to obtain the second connection. Figure 2In the prior art, the external interface of the OpenCAPI acceleration card is a standard QSFP+ interface, and the standard 100 Gbps Ethernet cable is supported, so that the OpenCAPI acceleration cards in different computing nodes are connected through a 100 Gbps Ethernet cable to obtain the second connection described above. A two-way server node can support up to four OpenCAPI acceleration cards, so that the OpenCAPI acceleration cards can be connected to four computing nodes to access the processors and memories thereof. The processors 1 and 2 of the computing nodes 1 and 2 in the prior art are cache coherent. Through the technical solution described above, the cache coherence between the processor 1 of the computing node 1 and the processor 1 of the computing node 2 is achieved, that is, the processor 1 of the computing node 1 can not only access the local memory 1 and the local memory 2, but also access the remote memory 1 of the computing node 2, and vice versa, that is, the processor 1 of the computing node 2 can not only access the local memory 1 and the local memory 2, but also access the remote memory 1 of the computing node 1.

[0049] Further, in combination with the cache coherence connection between the processors 1 and 2 in the same node in the prior art and the cache coherence connection based on OpenCAPI in the present application, the cache coherence between the four processors, that is, the processor 1 of the computing node 1, the processor 2 of the computing node 1, the processor 1 of the computing node 2 and the processor 2 of the computing node 2, can be achieved. For example, the processor 1 of the computing node 1 accesses the memory of the processor 2 of the computing node 2 through the OpenCAPI protocol, and then accesses the memory of the processor 2 of the computing node 2 through the cache coherence protocol in the node, that is, the memory sharing between the two processors is achieved in a two-hop manner.

[0050] Step S13: obtaining the memory data returned by the second processor for the access request, and writing the memory data into the memory.

[0051] In the embodiment, the memory data returned by the second processor for the access request is obtained, and the memory data is written into the local memory, so that the memory use efficiency is improved, and the memory data sharing is achieved.

[0052] It can be seen that the application first establishes a first connection between the first processor and the first OpenCAPI accelerator card; then sends a memory data access request to the second processor of the second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node; and finally obtains memory data returned by the second processor in response to the access request and writes the memory data into memory. It can be seen that the application establishes a first connection between the first processor and the first OpenCAPI accelerator card in the computing node, and establishes a second connection between the first computing node and the second computing node. In this way, the first processor can access memory data of the second processor in the second computing node through the first connection and the second connection. In this way, the OpenCAPI-based memory access method can ensure cache consistency when processors in the first computing node and processors in the second computing node access the same memory address, improve memory use efficiency, and thus realize memory data sharing.

[0053] Referring to Figure 3 The embodiment of the application discloses a specific memory access method. Compared with the previous embodiment, the embodiment further describes and optimizes the technical solution. Specifically, the embodiment includes the following steps:

[0054] Step S21: Establishing a first connection between the first processor and the first OpenCAPI accelerator card.

[0055] Step S22: Sending a memory data access request to the second processor of the second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node.

[0056] Step S23: Obtaining memory data returned by the second processor in response to the access request through the second connection by using the first field programmable gate array of the first OpenCAPI accelerator card, and writing the memory data into memory.

[0057] In the embodiment, the first field programmable gate array of the first OpenCAPI accelerator card acquires the memory data returned by the second processor through the second connection in response to the access request, including: the second field programmable gate array of the second OpenCAPI accelerator card acquires the memory data returned by the second processor in response to the access request; and the first field programmable gate array of the first OpenCAPI accelerator card acquires the memory data sent by the second OpenCAPI accelerator card through the second connection. It should be noted that the field programmable gate array (FPGA) in the OpenCAPI accelerator card is configured as an OpenCAPI interface IP core and a 100G network controller IP core. The FPGA can forward the OpenCAPI data from the processor through the 100G Ethernet network, or send the data from the 100G Ethernet network to the processor through the OpenCAPI interface, or directly write the data to the memory through the internal interconnection bus. Therefore, when acquiring the memory data, the second field programmable gate array of the second OpenCAPI accelerator card acquires the memory data returned by the second processor in response to the access request, and then the first field programmable gate array of the first OpenCAPI accelerator card acquires the memory data sent by the second OpenCAPI accelerator card through the 100G Ethernet connection.

[0058] In a specific embodiment, the memory data is written into the memory, including: the OpenCAPI bus interface is used to acquire the memory data sent by the first field programmable gate array, and then the first processor is used to write the memory data into the memory. That is, in the embodiment, the data from the 100G Ethernet network stored in the first field programmable gate array can be sent to the first processor through the OpenCAPI bus interface, and then written into the local memory by the first processor.

[0059] In another specific embodiment, the memory data is written into the memory, including: the internal interconnection bus is used to write the memory data stored in the first field programmable gate array into the memory. That is, in the embodiment, the data from the 100G Ethernet network stored in the first field programmable gate array can be directly written into the local memory through the internal interconnection bus.

[0060] The more specific processing process of steps S21 and S22 will be described in detail in the foregoing embodiments, and will not be repeated here.

[0061] It can be seen that, when the memory data returned by the second processor for the access request is acquired, the first field programmable gate array of the first OpenCAPI accelerator card is used to acquire the memory data returned by the second processor for the access request through the second connection, and when the memory data is written into the local memory, on the one hand, the memory data sent by the first field programmable gate array can be acquired by using the OpenCAPI bus interface of the first computing node, and then the memory data is written into the local memory by the first processor; on the other hand, the memory data stored in the first field programmable gate array can be directly written into the memory by using the internal interconnection bus.

[0062] It should be noted that the technical solution of the present application is not limited to the connection between two computing nodes, and can be extended to cache coherence interconnection in more computing nodes, and the scale can form a cache coherence memory sharing cluster system, greatly improving the capacity and bandwidth of the single node accessible memory. Figure 4 A topology diagram for cache coherence interconnection between 5 server computing nodes through OpenCAPI accelerator cards is disclosed, wherein there is a 100Gbps optical fiber cable (i.e. 100G Ethernet) between each two computing nodes. This connection mode expands the memory access space by 4 times, while effectively controlling the delay of accessing remote memory, i.e. there is only one OpenCAPI jump between each two computing nodes. For example, the memory accessed by computing node 1 to computing nodes 2 / 3 / 4 / 5 is called remote memory, and its delay is greater than that of accessing the local memory in computing node 1, and the increment of the delay is the delay generated by the OpenCAPI interconnection link. For applications with higher memory capacity requirements but lower memory delay requirements, more computing nodes can be connected for cache coherence interconnection based on OpenCAPI accelerator cards, Figure 5 A topology diagram for cache coherence interconnection between 18 server computing nodes through OpenCAPI accelerator cards is disclosed. In this connection mode, all computing nodes can still maintain cache coherence, but the delay of remote memory will increase, i.e. multiple OpenCAPI accelerator jumps are required. For example, the processor of node 1 accesses the remote memory of node 18, which requires 5 OpenCAPI jumps, as shown by the dashed line in the attached Figure 3 The present application can technically realize interconnection of more nodes, but the memory access delay and the actual memory space required by the application need to be considered comprehensively. It should be noted that the access delay of remote memory in the multi-node interconnection system of the present application is greater than that of the local memory. To solve this problem, hot data is stored in the local memory with lower delay, and cold data is stored in the remote memory with higher delay, thereby improving the data access efficiency. In addition, the cold and hot data layering in the present embodiment can be implemented in the application layer.

[0063] Reference is made to Figure 6As shown, the embodiment of the present application discloses a memory access device, applied to a first computing node in an OpenPower server, the device comprises:

[0064] The connection establishment module 11 is configured to establish a first connection between the first processor and the first OpenCAPI accelerator card.

[0065] The request sending module 12 is configured to send a memory data access request to a second processor of a second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node.

[0066] The memory writing module 13 is configured to acquire memory data returned by the second processor for the access request and write the memory data into a memory.

[0067] As can be seen, the present application first establishes a first connection between the first processor and the first OpenCAPI accelerator card; then sends a memory data access request to a second processor of a second computing node through the first processor based on the first connection and a second connection previously established between the first computing node and the second computing node; finally acquires memory data returned by the second processor for the access request and writes the memory data into a memory. As can be seen, the present application establishes a first connection between the first processor and the first OpenCAPI accelerator card in the computing node, and establishes a second connection between the first computing node and the second computing node. In this way, the first processor can access the memory data of the second processor in the second computing node through the first connection and the second connection. In this way, the memory access method based on OpenCAPI can guarantee the cache consistency when the processor in the first computing node and the processor in the second computing node access the same memory address, improve the memory use efficiency, and further realize the memory data sharing.

[0068] Figure 7 A structural schematic diagram of an electronic device provided by the embodiment of the present application. Specifically, it can include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is configured to store a computer program, the computer program is loaded and executed by the processor 21 to realize the related steps in the memory access method executed by the computer device disclosed in any of the preceding embodiments.

[0069] In this embodiment, the power supply 23 is configured to provide working voltage for each hardware device on the computer device 20; the communication interface 24 is configured to create a data transmission channel between the computer device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which will not be specifically limited herein; the input and output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which will not be specifically limited herein.

[0070] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 can also include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0071] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223, etc. The storage mode can be temporary storage or permanent storage.

[0072] The operating system 221 is used to manage and control each hardware device on the computer device 20 and the computer program 222, so as to realize the operation and processing of the processor 21 on the mass data 223 in the memory 22, and can be Windows, Unix, Linux, etc. The computer program 222 can further include a computer program capable of completing other specific work in addition to the computer program capable of completing the memory access method disclosed by any one of the preceding embodiments executed by the computer device 20. The data 223 can include data transmitted by an external device received by the computer device, and also can include data collected by the self input and output interface 25, etc.

[0073] Further, the embodiment of the present application further discloses a storage medium, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to realize the method steps executed in the memory access process disclosed by any one of the preceding embodiments.

[0074] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. For the device disclosed by the embodiment, since it corresponds to the method disclosed by the embodiment, the description is relatively simple, and the related parts can be referred to the method part.

[0075] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized by electronic hardware, computer software or combination of both. In order to clearly show the interchangeability of hardware and software, the composition and steps of each example have been described in the above description. Whether the functions are realized by hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0076] The steps of the method or algorithm described in combination with the embodiments disclosed in the present text can be directly implemented by hardware, software module executed by a processor, or combination of both. The software module can be placed in a random access memory (RAM), a memory, a read only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0077] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the stated element.

[0078] The above describes in detail a memory access method, device, equipment and storage medium provided by the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A memory access method, characterized by, A first computing node applied to an OpenPower server, comprising: establishing a first connection between the first processor and the first OpenCAPI accelerator card: establishing a third connection through an OpenCAPI bus interface of the first processor and a first SlimSAS connector of the computing board, and establishing a fourth connection through the first SlimSAS connector and a second SlimSAS connector in the first OpenCAPI accelerator card, obtaining the first connection based on the third connection and the fourth connection; establishing a 100G Ethernet connection between a first QSFP+ interface of the first OpenCAPI accelerator card and a second QSFP+ interface of a second OpenCAPI accelerator card in a second computing node to obtain a second connection; sending a memory data access request to a second processor of the second computing node through the first processor based on the first connection and the second connection; obtaining memory data returned by the second processor for the access request through a second field programmable gate array of the second OpenCAPI accelerator card; obtaining the memory data sent by the second OpenCAPI accelerator card through the second connection by using a first field programmable gate array array of the first OpenCAPI accelerator card; writing the memory data into memory: obtaining the memory data sent by the first field programmable gate array array through the OpenCAPI bus interface of the first processor, and then writing the memory data into memory through the first processor.

2. A memory access device, characterized by, A first computing node applied to an OpenPower server, comprising: a connection establishing module, configured to establish a first connection between the first processor and the first OpenCAPI accelerator card: establish a third connection through an OpenCAPI bus interface of the first processor and a first SlimSAS connector of the computing board, and establish a fourth connection through the first SlimSAS connector and a second SlimSAS connector in the first OpenCAPI accelerator card, obtain the first connection based on the third connection and the fourth connection, and establish a 100G Ethernet connection between a first QSFP+ interface of the first OpenCAPI accelerator card and a second QSFP+ interface of a second OpenCAPI accelerator card in a second computing node to obtain a second connection; a request sending module, configured to send a memory data access request to a second processor of the second computing node through the first processor based on the first connection and the second connection; The memory writing module is configured to acquire memory data returned by the second processor for the access request through a second field programmable gate array of the second OpenCAPI accelerator card; acquire the memory data sent by the second OpenCAPI accelerator card through the second connection by using a first field programmable gate array of the first OpenCAPI accelerator card; and write the memory data into memory by using an OpenCAPI bus interface of the first processor to acquire the memory data sent by the first field programmable gate array, and then write the memory data into memory by using the first processor.

3. An electronic device, comprising: The memory writing module is configured to acquire memory data returned by the second processor for the access request through a second field programmable gate array of the second OpenCAPI accelerator card; acquire the memory data sent by the second OpenCAPI accelerator card through the second connection by using a first field programmable gate array of the first OpenCAPI accelerator card; and write the memory data into memory by using an OpenCAPI bus interface of the first processor to acquire the memory data sent by the first field programmable gate array, and then write the memory data into memory by using the first processor. The memory writing module is configured to acquire memory data returned by the second processor for the access request through a second field programmable gate array of the second OpenCAPI accelerator card; acquire the memory data sent by the second OpenCAPI accelerator card through the second connection by using a first field programmable gate array of the first OpenCAPI accelerator card; and write the memory data into memory by using an OpenCAPI bus interface of the first processor to acquire the memory data sent by the first field programmable gate array, and then write the memory data into memory by using the first processor. The memory writing module is configured to acquire memory data returned by the second processor for the access request through a second field programmable gate array of the second OpenCAPI accelerator card; acquire the memory data sent by the second OpenCAPI accelerator card through the second connection by using 4. A memory access system, characterized by, ​

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