An ATD circuit module with aging detection and self-destruct function

Abstract

This invention relates to an ATD circuit module with aging detection and self-destruction functions, belonging to the field of chip data security technology. The ATD circuit module is integrated inside an SRAM chip and includes an aging detection unit and an ATD logic unit. The aging detection unit outputs a self-destruct signal to the ATD logic unit after detecting that the chip has reached an aging threshold. The ATD logic unit contains an electronic fuse that blows upon receiving the self-destruct signal, completely disabling the ATD logic unit. This invention can permanently self-destruct the SRAM chip after detecting that its aging level has reached the aging threshold, improving the security of data within the SRAM.

Description

Technical Field

[0001] This invention belongs to the field of chip data security technology, and in particular relates to an ATD circuit module with aging detection and self-destruction functions. Background Technology

[0002] Currently, high-capacity SRAM chips use an ATD (Address Translate Detector) module as an "interface" control module, which is responsible for the SRAM's internal data writing and reading functions.

[0003] To protect data security and prevent unauthorized access to chip data, one approach is to have the SRAM chip cut off its power supply upon detecting unauthorized access, thus preventing attackers from stealing data. However, existing SRAM chip technology suffers from data retention issues. This means that information stored before power loss can be partially recovered through aging and imprinting. This is because when a memory cell in an SRAM array stores fixed data for a long period, the two symmetrical MOSFETs will experience varying degrees of BTI (Bias Temperature Instability) aging, resulting in a permanent threshold voltage mismatch. Consequently, upon power-up, there is a certain probability (approximately 10%–20%) of the initial power-up value being read as the opposite of the original stored value. User activity is thus inadvertently recorded at the physical level. Therefore, cutting off the SRAM power supply still poses a security risk of data being read out.

[0004] Another method to protect chip data security is to incorporate anti-attack detection and control circuitry and a self-built power supply unit into the SRAM chip. When the anti-attack detection and control circuitry detects a threat, it erases or rewrites the data in the SRAM. However, this method has drawbacks: the chip circuitry is more complex, with more control signals, and the use of an additional power supply unit results in higher area overhead and power consumption. Furthermore, the anti-attack detection and control circuitry loses its detection function after the SRAM has been idle for an extended period.

[0005] To prevent data from being illegally read from SRAM chips, there is currently another technology for hardening the chips to prevent aging and imprinting. This technology increases the number of transistors used in each memory cell. However, this also increases the number of signal ports on the SRAM chip, consuming a large amount of chip area and power, and increasing the chip manufacturing cost. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the present invention aims to provide an ATD circuit module with aging detection and self-destruction functions. Starting from the ATD module inside the SRAM chip, by providing an ATD circuit module with self-destruction function, the data security of the SRAM chip is improved, and at the same time the problems of high power consumption and high manufacturing cost of existing chips with security hardening functions are solved.

[0007] An ATD circuit module with aging detection and self-destruct functions includes: an aging detection unit and an ATD logic unit; wherein,

[0008] The aging detection unit outputs a self-destruct signal to the ATD logic unit after detecting that the chip has reached the aging threshold.

[0009] The ATD logic unit is used to generate an ATD digital pulse signal, which disables the ATD digital pulse signal after receiving the self-destruct signal.

[0010] Furthermore, the aging detection unit includes a buffer circuit and a comparator circuit; wherein,

[0011] The buffer circuit is used to detect the ATD digital pulse signal. When the captured ATD digital pulse signal is a high-level signal, the comparator of the comparator circuit is turned on, and when it is a low-level signal, the comparator is turned off.

[0012] The comparator circuit is used to compare the high-level signal and the aging threshold when the comparator is turned on. If the high-level signal of the ATD digital pulse signal is lower than the aging threshold, a high-level self-destruct signal is output.

[0013] Furthermore, the buffer circuit includes: a first inverter and a second inverter circuit connected in series; wherein,

[0014] The input terminal of the first inverter is connected to the ATD digital pulse signal, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the comparator circuit.

[0015] Furthermore, the comparator circuit includes: a switching MOSFET, a comparator, a first resistor, and a second resistor; wherein,

[0016] The first resistor and the second resistor are connected in series between the power supply terminal and the ground terminal. The connection terminal of the first resistor and the second resistor is electrically connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the input terminal of the first inverter and receives the ATD digital pulse signal. The ground terminal of the comparator is connected to the source of the switching MOSFET. The output terminal of the comparator is connected to the self-destruct signal line. The drain of the switching MOSFET is grounded. The gate of the switching MOSFET is connected to the output terminal of the second inverter.

[0017] Furthermore, the method of disabling the ATD digital pulse signal includes narrowing, eliminating, or fixing the pulse width of the ATD digital pulse signal.

[0018] Furthermore, the ATD logic unit includes an electronic fuse, a weak pull-up circuit, and an addressing circuit; wherein the electronic fuse is located between the weak pull-up circuit and the addressing circuit.

[0019] Furthermore, the weak pull-up circuit is a PMOS transistor circuit; the gate of the PMOS transistor is connected to the chip select signal, and the chip select signal is connected to the read / write logic control circuit inside the SRAM chip; the source of the PMOS transistor is connected to the power supply; and the drain of the PMOS transistor is connected to the first terminal of the electronic fuse.

[0020] Furthermore, the addressing circuit is a plurality of NMOS transistor circuits; the plurality of NMOS transistors are connected in series between the power ground and the second terminal of the electronic fuse; the gates of the plurality of NMOS transistors are respectively connected to the address signal lines inside the SRAM chip.

[0021] Furthermore, the electronic fuse also has a third terminal for receiving the high-voltage signal.

[0022] Furthermore, an SRAM chip includes an ATD circuit module with aging detection and self-destruct functions.

[0023] The beneficial effects of this invention are as follows:

[0024] This invention incorporates an ATD circuit module with a self-destruct function within the chip. By detecting the attenuation level of the ATD digital pulse signal in the ATD circuit module, the aging level of the SRAM chip's BTI is determined. When the aging level reaches the aging threshold, the signal of the ATD circuit is shut down, and the "interface" of the chip's internal storage array is automatically destroyed, causing the chip to lose its read / write function and making it impossible to read data from the chip, thus improving the overall security of the SRAM chip. This invention has a simple structure and a permanent data destruction function, while also solving the problems of high power consumption and high chip manufacturing cost of traditional SRAM chips with security hardening functions. Attached Figure Description

[0025] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. It is obvious that the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings.

[0026] Figure 1 This is a structural diagram of an ATD circuit module with aging detection and self-destruct functions provided in one embodiment of the present invention;

[0027] Figure 2 A schematic diagram of the aging detection unit of an ATD circuit module with aging detection and self-destruction functions provided in an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of the ATD logic unit of an ATD circuit module with aging detection and self-destruction functions provided in an embodiment of the present invention;

[0029] Figure 4 A timing diagram of an ATD circuit module with aging detection and self-destruction functions provided in an embodiment of the present invention when the aging threshold is reached;

[0030] Figure 5 The schematic diagram of an SRAM chip containing an ATD circuit module with aging detection and self-destruction functions is provided for one embodiment of the present invention.

[0031] Figure Labels

[0032] 1. Aging detection unit; 2. ATD logic unit. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of the present invention to describe the principles of the present invention. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention should fall within the protection scope of the present invention.

[0034] Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts disclosed in this invention. Unless otherwise specified, the following embodiments and features described herein can be combined with each other.

[0035] Invention Embodiments

[0036] Traditional SRAM chips (Static Random Access Memory) adopt a globally static design approach, where operations on the memory are initiated by control signals such as address transitions. No other dedicated control unit is required. As a result, any transition of any input signal, such as data or address bus, will pass through subsequent circuits in sequence. Therefore, the fully static circuit implementation approach will result in a large area and power consumption when designing large-capacity SRAMs.

[0037] The high-capacity SRAM chip uses an ATD (Address Translate Detector) module as an "interface" control module, which is responsible for the SRAM's internal data writing and reading functions.

[0038] The working principle of the ATD module is as follows: When the external input control signal of the SRAM chip, such as the chip select / read / write enable signal or the address signal, changes, the ATD module inside the SRAM chip will be triggered to generate an ATD digital pulse signal. This pulse signal controls the sensitive amplifier and other modules inside the SRAM to complete the read and write functions of the SRAM memory cell array. Therefore, it does not need to wait for the synchronous clock signal, which greatly improves the working speed of the circuit and realizes the asynchronous working mode of the SRAM chip.

[0039] A specific embodiment of the present invention discloses an ATD circuit module with aging detection and self-destruction functions. The ATD circuit module can lose its data interface function after detecting that the circuit transistor has reached the aging threshold, and the SRAM chip will be unable to perform normal data read and write operations, thus becoming permanently invalid.

[0040] Figure 1 This is a structural diagram of the ATD circuit module with aging detection and self-destruct functions provided in this embodiment.

[0041] like Figure 1 As shown, an ATD circuit module with aging detection and self-destruction functions is disclosed. The ATD circuit module includes an aging detection unit 1 and an ATD logic unit 2.

[0042] The aging detection unit 1 is used to detect the voltage of the ATD digital pulse signal output by the ATD logic unit 2 and control the output of a self-destruct signal. When the aging detection unit 1 detects that the ATD digital pulse signal is lower than the aging threshold voltage when it is at a high level, it outputs a high-level self-destruct signal to the ATD logic unit 2. When the chip's aging degree is small, the ATD digital pulse signal is not lower than the aging threshold voltage when it is at a high level, and the aging detection unit 1 keeps the self-destruct signal at a low level.

[0043] The aging detection unit 1 includes a buffer circuit and a comparator circuit. Figure 2 This is a schematic diagram of the aging detection unit of an ATD circuit module with aging detection and self-destruction functions.

[0044] like Figure 2 As shown, the buffer circuit includes a first inverter and a second inverter circuit connected in series. The input terminal of the first inverter is connected to the ATD digital pulse signal, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate of the switching MOS transistor.

[0045] The buffer circuit is used to detect the ATD digital pulse signal. When a high-level signal is detected, the comparator of the comparator circuit is turned on, and when a low-level signal is detected, the comparator is turned off.

[0046] The comparator circuit includes a switching MOSFET, a comparator, a first resistor, and a second resistor. The first and second resistors form a voltage divider circuit, dividing the voltage to produce a threshold voltage which is input to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the ATD digital pulse signal. The ground terminal of the comparator is connected to the source of the switching MOSFET. The output terminal of the comparator is connected to the self-destruct signal line. The drain of the switching MOSFET is grounded. The gate of the switching MOSFET is connected to the output terminal of the second inverter.

[0047] The comparator circuit is used to compare whether the high level of the ATD digital pulse signal is lower than the threshold voltage when the comparator is turned on. If the high level of the ATD digital pulse signal is lower than the threshold voltage, the self-destruct signal becomes high; otherwise, the self-destruct signal remains low.

[0048] The threshold voltage is the chip's aging threshold, which characterizes the degree of chip aging and is determined by chip aging experiments or the chip's usage cycle.

[0049] The ATD logic unit 2 includes an electronic fuse, a weak pull-up circuit, and an addressing circuit, which are used to control the read and write operations of the SRAM. It can also blow the internal efuse electronic fuse after receiving a self-destruct signal from the aging detection unit, so that the ATD circuit module completely loses its working capability.

[0050] More specifically, the electronic fuse is an efuse electronic fuse that presents a low-resistance state under normal operating conditions. When it receives a high-voltage or high-current density signal, the fuse melts and presents a high-resistance state, and the original circuit becomes an open circuit.

[0051] Figure 3 The schematic diagram of the ATD logic unit circuit of the ATD circuit module with aging detection and self-destruction functions provided in this embodiment.

[0052] like Figure 3As shown, the ATD logic unit includes one efuse electronic fuse, n NMOS transistors and one PMOS transistor, where n is the number of address signal lines of the SRAM chip.

[0053] More specifically, the weak pull-up circuit is a PMOS transistor circuit. The gate of the PMOS transistor is connected to the chip select signal, which is connected to the read / write logic control circuit inside the SRAM chip. The source of the PMOS transistor is connected to the power supply, and the drain is connected to the first terminal of the electronic fuse.

[0054] like Figure 3 As shown, the addressing circuit consists of n NMOS transistor circuits.

[0055] More specifically, n NMOS transistors are connected in series between the power ground and the second terminal of the electronic fuse. The gates of the n NMOS transistors are respectively connected to the address signal lines inside the SRAM chip. Under normal operating conditions, the address signal bus generates ATD digital pulse signals through the n NMOS transistors, which are used to drive the sensitive amplifier and precharge module in the SRAM chip.

[0056] Under normal circumstances, by controlling the address signal bus and chip select signal, the on / off state of NMOS and PMOS can be controlled, thereby enabling the ATD logic unit to controllably output ATD digital pulse signals.

[0057] like Figure 3 As shown, the efuse electronic fuse is connected to the drain of the PMOS and the source of the last-stage NMOS, respectively, with the high-voltage terminal connected to the self-destruct signal from the aging detection unit. When the efuse electronic fuse receives the self-destruct signal from the aging detection unit, it melts and creates an open circuit in the current path, causing the pulse width of the ATD digital pulse signal output by the ATD logic unit to narrow, disappear, or become a fixed level. After the ATD logic unit fails, the SRAM chip fails because it cannot read or write data normally.

[0058] Figure 5 The schematic diagram of the SRAM chip containing an ATD circuit module with aging detection and self-destruction functions is provided for this embodiment.

[0059] like Figure 5 As shown, the SRAM chip mainly includes a read / write logic control module, a sensitive amplifier, an address signal bus, a data input / output port, a row decoder, a column decoder, an SRAM memory cell array, a precharge module, and an ATD circuit module.

[0060] More specifically:

[0061] The read / write logic control module is electrically connected to the data input / output port and also electrically connected to the chip select signal input of the SRAM chip.

[0062] The data input / output ports are electrically connected to the read / write logic control module and the sensitive amplifier, respectively, and are also electrically connected to the data signal input terminal of the SRAM chip;

[0063] The sensitive amplifier is electrically connected to the data input / output port and the column decoder, respectively.

[0064] The column decoder is electrically connected to the address signal bus, the sensitive amplifier, and the SRAM memory cell array, respectively.

[0065] The address signal bus is electrically connected to the column decoder and the row decoder, respectively, and is also electrically connected to the address signal input terminal of the SRAM chip;

[0066] The row decoder is electrically connected to the address signal bus and the SRAM memory cell array, respectively.

[0067] The SRAM memory cell array is electrically connected to the precharge module, column decoder, and row decoder, respectively.

[0068] The ATD circuit module is integrated inside the SRAM chip, wherein:

[0069] In the ATD circuit module, the chip select signal terminal of the ATD logic unit is electrically connected to the read / write logic control module inside the SRAM chip and is controlled by the chip select signal input terminal of the SRAM chip.

[0070] In the ATD circuit module, the address signal terminal of the ATD logic unit is electrically connected to the address signal bus of the SRAM chip and is controlled by the address signal input terminal of the SRAM chip.

[0071] In the ATD circuit module, the ATD digital pulse signal terminal of the ATD logic unit is electrically connected to the precharge module and the sensitive amplifier in the chip, respectively. When the ATD digital pulse signal terminal normally emits a digital pulse signal, it can control the precharge module and the sensitive amplifier to work normally, thereby enabling data read and write operations on the SRAM chip.

[0072] Taking the chip reaching its aging threshold as an example, combined with Figure 4 The timing diagram shown illustrates the operation and timing of the ATD circuit module in this embodiment. Figure 4 This is a timing diagram of the ATD circuit module with aging detection and self-destruct functions provided in this embodiment when it reaches the aging threshold. Figure 4As shown, when the aging detection unit detects that the voltage of the ATD digital pulse signal at a high level is lower than the threshold voltage, the aging detection unit changes the self-destruct signal from low level to high level and outputs it to the ATD logic unit. This causes the high-voltage terminal of the efuse electronic fuse inside the ATD logic unit to be loaded with a high level. After a certain fusing time, the efuse electronic fuse blows. After that, the ATD digital pulse signal continues to output a low level. The sensitive amplifier and precharge module in the SRAM chip fail and cannot be read normally. The SRAM completes its self-destruction.

[0073] This invention provides an ATD circuit module with aging detection and self-destruction functions. Starting from the ATD module inside the SRAM chip, by providing an ATD security module with self-destruction function, the data security of the SRAM chip is greatly improved. At the same time, it has a simple structure and a function of permanent data destruction, which solves the problems of high power consumption and high manufacturing cost of existing chips with security hardening functions.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. An ATD circuit module with aging detection and self-destruction functions, characterized in that, include: Aging detection unit and ATD logic unit; among which, The aging detection unit outputs a self-destruct signal to the ATD logic unit after detecting that the chip has reached the aging threshold. The ATD logic unit is used to generate an ATD digital pulse signal, which disables the ATD digital pulse signal upon receiving the self-destruct signal. The ATD logic unit includes an electronic fuse, a weak pull-up circuit, and an addressing circuit. The electronic fuse is located between the weak pull-up circuit and the addressing circuit. The weak pull-up circuit is connected to the first terminal of the electronic fuse. The addressing circuit is a plurality of NMOS transistor circuits. The plurality of NMOS transistors are connected in series between the power ground and the second terminal of the electronic fuse. The gates of the plurality of NMOS transistors are respectively connected to the address signal lines inside the SRAM chip.

2. An ATD circuit module with aging detection and self-destruction functions according to claim 1, characterized in that, The aging detection unit includes a buffer circuit and a comparator circuit; wherein... The buffer circuit is used to detect the ATD digital pulse signal. When the captured ATD digital pulse signal is a high-level signal, the comparator of the comparator circuit is turned on, and when it is a low-level signal, the comparator is turned off. The comparator circuit is used to compare the high-level signal and the aging threshold when the comparator is turned on. If the high-level signal of the ATD digital pulse signal is lower than the aging threshold, a high-level self-destruct signal is output.

3. An ATD circuit module with aging detection and self-destruction functions according to claim 2, characterized in that, The buffer circuit includes: a first inverter and a second inverter circuit connected in series; wherein... The input terminal of the first inverter is connected to the ATD digital pulse signal, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the comparator circuit.

4. An ATD circuit module with aging detection and self-destruction functions according to claim 3, characterized in that, The comparator circuit includes: a switching MOSFET, a comparator, a first resistor, and a second resistor; wherein... The first resistor and the second resistor are connected in series between the power supply terminal and the ground terminal. The connection terminal of the first resistor and the second resistor is electrically connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the input terminal of the first inverter and receives the ATD digital pulse signal. The ground terminal of the comparator is connected to the source of the switching MOSFET. The output terminal of the comparator is connected to the self-destruct signal line. The drain of the switching MOSFET is grounded. The gate of the switching MOSFET is connected to the output terminal of the second inverter.

5. An ATD circuit module with aging detection and self-destruction functions according to claim 1, characterized in that, Disabling the ATD digital pulse signal includes narrowing the pulse width, eliminating the pulse width, or setting it to a fixed level.

6. An ATD circuit module with aging detection and self-destruction functions according to claim 5, characterized in that, The weak pull-up circuit is a PMOS transistor circuit; the gate of the PMOS transistor is connected to the chip select signal, and the chip select signal is connected to the read / write logic control circuit inside the SRAM chip; the source of the PMOS transistor is connected to the power supply; and the drain of the PMOS transistor is connected to the first terminal of the electronic fuse.

7. An ATD circuit module with aging detection and self-destruction functions according to claim 6, characterized in that, The electronic fuse also has a third terminal for receiving high-voltage signals.

8. An SRAM chip containing an ATD circuit module with aging detection and self-destruction functions as described in any one of claims 1-7.

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