A method, device, equipment and medium for establishing an improved impedance arc model

Abstract

The application provides a method and device for establishing an improved impedance arc model, equipment and a medium thereof, including establishing an arc model equivalent circuit on the basis of a Cassie model; under a power frequency condition of the equivalent circuit, the equivalent circuit is expressed as an impedance function with a 10 ms period, an equivalent time-varying conductance when the arc is stably burning, and an equivalent time-varying impedance containing LC and RC oscillation when the arc is extinguished and reignited; the arc resistance dynamic expression is obtained by differentiating the Cassie model equation; when the arc current is close to the natural zero, the initial value of the arc conductance is obtained according to the dynamic expression and the instantaneous current is ignored; when the arc is stably burning, the arc resistance is equivalent to a time-varying conductance, and the maximum conductance value of the arc is obtained according to the total impedance of the load; the arc impedance Z_a expression is obtained according to the initial conductance value and the maximum conductance value, and the improved impedance arc model is generated. The traditional Cassie and Mayr models do not consider the near-pole effect, corona discharge and other phenomena, and the arc is equivalent to a single time-varying resistance, so that the fault arc cannot be accurately described in the actual situation.

Description

Technical Field

[0001] The present invention relates to the field of fault arcs, and in particular to a method, device, equipment and medium for establishing an improved impedance arc model. Background Art

[0002] With the development of the national economy and the continuous improvement of people's living standards, the use of various electrical appliances is becoming increasingly widespread, and electricity consumption is showing an upward trend year by year. This has led to increasingly stringent requirements for electrical safety, load device stability, and power line reliability. According to data released by the Fire Department of the Ministry of Public Security of China, from 2010 to 2019, a total of 786,200 electrical fires occurred nationwide, accounting for 32.4% of the total number of fires in history and ranking first among all known fire causes. Arc faults generated by low-voltage distribution lines can produce high temperatures, arcs, sparks, and non-fault-induced energy release, and are the primary cause of electrical fires. In certain situations in low-voltage distribution systems, the normal operating current of an appliance and the arc fault current waveform are very similar, making them difficult to distinguish. Therefore, accurately analyzing the characteristics of arc faults is of great significance.

[0003] Early research on arc faults relied primarily on experiments, but accurate interpretation of experimental phenomena and results was difficult, making arc fault model simulation a crucial method for studying their characteristics. Arc models treat the arc as a cylindrical gas channel based on energy balance, where the conductance varies with energy. In the early 20th century, foreign researchers proposed the Mayr and Cassie models, respectively, based on energy balance theory, using convection and conduction heat dissipation as the starting point. Both models are classic mathematical arc models. These models incorporate two parameters: the arc time constant and arc heat dissipation power, which require extensive testing under various operating conditions to determine. Among them, the Mayr model mainly reflects the fault characteristics after the arc current passes through zero, while the Cassie model mainly reflects the fault characteristics before the arc current passes through zero. In order to avoid the hazards of the fault arc, the fault characteristics before zero crossing play a key role in the early prediction of the arc fault. Therefore, it is necessary to improve the Cassie model; and the existing arc model is mainly improved based on the Mayr model, which can simulate the arc current waveform under resistive load and resistive-inductive load, but has certain limitations in the arc current zero-rest time, the current change rate before and after zero crossing, and the fault characteristics of high-frequency and low-frequency oscillations; and the traditional Cassie and Mayr models do not consider the near-pole effect, corona discharge and other phenomena, and the arc is equivalent to a single time-varying resistor. In actual situations, it is impossible to accurately describe the characteristics of the fault arc by using only a single time-varying resistor equivalent.

[0004] In view of this, this application is filed. Summary of the Invention

[0005] The present invention discloses a method, device, equipment and medium for establishing an improved impedance arc model, aiming to solve the problem that the existing arc model is mainly improved based on the Mayr model, which can simulate the arc current waveform under resistive load and inductive load, but has certain limitations in the arc current zero-rest time, the current change rate before and after zero crossing, and the fault characteristics of high-frequency and low-frequency oscillations; and the traditional Cassie and Mayr models do not consider phenomena such as near-pole effects and corona discharges, and equate the arc to a single time-varying resistor. However, in actual situations, the characteristics of the fault arc cannot be accurately described by using only a single time-varying resistor.

[0006] A first embodiment of the present invention provides a method for establishing an improved impedance arc model, comprising:

[0007] Based on the Cassie model, an equivalent circuit of the arc model is established. In this equivalent circuit, under power frequency conditions, it is expressed as an impedance function with a period of 10ms. The arc is equivalent to a time-varying conductance during stable burning and a time-varying impedance containing LC oscillations and RC oscillations during arc extinction and re-strike.

[0008] Differentiate the Cassie arc model equation and solve it to obtain the dynamic expression of arc resistance;

[0009] When the arc current approaches the natural zero crossing, the initial value of the arc conductance is obtained according to the dynamic expression while ignoring the instantaneous arc current;

[0010] When the arc is burning stably, the arc resistance is equivalent to a time-varying conductance. According to the total impedance of the load, the maximum arc conductance value in the arc extinction and reignition interval is obtained;

[0011] According to the arc conductance initial value and the arc maximum conductance value, an expression of arc impedance Z_a is obtained to generate an improved impedance arc model.

[0012] Preferably, the equivalent circuit of the arc model includes a current source, a time-varying conductance equivalent circuit, a time-varying impedance equivalent circuit and an ideal switch, wherein the current source is connected in series with the time-varying conductance equivalent circuit, and the time-varying conductance equivalent circuit is connected in parallel with the time-varying impedance equivalent circuit through the ideal switch.

[0013] Preferably, the time-varying conductivity equivalent circuit includes a resistive-inductive load, a first capacitor, and an arc resistor, wherein the resistive-inductive load is connected in parallel with the first capacitor and then in series with the arc resistor, one end of the current source is electrically connected to one end of the resistive-inductive load, and the other end of the resistive-inductive load is respectively electrically connected to one end of the arc resistor, one end of the ideal switch, and one end of the first capacitor, the other end of the ideal switch and the other end of the arc resistor are both electrically connected to the time-varying impedance equivalent circuit, and the other end of the arc resistor and the other end of the first capacitor are both electrically connected to the other end of the current source.

[0014] Preferably, the time-varying impedance equivalent circuit includes a resistor, a second capacitor, an inductor, and a third capacitor, the resistor is connected in series with the second capacitor, the inductor is connected in series with the third capacitor, the resistor and the second capacitor are connected in parallel with the inductor and the third capacitor, the other end of the ideal switch is electrically connected to one end of the resistor and one end of the inductor, the other end of the resistor is electrically connected to one end of the second capacitor, the other end of the inductor is electrically connected to one end of the third capacitor, and the other end of the second capacitor and the other end of the third capacitor are both electrically connected to the other end of the arc resistor.

[0015] Preferably, the arc impedance Z_a is expressed as follows:

[0016]

[0017] Where G a is the maximum arc conductivity value between arc extinction and reignition, G0 is the initial value of arc conductivity, C a is the first capacitor, L a For resistive inductive load, R RC is the resistance, C RC is the second capacitor, L LC Inductor, C LC is the third capacitor, C1 is the RC oscillation value in the time-varying impedance equivalent circuit, C2 is the LC oscillation value in the time-varying impedance equivalent circuit, θ is the arc time constant, and the interval (t A ,t B ) and interval (t D ,t E ) is the arc stable burning range, and the range (t B ,t C ) is the arc extinction interval, interval (t C ,t D ) is the arc restrike interval.

[0018] Preferably, after obtaining an expression of arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model, the method further includes:

[0019] An improved impedance arc equivalent circuit simulation model corresponding to the expression of arc impedance Z_a was built through Matlab;

[0020] The improved impedance arc model is analyzed and verified using the improved impedance arc equivalent circuit simulation model.

[0021] Preferably, the improved impedance arc model is verified for accuracy using an improved impedance arc equivalent circuit simulation model, specifically as follows:

[0022] Obtain the improved impedance arc equivalent circuit simulation model in Matlab and simulate the input to obtain the simulated output voltage;

[0023] The simulated output current is compared with the output current of the traditional Cassie model to analyze and verify the improved impedance arc model.

[0024] A second embodiment of the present invention provides an improved device for establishing an impedance arc model, comprising:

[0025] An equivalent circuit establishment unit is used to establish an equivalent circuit of the arc model based on the Cassie model; wherein, in the equivalent circuit, under power frequency conditions, it is expressed as an impedance function with a period of 10ms, the arc is equivalent to a time-varying conductance during stable burning, and is equivalent to a time-varying impedance containing LC oscillation and RC oscillation during arc extinction and re-strike;

[0026] A dynamic expression acquisition unit is used to differentiate the Cassie arc model equation and solve it to obtain a dynamic expression of arc resistance;

[0027] an arc conductance initial value calculation unit, configured to obtain an arc conductance initial value according to the dynamic expression while ignoring the arc instantaneous current when the arc current approaches a natural zero crossing;

[0028] The arc maximum conductance value calculation unit is used to obtain the arc maximum conductance value in the arc extinction and reignition interval according to the total impedance of the load when the arc is burning stably and the arc resistance is equivalent to a time-varying conductance;

[0029] The improved impedance arc model generating unit is used to obtain an expression of arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model.

[0030] A third embodiment of the present invention provides a device for establishing an improved impedance arc model, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the method for establishing the improved impedance arc model as described in any one of the above.

[0031] A fourth embodiment of the present invention provides a readable storage medium storing a computer program, wherein the computer program can be executed by a processor of a device where the storage medium is located to implement the method for establishing an improved impedance arc model as described in any one of the above.

[0032] In summary, the present embodiment provides a method, apparatus, device, and medium for establishing an improved impedance arc model. The improved impedance arc model is an impedance arc model proposed on the basis of the traditional Cassie model, which is expressed as an impedance function with a period of 10 ms. The improved impedance arc model equates the arc to a time-varying conductance during stable burning, and to a time-varying impedance containing RL oscillations and RC oscillations during arc extinction and re-ignition. This solves the problem that the existing arc model is mainly improved based on the Mayr model and can simulate the arc current waveform under resistive loads and inductive loads, but has certain limitations in the arc current zero-rest time, the current change rate before and after zero crossing, and the fault characteristics of high-frequency and low-frequency oscillations. In addition, the traditional Cassie and Mayr models do not consider phenomena such as near-pole effects and corona discharges, and equate the arc to a single time-varying resistance. However, in actual situations, the characteristics of the fault arc cannot be accurately described by using only a single time-varying resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flow chart of a method for establishing an improved impedance arc model provided by the present invention.

[0034] Figure 2 It is a schematic diagram of an equivalent circuit of an improved impedance arc model provided by the present invention for establishing an improved impedance arc model.

[0035] Figure 3 It is a schematic diagram of the physical process of arc power generation of an improved impedance arc model provided by the present invention, in which a method for establishing an improved impedance arc model is provided.

[0036] Figure 4 The present invention provides an improved impedance arc model establishment method, which is an equivalent circuit diagram of an improved impedance arc model when the arc is stably burning.

[0037] Figure 5 The present invention provides an improved impedance arc model establishment method, which is an equivalent circuit diagram of an improved impedance arc model when the arc is extinguished and reignited.

[0038] Figure 6 is an arc fault circuit simulation schematic diagram of an improved impedance arc equivalent circuit simulation model of an improved impedance arc model establishment method provided by the application.

[0039] Figure 7 is a simulation schematic diagram of an improved impedance arc model establishment method provided by the application.

[0040] Figure 8 is a simulation waveform comparison schematic diagram of an improved impedance arc model when the load of the improved impedance arc model is a resistive load.

[0041] Figure 9 is a simulation waveform comparison schematic diagram of an improved impedance arc model when the load of the improved impedance arc model is a resistive and inductive load.

[0042] Figure 10 is an arc current zero-hibernation time schematic diagram of a traditional Cassie model when the load of an improved impedance arc model is a resistive load.

[0043] Figure 11 is an arc current zero-hibernation time schematic diagram of an improved impedance arc model when the load of an improved impedance arc model is a resistive load.

[0044] Figure 12 is an arc current zero-hibernation time schematic diagram of a traditional Cassie model when the load of an improved impedance arc model is a resistive and inductive load.

[0045] Figure 13 is an arc current zero-hibernation time schematic diagram of an improved impedance arc model when the load of an improved impedance arc model is a resistive and inductive load.

[0046] Figure 14 is an arc current change rate comparison schematic diagram of an improved impedance arc model under a resistive load.

[0047] Figure 15 is an arc current wavelet decomposition low-frequency part schematic diagram of a traditional Cassie model under a resistive and inductive load of an improved impedance arc model.

[0048] Figure 16is an improved impedance arc model under the inductive load of the improved impedance arc model of the improved impedance arc model establishment method provided by the application. The schematic diagram of the low-frequency part of each layer of the arc current wavelet decomposition of the improved impedance arc model under the inductive load of the improved impedance arc model.

[0049] Figure 17 is a schematic diagram of the high-frequency part of each layer of the arc current wavelet decomposition of the traditional Cassie model under the inductive load of the improved impedance arc model of the improved impedance arc model establishment method provided by the application.

[0050] Figure 18 is a schematic diagram of the high-frequency part of each layer of the arc current wavelet decomposition of the improved impedance arc model under the inductive load of the improved impedance arc model of the improved impedance arc model establishment method provided by the application.

[0051] Figure 19 is a module of the improved impedance arc model establishment device provided by the application. DETAILED DESCRIPTION

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in connection with the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application. Therefore, the following detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0053] The specific embodiments of the application are described in detail below in connection with the drawings.

[0054] Please refer to Figure 1 The first embodiment of the application provides an improved impedance arc model establishment method, comprising:

[0055] S101, on the basis of the Cassie model, an equivalent circuit of the arc model is established; wherein in the equivalent circuit, under the power frequency condition, it is expressed as an impedance function with a period of 10 ms, the arc is equivalent to a time-varying conductance during stable combustion, and is equivalent to a time-varying impedance containing LC oscillation and RC oscillation during arc extinction and re-arc.

[0056] Please refer to Figure 2Specifically, in this embodiment, the equivalent circuit of the arc model includes a current source E0, a time-varying conductance equivalent circuit, a time-varying impedance equivalent circuit and an ideal switch K, wherein the current source E0 is connected in series with the time-varying conductance equivalent circuit, and the time-varying conductance equivalent circuit is connected in parallel with the time-varying impedance equivalent circuit through the ideal switch K.

[0057] In this embodiment, the time-varying conductance equivalent circuit includes a resistive-inductive load Load, a first capacitor C a , and arc resistance G, wherein the resistive-inductive load Load and the first capacitor C a After being connected in parallel, it is connected in series with the arc resistor G. One end of the current source E0 is electrically connected to one end of the resistive-inductive load Load. The other end of the resistive-inductive load Load is respectively connected to one end of the arc resistor G, one end of the ideal switch K, and the first capacitor C. a One end of the ideal switch K is electrically connected to the other end of the arc resistor G, and the other end of the arc resistor G is electrically connected to the time-varying impedance equivalent circuit. The other end of the arc resistor G and the first capacitor C a The other end of each is electrically connected to the other end of the current source E0.

[0058] In this embodiment, the time-varying impedance equivalent circuit includes a resistor R RC , the second capacitor C RC 、Inductor L LC , and a third capacitor C LC , the resistor R RC With the second capacitor C RC In series, the inductor L LC With the third capacitor C LC In series, the resistor R RC and the second capacitor C RC With the inductor L LC and the third capacitor C LC In parallel, the other end of the ideal switch K is connected to the resistor R RC One end of the inductor L LC One end of the resistor R is electrically connected to RC The other end of the second capacitor C RC One end of the inductor is electrically connected to LC The other end of the third capacitor C LC One end of the second capacitor C is electrically connected to RC The other end of the third capacitor C LC The other end of each is electrically connected to the other end of the arc resistor G.

[0059] Specifically, in this embodiment, since the arc resistance is a nonlinear time-varying resistance, the resistance model of a fixed resistor cannot be used to calculate the dynamic characteristics of the arc. The improved impedance arc model is expressed as an impedance function with a period of 10ms. The arc is equivalent to a time-varying conductance during stable combustion and a time-varying impedance containing LC oscillations and RC oscillations during arc extinction and re-strike. According to the physical process of arc discharge, each cycle can be divided into four processes: stable arc combustion - arc extinction - arc re-ignition - stable arc combustion, as shown in Figure 2. Figure 3 As shown in the figure: AB and DE areas belong to the arc stable burning process, and the arc resistance changes are relatively small and tend to be stable, while BC and CD areas belong to the arc extinction and arc reignition process, and the arc resistance shows instantaneous changes, corresponding to the "flat shoulder" period of the arc current zero rest stage. At this time, the change rate of the arc voltage and arc resistance is large.

[0060] Specifically, in this embodiment, in order to prevent the harm caused by arc faults in low-voltage power distribution systems, it is of great significance to accurately analyze their characteristics. To address the errors in the traditional arc model in the arc current zero-off period, the current change rate before and after zero crossing, and the fault characteristics of high-frequency and low-frequency oscillations, an improved impedance arc model is proposed based on the traditional Cassie model. The arc is equivalent to a time-varying conductance during the stable burning period and a time-varying impedance containing RL and RC oscillations during the arc extinction and re-strike periods. This solves the problem that existing arc models are mainly based on the Mayr model and can simulate arc current waveforms under resistive and inductive loads, but have certain limitations in the arc current zero-off period, the current change rate before and after zero crossing, and the fault characteristics of high-frequency and low-frequency oscillations. In addition, the traditional Cassie and Mayr models do not consider phenomena such as the near-pole effect and corona discharge, and equate the arc to a single time-varying resistance. In reality, using only a single time-varying resistance as an equivalent cannot accurately describe the characteristics of the fault arc.

[0061] S102, differentiating the Cassie arc model equation and solving it to obtain a dynamic expression for the arc resistance;

[0062] The arc model treats the arc as a cylindrical gas channel based on energy balance. Its conductivity changes with energy. The arc releases energy to the surrounding medium through heat conduction, convection, and radiation. Therefore, the arc resistance is actually determined by the energy input and output of the arc and is related to time. The general form of the dynamic arc model equation of the traditional fault arc mathematical model is: Where: G a is the instantaneous value of arc conductance per unit length, i a is the instantaneous value of the arc current, E is the instantaneous value of the arc column voltage gradient, R ais the instantaneous value of arc resistance per unit length, P is the input power per unit length of arc, P = Ei a , N is the power dissipated per unit length of arc, t is time, and Q is the energy accumulated per unit length of arc. After calculation and simplification, equation (1) can be obtained as the differential equation of the dynamic arc model of the traditional fault arc mathematical model: The Cassie model assumes that the arc has the shape of a cylindrical gas channel with clear boundaries. Its cross section has a uniformly distributed temperature, and the temperature is constant in space and time, but the diameter is variable. Based on the energy balance theory of the arc gap, it is assumed that the arc voltage gradient is constant, the energy dissipation rate is proportional to the change in the arc column cross section, and the energy dissipation is mainly due to heat convection. The Cassie arc model equation is derived from formula (2): Where: θ is the arc time constant; E0 is the arc voltage gradient.

[0063] The traditional Mayr model also assumes that the arc has the form of a cylindrical gas channel, but its diameter is constant. The arc temperature is related to the radial distance from the arc axis and time. Based on the arc gap dielectric strength recovery theory, it is assumed that the power dissipated by the arc is constant and the energy dissipation depends on heat conduction and radial diffusion. The Mayr arc model equation is derived from formula (2): Where: θ is the arc time constant; N0 is the arc power dissipation.

[0064] As can be seen from the above, different dynamic equations are derived from Equation (2) under different assumptions of the Cassie model and the Mayr model. The traditional Cassie model and the traditional Mayr model do not consider phenomena such as the near-pole effect and corona discharge, and the arc is equivalent to a single time-varying resistor. In reality, the arc current has a clear zero-rest phase, and the arc current has a large rate of change before and after zero crossing under resistive loads. High-frequency and low-frequency oscillations occur when the arc current crosses zero under inductive loads. The reason is that the current signal in the fault circuit is closely related to the arc resistance and circuit parameters. The changes in the dielectric strength and deionization degree in the transition zone between the last arc extinction and the next arcing are extremely complex, and there are complex phenomena such as the near-pole effect and corona discharge. It is impossible to accurately describe the characteristics of the fault arc by using only a single time-varying resistor equivalent.

[0065] Specifically, in this embodiment, equation (3) is rewritten as a linear differential equation: Where: i a (t) is the instantaneous arc current; E0 is the arc voltage gradient. Solving equation (5) yields the dynamic expression of arc resistance:

[0066] S103, when the arc current approaches a natural zero crossing, ignoring the instantaneous arc current according to the dynamic expression, obtaining an initial value of the arc conductance;

[0067] Specifically, in this embodiment, when the arc current is close to the natural zero crossing, the arc resistance is quite large, showing a high resistance state, and the arc voltage determines the circuit, so the arc instantaneous current i can be ignored. a (t), formula (6) can be simplified as: Where: G0 is the initial value of arc conductance. Among them I m is the maximum value of the arc current, which can be transformed into formula (6): From formula (8), we can know the initial value of arc conductance:

[0068] S104, when the arc is burning stably, the arc resistance is equivalent to a time-varying conductance, and the maximum arc conductance value in the arc extinction and reignition intervals is obtained based on the total impedance of the load;

[0069] Specifically, in this embodiment, when the arc is burning stably, the arc resistance during this period is equivalent to the time-varying conductance, and the equivalent circuit is as follows: Figure 4 As shown; Since the arc resistance is related to the total load impedance, if the total impedance is Z=R+jX, X>0, the maximum arc conductance value G in the arc extinction and reignition zone is M : During the arc extinction and arc reignition period, the arc current will experience high-frequency and low-frequency oscillations. Therefore, the arc resistance during this period is equivalent to a time-varying impedance containing LC oscillations and RC oscillations. The equivalent circuit is as follows: Figure 5 shown.

[0070] S105 , obtaining an expression for arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value, so as to generate an improved impedance arc model.

[0071] Specifically, in this embodiment, according to the above derivation, the arc impedance Z_a is expressed as follows:

[0072]

[0073] Where G a is the maximum arc conductivity value between arc extinction and reignition, G0 is the initial value of arc conductivity, C a is the first capacitor, L a For resistive inductive load, R RC is the resistance, C RC is the second capacitor, L LC Inductor, C LC is the third capacitor, C1 is the RC oscillation value in the time-varying impedance equivalent circuit, C2 is the LC oscillation value in the time-varying impedance equivalent circuit, θ is the arc time constant, and the interval (t A ,t B) and interval (t D ,t E ) is the arc stable burning range, and the range (t B ,t C ) is the arc extinction interval, interval (t C ,t D ) is the arc restrike interval.

[0074] Specifically, in this embodiment, formula (11) is an improved impedance arc model. Considering the characteristics of the actual arc current, such as the obvious zero-rest stage, the large current change rate before and after zero crossing, and the existence of high-frequency and low-frequency oscillations, the arc is equivalent to a time-varying resistance during the stable burning period, and is equivalent to a time-varying impedance containing LC oscillations and RC oscillations during the arc extinction and re-ignition periods. This formula can effectively and completely describe the arc characteristics.

[0075] In a possible embodiment of the present invention, after obtaining an expression for arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model, the method further includes:

[0076] An improved impedance arc equivalent circuit simulation model corresponding to the expression of arc impedance Z_a was built through Matlab;

[0077] The improved impedance arc model is analyzed and verified using the improved impedance arc equivalent circuit simulation model.

[0078] In this embodiment, the improved impedance arc equivalent circuit simulation model is used to verify the accuracy of the improved impedance arc model, specifically:

[0079] Obtain the improved impedance arc equivalent circuit simulation model in Matlab and simulate the input to obtain the simulated output voltage;

[0080] The simulated output current is compared with the output current of the traditional Cassie model to analyze and verify the improved impedance arc model.

[0081] Specifically, in this embodiment, an improved impedance arc equivalent circuit simulation model is built on the Matlab / Simulink platform, such as Figure 6 and Figure 7 As shown in the figure, the arc fault trigger source controls the arc fault occurrence time, the fixed value measurement module detects the arc current zero crossing point and time, the circuit breaker opens during the arc extinction and re-strike period, the LC and RC oscillation paths are connected, and the arc resistance value is controlled by the Matlab scripting language. The arc model includes a controlled current source. To solve the problem of the controlled source not being connected in series with the inductor, a capacitor is connected in parallel with the resistive and inductive load.

[0082] Among them, taking the setting model parameters, arc time constant θ = 50us, arc voltage gradient E0 = 50V, La = 0.003H, Ca = 30nF, RRC = 50Ω and CRC = 100nF in RC oscillation, LRC = 0.001H and LLC = 120nF in LC oscillation as an example: when the load is a resistive load, the fault arc simulation experiment is carried out with a resistor with a resistance of 40Ω as an example; when the load is an inductive load, the fault arc simulation experiment is carried out with a resistor with a resistance of 35Ω and an inductor with a resistance of 0.125H as an example. Set the circuit to fault at 0s, the simulation time is 0.06s, and the comparison of the simulation waveforms of the traditional Cassie model and the improved impedance arc model for resistive load and inductive load are as follows: Figure 8 and Figure 9 shown.

[0083] Depend on Figure 8 and Figure 9 It can be seen that the arc current phenomena of the improved impedance arc model and the classic Cassie model are consistent under the same simulation conditions. Under resistive load and inductive load, such as Figure 10 and Figure 12 As shown in Figure 2, the zero rest time of the traditional Cassie model is 0.788ms and 0.394ms respectively; Figure 11 and Figure 13 As shown in the figure, the zero-break time of the improved impedance arc model is 3.02ms and 0.985ms respectively. By comparison, it can be seen that the zero-break stage of the arc current of the improved impedance arc model is more obvious.

[0084] Specifically, in this embodiment, Figure 14 As shown, under resistive load, the slopes of the traditional Cassie model and the improved impedance arc model before the current passes through zero are K1 and K2 respectively, and the slopes after the current passes through zero are K3 and K4 respectively, K2>K1 and K4 <K3,因此改进阻抗电弧模型更好体现电流过零前后变化率大的特点。其中,Daubechies极限相位小波具有频域局部化的能力,且能清楚地划分频带;因此,在阻感性负载下,对仿真波形进行小波分析,用db3小波函数分解信号到3层,将信号中的最高频率成分看做1,则各层具体频带分别为:a1=0-0.5,a2=0-0.25,a3=0-0.125;d1=0.5-1,d2=0.25-0.5,d3=0.125-0.25。与 Figure 15 and Figure 17 compared to, Figure 16 and Figure 18 The current waveform of the improved impedance arc model oscillates more significantly in the high-frequency and low-frequency parts of each layer. Therefore, the improved impedance arc model has the characteristics of high-frequency oscillation and low-frequency oscillation when the arc current passes through zero.

[0085] In summary, the improved impedance arc model equivalent to a time-varying conductance during stable combustion, and equivalent to a time-varying impedance containing LC oscillation and RC oscillation during arc extinction and re-ignition, makes up for the shortcomings of the classic Cassie model in terms of the zero-hibernation stage of arc current, the current change rate before and after zero-crossing, and the unsatisfactory performance of high-frequency and low-frequency oscillation fault characteristics. Through model principle formula derivation and Simulink simulation, it is proved that the improved impedance arc model is effective, can better reflect the fault characteristics of arc current, has high theoretical significance and practical value, and lays a foundation for further research on fault arc and development of low-voltage fault arc protection electric appliances.

[0086] Referring to Figure 19 The second embodiment of the present application provides an improved impedance arc model establishment device, comprising:

[0087] The equivalent circuit establishment unit 201 is configured to establish an equivalent circuit of the arc model based on the Cassie model, wherein in the equivalent circuit, under the condition of power frequency, the equivalent circuit is expressed as an impedance function with a period of 10 ms, and during stable combustion, the arc is equivalent to a time-varying conductance, and during arc extinction and re-ignition, the arc is equivalent to a time-varying impedance containing LC oscillation and RC oscillation.

[0088] The dynamic expression acquisition unit 202 is configured to differentiate the Cassie arc model equation and obtain a dynamic expression of arc resistance by solving.

[0089] The arc conductance initial value calculation unit 203 is configured to, when the arc current approaches the natural zero-crossing, obtain an arc conductance initial value according to the dynamic expression and ignoring the arc instantaneous current.

[0090] The arc maximum conductance value calculation unit 204 is configured to, when the arc is in stable combustion, equivalent to a time-varying conductance, obtain the arc maximum conductance value in the arc extinction and re-ignition interval according to the total impedance of the load.

[0091] The improved impedance arc model generation unit 205 is configured to obtain an expression of the arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value, and generate an improved impedance arc model.

[0092] The third embodiment of the present application provides an improved impedance arc model establishment device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the improved impedance arc model establishment method of any one of the above embodiments when executing the computer program.

[0093] The fourth embodiment of the present application provides a readable storage medium, which stores a computer program. The computer program can be executed by a processor of a device where the readable storage medium is located, so as to realize the method for establishing an improved impedance arc model according to any one of the above embodiments.

[0094] Exemplarily, the computer program in the third and fourth embodiments of the present application can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present application. The one or more modules can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the device for establishing an improved impedance arc model. For example, the device in the second embodiment of the present application.

[0095] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. The processor is the control center of the method for establishing an improved impedance arc model, and is connected with all parts of the device for establishing an improved impedance arc model through various interfaces and lines.

[0096] The memory can be used to store the computer program and / or module, and the processor implements various functions of an improved impedance arc model establishment method by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function (such as a sound playback function, a text conversion function, etc.); the data storage area can store data created based on the use of the mobile phone (such as audio data, text message data, etc.). In addition, the memory can include a high-speed random access memory and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0097] Wherein, if the implemented module is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of each of the above-mentioned method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0098] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0099] The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention.

Claims

1. A method for establishing an improved impedance arc model, characterized in that: include: Based on the Cassie model, an equivalent circuit of the arc model is established. In this equivalent circuit, under power frequency conditions, it is expressed as an impedance function with a period of 10ms. The arc is equivalent to a time-varying conductance during stable burning and a time-varying impedance containing LC oscillations and RC oscillations during arc extinction and re-strike. Differentiate the Cassie arc model equation and solve it to obtain the dynamic expression of arc resistance; When the arc current approaches the natural zero crossing, the initial value of the arc conductance is obtained according to the dynamic expression while ignoring the instantaneous arc current; When the arc is burning stably, the arc resistance is equivalent to a time-varying conductance. According to the total impedance of the load, the maximum arc conductance value in the arc extinction and reignition interval is obtained; Obtaining an expression for arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model; The equivalent circuit of the arc model includes a current source, a time-varying conductance equivalent circuit, a time-varying impedance equivalent circuit, and an ideal switch, wherein the current source is connected in series with the time-varying conductance equivalent circuit, and the time-varying conductance equivalent circuit is connected in parallel with the time-varying impedance equivalent circuit via the ideal switch; The time-varying conductance equivalent circuit includes a resistive-inductive load, a first capacitor, and an arc resistor, wherein the resistive-inductive load is connected in parallel with the first capacitor and then in series with the arc resistor, one end of the current source is electrically connected to one end of the resistive-inductive load, and the other end of the resistive-inductive load is respectively electrically connected to one end of the arc resistor, one end of the ideal switch, and one end of the first capacitor, the other end of the ideal switch and the other end of the arc resistor are both electrically connected to the time-varying impedance equivalent circuit, and the other end of the arc resistor and the other end of the first capacitor are both electrically connected to the other end of the current source; The time-varying impedance equivalent circuit includes a resistor, a second capacitor, an inductor, and a third capacitor, the resistor and the second capacitor are connected in series, the inductor and the third capacitor are connected in series, the resistor and the second capacitor are connected in parallel with the inductor and the third capacitor, the other end of the ideal switch is electrically connected to one end of the resistor and one end of the inductor, the other end of the resistor is electrically connected to one end of the second capacitor, the other end of the inductor is electrically connected to one end of the third capacitor, and the other end of the second capacitor and the other end of the third capacitor are both electrically connected to the other end of the arc resistor; The arc impedance Z_a is expressed as follows: ； Where, is the maximum arc conductivity value between arc extinction and reignition, is the initial value of arc conductance, is the first capacitor, For resistive inductive load, is the resistance, is the second capacitor, inductance, is the third capacitor, is the RC oscillation value in the time-varying impedance equivalent circuit, is the LC oscillation value in the time-varying impedance equivalent circuit, is the arc time constant, interval and interval The arc is stably burning in the range is the arc extinction interval, interval It is the arc restrike interval.

2. The method for establishing an improved impedance arc model according to claim 1, characterized in that: After obtaining an expression of arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model, the method further includes: An improved impedance arc equivalent circuit simulation model corresponding to the expression of arc impedance Z_a was built through Matlab; The improved impedance arc model is analyzed and verified using the improved impedance arc equivalent circuit simulation model.

3. The method for establishing an improved impedance arc model according to claim 2, wherein: The improved impedance arc equivalent circuit simulation model is used to verify the accuracy of the improved impedance arc model, specifically: Obtain the improved impedance arc equivalent circuit simulation model in Matlab and simulate the input to obtain the simulated output voltage; The simulated output current is compared with the output current of the traditional Cassie model to analyze and verify the improved impedance arc model.

4. A device for establishing an improved impedance arc model, characterized in that: A method for establishing an improved impedance arc model according to any one of claims 1 to 3, comprising: An equivalent circuit establishment unit is used to establish an equivalent circuit of the arc model based on the Cassie model; wherein, in the equivalent circuit, under power frequency conditions, it is expressed as an impedance function with a period of 10ms, the arc is equivalent to a time-varying conductance during stable burning, and is equivalent to a time-varying impedance containing LC oscillation and RC oscillation during arc extinction and re-strike; A dynamic expression acquisition unit is used to differentiate the Cassie arc model equation and solve it to obtain a dynamic expression of arc resistance; an arc conductance initial value calculation unit, configured to obtain an arc conductance initial value according to the dynamic expression while ignoring the arc instantaneous current when the arc current approaches a natural zero crossing; The arc maximum conductance value calculation unit is used to obtain the arc maximum conductance value in the arc extinction and reignition interval according to the total impedance of the load when the arc is burning stably and the arc resistance is equivalent to a time-varying conductance; The improved impedance arc model generating unit is used to obtain an expression of arc impedance Z_a according to the arc conductance initial value and the arc maximum conductance value to generate an improved impedance arc model.

5. An improved impedance arc model establishment device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for establishing the improved impedance arc model according to any one of claims 1 to 3 is implemented.

6. A readable storage medium, characterized in that: A computer program is stored, and the computer program can be executed by a processor of the device where the storage medium is located to implement the method for establishing the improved impedance arc model as described in any one of claims 1 to 3.

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