Analysis Method, Device, Electronic Device, and Storage Medium of Digital Circuit

Abstract

A method, apparatus, electronic device, and storage medium for analyzing a digital circuit. The method for analyzing the digital circuit includes: processing a first synthesis file corresponding to the digital circuit to obtain a second synthesis file; extracting a plurality of waveform sub-files corresponding to a plurality of second instances from a first waveform file corresponding to the first synthesis file; and integrating the plurality of waveform sub-files based on a second hierarchical structure to obtain a second waveform file corresponding to the second synthesis file. The method for analyzing the digital circuit effectively solves the problem that waveforms cannot be converted due to changes in the hierarchical structure, provides an effective solution for complex chip design, greatly improves the efficiency of circuit design, reduces the time spent in the circuit simulation and verification process, and speeds up the project R & D progress.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for analyzing a digital circuit, an apparatus for analyzing a digital circuit, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Hierarchy design is a very popular design concept nowadays. As the scale of chips increases, the data volume and complexity of chips increase sharply. Therefore, it is becoming increasingly unrealistic to directly complete the design, synthesis, etc. of the entire chip. Therefore, the concept of hierarchy design is introduced in chip design. From the initial planning stage of the chip, the hierarchy concept runs through the entire design process, and each design stage in the integrated circuit will be affected to varying degrees. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for analyzing a digital circuit, including: processing a first synthesis file corresponding to the digital circuit to obtain a second synthesis file, where the first synthesis file includes a plurality of first instances, the second synthesis file includes a plurality of second instances, and the processing includes re-partitioning the plurality of first instances to obtain the plurality of second instances; extracting a plurality of waveform sub-files corresponding to the plurality of second instances respectively from a first waveform file corresponding to the first synthesis file; and integrating the plurality of waveform sub-files based on a second hierarchy structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file.

[0004] For example, in the method for analyzing a digital circuit provided by at least one embodiment of the present disclosure, a first hierarchy structure of the first synthesis file is different from a second hierarchy structure of the second synthesis file.

[0005] For example, in the method for analyzing a digital circuit provided by at least one embodiment of the present disclosure, the first synthesis file includes a register transfer level description file or a front-end netlist, and the second synthesis file includes a register transfer level description file, a front-end netlist, or a back-end netlist.

[0006] For example, in the method for analyzing a digital circuit provided by at least one embodiment of the present disclosure, each second instance has a corresponding first instance. Extracting the plurality of waveform sub-files corresponding to the plurality of second instances respectively from the first waveform file corresponding to the first synthesis file includes: determining a correspondence relationship of the plurality of second instances in the first synthesis file; and extracting the plurality of waveform sub-files corresponding to the plurality of second instances respectively from the first waveform file based on the correspondence relationship.

[0007] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, based on the corresponding relationship, extracting multiple waveform sub-files respectively corresponding to the multiple second instances from the first waveform file includes: for each second instance among the multiple second instances: based on the corresponding relationship, determining the first instance corresponding to the second instance; extracting the associated waveform corresponding to the first instance from the first waveform file; and adjusting the hierarchical relationship of the associated waveform according to the hierarchical relationship of the second instance in the second hierarchical structure to obtain the waveform sub-file corresponding to the second instance, where the hierarchical relationship of the waveform sub-file is the same as the hierarchical relationship of the second instance in the second hierarchical structure.

[0008] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, based on the second hierarchical structure of the second synthesis file, integrating the multiple waveform sub-files to obtain the second waveform file corresponding to the second synthesis file includes: combining the multiple waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to the second instance in the second hierarchical structure to obtain the second waveform file, where the hierarchical structure of the second waveform file is the same as the second hierarchical structure.

[0009] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, the re-partitioning process includes a combination operation and a de-partitioning operation, and the second synthesis file further includes at least one third instance. Re-partitioning the multiple first instances to obtain the multiple second instances includes: performing the combination operation on at least one first instance to obtain one third instance; or performing the de-partitioning operation on one first instance to obtain at least two second instances.

[0010] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, based on the second hierarchical structure of the second synthesis file, integrating the multiple waveform sub-files to obtain the second waveform file corresponding to the second synthesis file includes: combining the multiple waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to the second instance in the second hierarchical structure to obtain an intermediate waveform file; establishing a state element mapping relationship for the instance to be adjusted according to the second hierarchical structure, where the instance to be adjusted includes the at least one third instance or M second instances obtained by the de-partitioning operation, and M is a positive integer greater than 1; and obtaining the second waveform file based on the intermediate waveform file and the state element mapping relationship.

[0011] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, according to the second hierarchical structure, establishing a state element mapping relationship for an instance to be adjusted includes: determining at least one second instance constituting the at least one third instance according to the hierarchical relationship of the at least one third instance in the second hierarchical structure; obtaining all state elements of the at least one second instance according to the second comprehensive document; and establishing a state element mapping relationship for the at least one third instance according to the first comprehensive document and all state elements of the at least one second instance.

[0012] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, according to the second hierarchical structure, establishing a state element mapping relationship for the M second instances includes: obtaining all state elements of the M second instances according to the second comprehensive document; and establishing a state element mapping relationship for the M second instances according to the first comprehensive document and all state elements of the M second instances.

[0013] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, where the state element includes an input port, establishing a state element mapping relationship for the at least one third instance according to the first comprehensive document and all state elements of the at least one second instance includes: for each third instance in the at least one third instance, determining N second instances constituting the third instance, where N is a positive integer; determining the fan-in corresponding to all input ports of the N second instances according to the first comprehensive document; and establishing a mapping relationship between the fan-in and all input ports of the N second instances to establish a state element mapping relationship for the third instance.

[0014] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, when both the first comprehensive document and the second comprehensive document are front-end netlists, the analysis method further includes: obtaining a register transfer level description file corresponding to the second comprehensive document; and performing gate-level power consumption analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive document, the second comprehensive document, and the second waveform file.

[0015] For example, in the analysis method of a digital circuit provided by at least one embodiment of the present disclosure, performing gate-level power consumption analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive document, the second comprehensive document, and the second waveform file includes: performing a one-to-one mapping between the register transfer level description file corresponding to the second comprehensive document and the timing devices in the second comprehensive document to obtain a mapping relationship; and performing a parallel simulation analysis on the combinational logic between the timing devices according to the second waveform file and the mapping relationship to obtain the gate-level power consumption analysis result of the digital circuit.

[0016] At least one embodiment of the present disclosure provides an analysis device for a digital circuit, including: a processing unit configured to process a first synthesis file corresponding to the digital circuit to obtain a second synthesis file, where the first synthesis file includes a plurality of first instances, the second synthesis file includes a plurality of second instances, and the processing includes performing a re-partitioning process on the plurality of first instances to obtain the plurality of second instances; an extraction unit configured to extract a plurality of waveform sub-files respectively corresponding to the plurality of second instances from a first waveform file corresponding to the first synthesis file; and an integration unit configured to integrate the plurality of waveform sub-files based on a second hierarchical structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file.

[0017] At least one embodiment of the present disclosure further provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; and a processor configured to run the computer-executable instructions, where the computer-executable instructions, when run by the processor, implement the analysis method of the digital circuit according to any one of the embodiments of the present disclosure.

[0018] At least one embodiment of the present disclosure further provides a non-transient computer-readable storage medium, where the non-transient computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by a processor, implement the analysis method of the digital circuit according to any one of the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0020] Figure 1 A schematic diagram showing the hierarchical structure of a digital circuit;

[0021] Figure 2 A schematic flowchart of an analysis method of a digital circuit provided by at least one embodiment of the present disclosure;

[0022] Figure 3A and Figure 3B A schematic diagram of circuit partitioning provided by one embodiment of the present disclosure;

[0023] Figure 3C and Figure 3D A schematic diagram of circuit partitioning provided by another embodiment of the present disclosure;

[0024] Figure 4A and Figure 4BSchematic diagram of the hierarchical structure of a comprehensive document provided by an embodiment of the present disclosure;

[0025] Figure 5 Schematic block diagram of an analysis device for a digital circuit provided by at least one embodiment of the present disclosure;

[0026] Figure 6 Schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0027] Figure 7 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0028] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0029] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and the like used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0030] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted in the present disclosure.

[0031] In the design process of large-scale digital circuits, such as very large scale integrated circuits (VLSIs), the hierarchical structure of the circuit can be determined according to actual needs during the initial planning stage of the project. For example, the hierarchical structure can be partitioned based on module functions and module scales, dividing the entire circuit into multiple partitions. For example, these multiple partitions can also be referred to as multiple sub-designs. Each partition has separate physical constraints, and the part of the entire circuit (design) other than the multiple partitions is regarded as the top-level design (Top). The top-level design and each partition are treated as separate designs for placement and routing. In this way, an ultra-large-scale circuit can be divided into multiple sub-designs with relatively small scales, thus greatly improving the tolerance and design efficiency of Electronic Design Automation (EDA) software for the design.

[0032] Figure 1 Fig. shows a schematic diagram of the hierarchical structure of a digital circuit.

[0033] As Figure 1 shown, the design of the digital circuit includes a top-level design and 4 sub-designs. The 4 sub-designs are Partition 1, Partition 2, Partition 3, and the sub-top-level design (sub-top). Under the sub-top-level design, there are sub-partition_1, sub-partition_2, and sub-partition_3. There is no dependency relationship between each sub-design, and each sub-design can have independent physical constraints.

[0034] Figure 1 The top-level design and the sub-top-level design in are typical hierarchical designs. Generally, in a hierarchically designed digital circuit (such as a chip), there is only one top-level design, but there may be multiple sub-top-level designs. Even deeper-level sub-top-level designs may exist under the sub-top-level design, which depends on the depth of the digital circuit hierarchy and the complexity of the chip. It can be foreseen that the deeper the hierarchical depth, the lower the complexity of a single partition.

[0035] For example, an integrated circuit can also be directly divided into multiple modules, and then the multiple modules can be designed and developed in parallel, and finally integrated, placed and routed together. For example, each module consists of some circuit logics that perform specific functions. For example, if a module in the circuit appears only once, for this module, the instance and the module have the same meaning, both referring to this module; if a module in the integrated circuit appears multiple times and is named differently, these modules with different names are called different instances. For example, the integrated circuit includes two Module 1s, and the two Module 1s have different names and can be called Instance 1 and Instance 2 respectively.

[0036] For example, ideally, all partitions are planned at the initial stage of the project. For example, the circuit is partitioned according to functions, design size and complexity, design reuse, physical constraints, etc. However, at any design stage in the entire circuit design process, in order to obtain the optimal circuit, it may be necessary to modify the hierarchical structure of the circuit so that the comprehensive structure of each partition, each module / instance, and the entire circuit can meet the expected goals.

[0037] The circuit is simulated and verified at multiple design stages in the integrated circuit design process, including pre-simulation, post-synthesis simulation, and post-simulation, etc. For example, pre-simulation includes Register Transfer Level (RTL) simulation. RTL simulation is based on RTL files for simulation and tests the logic function to verify whether the function meets the design requirements. For example, in post-synthesis simulation, the standard delay file is backannotated to the synthesis simulation model to estimate the impact of gate delay on the circuit. For example, post-simulation includes simulating the netlist after placement and routing, and this simulation is closer to the actual operation of the circuit devices.

[0038] When the hierarchical structure of the circuit changes, for example, when the circuit is re-partitioned according to specific circuit requirements, so that the hierarchical structure of the circuit is modified from the first hierarchical structure to the second hierarchical structure, the waveform file obtained by simulating the circuit with the first hierarchical structure cannot be directly used. If a waveform file for the circuit with the second hierarchical structure is required, it is necessary to re-simulate and analyze the circuit with the second hierarchical structure. However, since the circuit partition may be adjusted according to the actual situation of the circuit at each stage of the circuit design, this will result in the unusability of the already executed simulation results, and re-simulation will greatly increase the time spent on circuit simulation verification and reduce the project R & D progress.

[0039] For example, in a specific example, with the continuous increase in the chip design scale and the continuous upgrade of the process, reducing power consumption has become a major problem in chip design. The true power consumption of the chip can only be tested after placement and routing are completed. For example, the circuit after placement and routing can be post-simulated to obtain a waveform file, and the power consumption can be analyzed based on this waveform file. Although the post-simulation waveform is very close to the actual circuit situation, the post-simulation cycle is very long and requires a large amount of hardware resources and time. Especially in very large-scale integrated circuits, such as CPU (Central Processing Unit) or GPU (Graphics Processing Unit) chips, it is very difficult for designers to perform simulation verification for all modes of the entire circuit. In contrast, the time spent on pre-simulation is much less. Therefore, the post-simulation waveform can be obtained using the pre-simulation waveform, enabling power consumption analysis to be synchronized with automatic placement and routing in the project, greatly improving the power consumption analysis speed and playing a key role in reducing the circuit power consumption.

[0040] However, in some complex chip designs, the front-end circuit design is divided according to circuit architecture, function, etc. However, in the synthesis stage, the division of the front-end circuit design may be modified according to factors such as the size, complexity, and distance arrangement of the modules. Moreover, in the logic synthesis stage of the front-end design, the register transfer level description file is regrouped (re-divided) according to the specific situation of the above-mentioned back-end placement and routing process, that is, re-divided, and then a new front-end netlist is generated. At this time, the hierarchical structure of the new front-end netlist is different from that of the front-end netlist before re-division.

[0041] For example, a method for power consumption analysis based on the simulation waveform of the front-end netlist is to perform power consumption analysis according to the RTL file of the circuit, the front-end netlist, and the simulation waveform file corresponding to the front-end netlist. However, since the hierarchical structure of the front-end netlist has been modified, the simulation waveform of the front-end netlist before re-division can no longer be directly used. At this time, only the new front-end netlist can be re-simulated to perform power consumption analysis, which will also greatly increase the time spent on circuit simulation verification and power consumption analysis. If multiple re-divisions occur in the design stage, and pre-simulation needs to be re-executed each time for synchronous power consumption analysis, or designers need to implement functional verification based on two sets of front-end netlists, this will greatly reduce the R & D efficiency and consume a large amount of resources and time.

[0042] At least one embodiment of the present disclosure provides an analysis method for a digital circuit, including: processing a first synthesis file corresponding to the digital circuit to obtain a second synthesis file, where the first synthesis file includes multiple first instances, the second synthesis file includes multiple second instances, and the processing includes re-dividing the multiple first instances to obtain multiple second instances; extracting multiple waveform sub-files corresponding to the multiple second instances from a first waveform file corresponding to the first synthesis file; and integrating the multiple waveform sub-files based on a second hierarchical structure to obtain a second waveform file corresponding to the second synthesis file.

[0043] At least one embodiment of the present disclosure provides an analysis method for a digital circuit. Integrating the extracted multiple waveform sub-files according to the second hierarchical structure to obtain a second waveform file corresponding to the new hierarchical structure, so that the obtained simulation results do not have to be unusable due to the change of the circuit hierarchical structure, effectively solving the problem that the waveform cannot be converted due to the change of the hierarchical structure, providing an effective solution for complex chip design, greatly improving the efficiency of circuit design, reducing the time spent in the circuit simulation verification process, and accelerating the project R & D progress.

[0044] Figure 2 It is a schematic flowchart of an analysis method for a digital circuit provided by at least one embodiment of the present disclosure. As Figure 2As shown, an analysis method for a digital circuit provided by at least one embodiment of the present disclosure at least includes steps S10 - S30.

[0045] For example, the digital circuit can be an integrated circuit, such as a large - scale integrated circuit or a very - large - scale integrated circuit, such as the chip circuit of a CPU or a GPU, etc.

[0046] In step S10, process the first synthesis file corresponding to the digital circuit to obtain a second synthesis file.

[0047] For example, the first synthesis file includes multiple first instances, and the second synthesis file includes multiple second instances. The processing includes re - partitioning the multiple first instances to obtain multiple second instances.

[0048] For example, the first hierarchical structure of the first synthesis file is different from the second hierarchical structure of the second synthesis file.

[0049] For example, the re - partitioning process includes a combination operation and an un - partitioning operation. Re - partitioning the multiple first instances to obtain multiple second instances can include: performing a combination operation on at least one first instance to obtain a third instance; or, performing an un - partitioning operation on a first instance to obtain at least two second instances.

[0050] For example, during the design process, it is found that some module areas are too small. For example, due to the module boundaries divided manually, the optimization is restricted and the synthesis result is not optimal. At this time, these modules can be combined into a new module. For example, these modules can be combined through a combination operation (such as the group command).

[0051] Figure 3A and Figure 3B is a schematic diagram of circuit partitioning provided by an embodiment of the present disclosure.

[0052] As Figure 3A shown, the entire circuit includes a top - level design, instance U1, instance U2, and instance U3. Instance U1 includes combinational logic 1 and registers. Instance U2 includes combinational logic 2. Instance U3 includes combinational logic 3 and registers.

[0053] As Figure 3B shown, the entire circuit includes a top - level design, instance U1’, instance U2’, and instance U3’. Instance U1’ corresponds to instance U1, instance U2’ corresponds to instance U2, and instance U3’ corresponds to instance U3. Figure 3B The circuit in Figure 3A is obtained by performing a combination operation on the circuit shown in

[0054] For example, to obtain a better comprehensive result, the group command is used to combine instances U2 and U3, generating a new instance U23. At this time, Figure 3A The hierarchical structure of the circuit shown is different from that of Figure 3B The hierarchical structure of the circuit shown, and the new instance U23 generates a new hierarchy.

[0055] For example, during the design process, it is found that the area of a certain partition / module is too large, such as the running time required for optimization is too long. At this time, these modules can be split to obtain multiple modules. For example, these modules can be split by canceling the partitioning operation (such as the ungroup command).

[0056] Figure 3C and Figure 3D is a schematic diagram of circuit partitioning provided by another embodiment of the present disclosure.

[0057] As Figure 3C shown, the entire circuit includes a top-level design, instance U4, and instance U56. Instance U56 includes sub-instances U5 and U6. Instance U4 includes combinational logic 4 and registers. Sub-instance U5 includes combinational logic 5. Sub-instance U6 includes combinational logic 6 and registers.

[0058] As Figure 3D shown, the entire circuit includes a top-level design, instance U4', instance U5', and instance U6'. Instance U4' corresponds to instance U4. Instance U5' corresponds to sub-instance U5. Instance U6' corresponds to sub-instance U6. Figure 3D The circuit in Figure 3C is obtained by performing an ungrouping operation on the circuit shown.

[0059] For example, the ungroup command is used to perform an ungrouping process on instance U56, generating new instances U5' and U6'. At this time, Figure 3C The hierarchical structure of the circuit shown is different from that of Figure 3D The hierarchical structure of the circuit shown, and the hierarchical relationship between instances U5' and U6' changes.

[0060] For example, each second instance has a corresponding first instance, that is, the second instance does not belong to the newly added hierarchy during the re-partitioning process. The second instance can be obtained by performing an ungrouping operation, or the second instance can also include the first instance on which the ungrouping operation and the combination operation are not performed.

[0061] For example, the third instance belongs to the newly added hierarchy during the re-partitioning process.

[0062] For example, taking the circuit schematic diagrams shown in Figure 3A and Figure 3B as an example, multiple first instances can includeFigure 3A The illustrated Instance U1, Instance U2, and Instance U3. By performing a re-partitioning process on multiple first instances, Figure 3B the multiple second instances and a third instance shown are obtained. Specifically, Figure 3A by performing a combination operation on the illustrated first Instance U2 and first Instance U3, the third Instance U23 is obtained. Therefore, the multiple second instances may include Figure 3B the illustrated Instance U1’, Instance U2’, and Instance U3’, and the third instance may include Figure 3B the illustrated Instance U23. Figure 3B The second Instance U1’, second Instance U2’, and second Instance U3’ in Figure 3A correspond to the illustrated first Instance U1, first Instance U2, and first Instance U3 respectively.

[0063] For example, taking the circuit schematic diagrams shown in Figure 3C and Figure 3D as an example, the multiple first instances may include Figure 3C the illustrated Instance U4, Instance U56, and the sub-instances U5 and U6 included in Instance U56. By performing a re-partitioning process on the multiple first instances, Figure 3D the multiple second instances shown are obtained. Specifically, Figure 3C by performing a de-partitioning operation on the illustrated first Instance U56, the second instances U5’ and U6’ are obtained. Therefore, the multiple second instances may include Figure 3D the illustrated Instance U4’, Instance U5’, and Instance U6’. Figure 3D The second Instance U4’ shown in Figure 3C corresponds to the first Instance U4 in Figure 3D The second Instance U5’ shown in Figure 3C corresponds to the sub-instance U5 in Figure 3D The second Instance U6’ shown in Figure 3C corresponds to the sub-instance U6 in

[0064] In different scenarios, the results obtained from the de-partitioning operation and the combination operation may be different. Figures 3A - 3D For a schematic description, the present disclosure does not specifically limit the execution manners and execution results of the de-partitioning operation and the combination operation.

[0065] For example, the first synthesis file includes a register transfer level description file or a front-end netlist, and the second synthesis file includes a register transfer level description file, a front-end netlist, or a back-end netlist.

[0066] It should be noted that the front-end netlist (pre-layout netlist or pre place and route netlist) in the present disclosure refers to the gate-level netlist obtained after logical synthesis of the register transfer level description file, that is, the netlist before performing routing and placement. The front-end netlist represents the connection relationship of components at the logic layer. The back-end netlist (post-layout netlist or post place and route netlist) refers to the netlist generated after physical synthesis of the front-end netlist, that is, the netlist after optimization processes such as placement and routing, timing optimization, clock tree synthesis, and high fan-out synthesis. The back-end netlist adds information such as clock trees and buffers according to the physical implementation.

[0067] For example, in the RTL design stage, the register transfer level description file can be re-partitioned according to the specific needs of the RTL design process. For example, the re-partitioning process includes the combination operation and the de-partitioning operation as described above, thereby obtaining register transfer level description files with different hierarchical structures. At this time, the first synthesis file is the register transfer level description file before the re-partitioning process, and the second synthesis file is the register transfer level description file after the re-partitioning process.

[0068] For example, in the front-end design stage, the front-end netlist can be re-partitioned according to the specific needs of the front-end design process, thereby obtaining front-end netlists with different hierarchical structures. At this time, the first synthesis file can be the front-end netlist before the re-partitioning process, and the second synthesis file can be the front-end netlist after the re-partitioning process.

[0069] For example, when performing power consumption analysis, the register transfer level description file with the first hierarchical structure can be re-partitioned according to the specific situation of the back-end placement and routing. For example, two modules with smaller areas can be merged into a new module, or a module with a larger area can be split into multiple new modules, thereby obtaining a register transfer level description file with the second hierarchical structure. Then, logical synthesis is performed on the register transfer level description file with the second hierarchical structure to obtain a front-end netlist with the second hierarchical structure. At this time, the first synthesis file can be the front-end netlist before the re-partitioning process, and the second synthesis file can be the front-end netlist after the re-partitioning process.

[0070] For example, when performing power consumption analysis, the first synthesis file can also be a register transfer level (RTL) description file before re-partitioning processing, and the second synthesis file can be a front-end netlist after re-partitioning processing. At this time, in step S10, processing the first synthesis file corresponding to the digital circuit to obtain the second synthesis file may include: re-partitioning the RTL description file with the first hierarchical structure to obtain an RTL description file with the second hierarchical structure; and then performing logic synthesis on the RTL description file with the second hierarchical structure to obtain the second synthesis file.

[0071] For example, in other embodiments, such as in other design stages, the first synthesis file can also be a front-end netlist, the second synthesis file can also be a back-end netlist, etc. The contents of the first synthesis file and the second synthesis file can be selected according to usage needs, and the present disclosure does not limit this.

[0072] In step S20, extract multiple waveform sub-files corresponding to multiple second instances from the first waveform file corresponding to the first synthesis file.

[0073] For example, step S20 may include: determining the correspondence of multiple second instances in the first synthesis file; and based on the correspondence, extracting multiple waveform sub-files corresponding to multiple second instances from the first waveform file.

[0074] For example, the correspondence may include the first instance corresponding to the second instance in the first synthesis file, and the correspondence between the first instance and the second instance can be referred to the relevant description of the circuit schematic diagram shown Figures 3A - 3D and will not be elaborated here.

[0075] For example, based on the correspondence, extracting multiple waveform sub-files corresponding to multiple second instances from the first waveform file may include: for each second instance among the multiple second instances: based on the correspondence, determining the first instance corresponding to the second instance; extracting the associated waveform corresponding to the first instance from the first waveform file; and adjusting the hierarchical relationship of the associated waveform according to the hierarchical relationship of the second instance in the second hierarchical structure to obtain the waveform sub-file corresponding to the second instance, where the hierarchical relationship of the waveform sub-file is the same as the hierarchical relationship of the second instance in the second hierarchical structure.

[0076] For example, taking the second instance as Figure 3B the instance U2' in Figure 3A as an example, the first instance corresponding to the second instance U2' is Figure 3ASimulate the circuit shown to obtain a first waveform file, and extract the associated waveform corresponding to the first instance U2 from the first waveform file. The associated waveform refers to the simulation waveform related to the first instance U2. For example, the extraction of the associated waveform can be achieved through an EDA tool, such as the fsdbextract command, etc. Regarding the fsdbextract command, reference can be made to the content described later. Of course, the extraction of the associated waveform can also adopt other feasible methods, and the present disclosure places no restrictions thereon.

[0077] For example, since new levels are added during the re-partitioning process, as Figure 3B shown, a third instance U23 is added between the second instance U2’ and the top-level design. Therefore, the hierarchical relationships of the first instance U2 and the second instance U2’ in the corresponding hierarchical structure are different. For example, the hierarchical relationship of the first instance U2 is / TOP / U2, and the hierarchical relationship of the second example U2’ is / TOP / U23 / U2’. Thus, the hierarchical relationship of the associated waveform corresponding to the first instance U2 needs to be adjusted accordingly to obtain the waveform sub-file corresponding to the second instance U2’, and the waveform sub-file corresponding to the second instance needs to be the same as the hierarchical relationship of the second instance in the second hierarchical structure.

[0078] For example, since a second instance is added during the re-partitioning process, for example, Figure 3C in which the first instance U56 is split into Figure 3D the second instance U5’ and the second instance U6’ in Figure 3D the circuit shown. The second instance U5’ corresponds to the first instance U5, and the hierarchical relationship of the associated waveform of the first instance U5 is different from the hierarchical relationship of the second instance U5’ in

[0079] the circuit shown. For example, the hierarchical relationship of the first instance U5 is / TOP / U56 / U5, and the hierarchical relationship of the second example U5’ is / TOP / U5’. Thus, the hierarchical relationship of the associated waveform needs to be adjusted accordingly to obtain the waveform sub-file corresponding to the second instance, and the waveform sub-file corresponding to the second instance needs to be the same as the hierarchical relationship of the second instance in the second hierarchical structure.

[0080] In step S30, based on the second hierarchical structure, integrate multiple waveform sub-files to obtain the second waveform file corresponding to the second comprehensive file.

[0081] For example, step S30 may include: combining a plurality of waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to a second instance in the second hierarchy to obtain a second waveform file, where the hierarchy of the second waveform file is the same as that of the second hierarchy.

[0082] For example, the process of waveform integration corresponds to the process of re-partitioning the design, that is, how the re-partitioning process is performed, and correspondingly how the waveform integration is performed.

[0083] For example, in step S20, Figure 3B after obtaining the waveform sub-file 1 corresponding to the instance U2' and the waveform sub-file 2 corresponding to the instance U3' in, the waveform sub-file 1 and the waveform sub-file 2 are merged in waveform to obtain the waveform file of the instance U23. For example, the waveform merging can be implemented by an EDA tool, such as the fsdbmerge command, etc. For the fsdbmerge command, reference can be made to the content described later. Of course, the waveform merging can also be implemented in other feasible ways, and the present disclosure does not limit this.

[0084] After that, according to the waveform sub-file 3 corresponding to the instance U1' obtained in step S20 and the waveform file of the instance U23, a second waveform file is obtained.

[0085] For the newly added third instance and the second instance obtained by the un-partitioning operation, the interface mapping relationships of these newly added instances need to be adjusted. For example, taking the combination operation as an example, it is necessary to map the interface of the instance U23 to the interfaces of the instance U2' and the instance U3' correspondingly.

[0086] For example, when a new instance is generated during the re-partitioning process, step S30 may include: combining a plurality of waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to a second instance in the second hierarchy to obtain an intermediate waveform file; establishing a state element mapping relationship for the instance to be adjusted according to the second hierarchy, where the instance to be adjusted includes at least one third instance or M second instances obtained by the un-partitioning operation, and M is a positive integer greater than 1; and obtaining a second waveform file based on the intermediate waveform file and the state element mapping relationship.

[0087] The generation process of the intermediate waveform file is the same as the foregoing content and will not be elaborated here.

[0088] For example, when the instance to be adjusted includes a third instance, establishing a state element mapping relationship for the instance to be adjusted according to the second-level hierarchy may include: determining at least one second instance that constitutes at least one third instance according to the hierarchical relationship of at least one third instance in the second-level hierarchy; obtaining all state elements of at least one second instance according to the second comprehensive document; and establishing a state element mapping relationship for at least one third instance according to the first comprehensive document and all state elements of at least one second instance.

[0089] For example, state elements may include input ports, output ports, etc.

[0090] For example, when the state element includes an input port, establishing a state element mapping relationship for at least one third instance according to the first comprehensive document and all state elements of at least one second instance may include: for each third instance among at least one third instance, determining N second instances that constitute the third instance; determining the fan-in corresponding to all input ports of the N second instances according to the first comprehensive document; and establishing a mapping relationship between the fan-in and all input ports of the N second instances to establish a state element mapping relationship for the third instance, where N is a positive integer.

[0091] For example, when the instance to be adjusted includes a third instance obtained by a cancellation partitioning operation, establishing a state element mapping relationship for the instance to be adjusted according to the second-level hierarchy may include: obtaining all state elements of M second instances according to the second comprehensive document; and establishing a state element mapping relationship for M second instances according to the first comprehensive document and all state elements of M second instances.

[0092] Similarly, establishing a state element mapping relationship for M second instances can also be determined according to the fan-in corresponding to all input ports of M second instances, which will not be elaborated here.

[0093] The analysis method of a digital circuit provided by at least one embodiment of the present disclosure can effectively solve the problem that waveforms cannot be directly converted due to re-partitioning processing, and the simulation waveform file of the circuit after re-partitioning processing can be obtained at any time in all stages of digital circuit design, promoting the normal operation of the project, reducing resource waste, and improving R & D efficiency.

[0094] Figure 4A and Figure 4B is a schematic diagram of the hierarchical structure of a comprehensive document provided by an embodiment of the present disclosure.

[0095] As Figure 4A shown, under the top-level design (TOP-LEVEL), the circuit includes three instances, namely instance A, instance B, and instance C, and instance B includes sub-instances D, sub-instance E, and sub-instance F.

[0096] AsFigure 4B As shown, under the top-level design, the circuit includes instance M1, instance M2, and instance M3. Instance M1 includes sub-instances A' and D'. Instance M2 includes sub-instance B', and sub-instance B' includes sub-instance E'. Instance M3 includes sub-instances C' and F'.

[0097] For example, the first synthesis file has a first hierarchical structure as Figure 4A shown, and the second synthesis file has a second hierarchical structure as Figure 4B shown.

[0098] Next, in conjunction with Figure 4A and Figure 4B , a design method for a digital circuit provided by at least one embodiment of the present disclosure will be specifically described.

[0099] First, in step S10, the first synthesis file is processed to obtain a second synthesis file.

[0100] For example, the first synthesis file includes first instances A, B, C, D, E, and F.

[0101] For example, the second synthesis file includes second instances A', B', C', D', E', and F'. In addition, the second synthesis file further includes third instances M1, M2, and M3.

[0102] For example, first instance A corresponds to second instance A', first instance B corresponds to second instance B', first instance C corresponds to second instance C', first instance D corresponds to second instance D', first instance E corresponds to second instance E', and first instance F corresponds to second instance F'.

[0103] For example, the hierarchical relationship of first instance A is / TOP / A, the hierarchical relationship of second instance A' is / TOP / M1 / A', the hierarchical relationship of first instance B is / TOP / B, the hierarchical relationship of second instance B' is / TOP / M2 / B', the hierarchical relationship of first instance C is / TOP / C, the hierarchical relationship of second instance C' is / TOP / M3 / C', the hierarchical relationship of first instance D is / TOP / B / D, the hierarchical relationship of second instance D' is / TOP / M1 / D', the hierarchical relationship of first instance E is / TOP / B / E, the hierarchical relationship of second instance E' is / TOP / M2 / B' / E', the hierarchical relationship of first instance F is / TOP / B / F, and the hierarchical relationship of second instance F' is / TOP / M3 / F'.

[0104] Specifically, perform a re - partitioning process on multiple first instances included in the first comprehensive file. For example, perform a combination operation on the first instance A and the first instance D to generate the third instance M1, perform a combination operation on the first instance B to generate the third instance M2, and perform a combination operation on the first instance C and the first instance F to generate the third instance M3.

[0105] Such as Figure 4A and Figure 4B It can be seen that after the combination operation in the re - partitioning process, the hierarchical structure of the second comprehensive file is completely different from that of the first comprehensive file.

[0106] After that, in step S20, extract the waveform sub - files corresponding to the second instance A’, the second instance B’, the second instance C’, the second instance D’, the second instance E’ and the second instance F’ respectively from the first waveform file corresponding to the first comprehensive file.

[0107] For example, taking the second instance A’ as an example, first execute the following command to extract the associated waveform of the first instance A and store it as an independent waveform file step1.fsdb:

[0108] fsdbextract tb.fsdb – s / TOP / A – level 0 – o step1.fsdb

[0109] Here, fsdbextract represents the waveform extraction command, step1.fsdb represents the waveform file of the associated waveform of the first instance A, tb.fsdb represents the first waveform file, / TOP / A represents the hierarchical relationship of the first instance A, and – s, – level 0 and – o represent command parameters.

[0110] After that, execute the following command to adjust the hierarchical relationship of the associated waveform of the first instance A to obtain the waveform sub - file A.fsdb corresponding to the second instance A’:

[0111] fsdbedit step1.fsdb – insert_scope ‘ / TOP / $scope(M1) / A’ – o step2.fsdb

[0112] fsdbedit step2.fsdb – delate_scope ‘$scope( / TOP)’ – o A.fsdb

[0113] fsdbedit represents the waveform editing command. For the specific parameters of the fsdbedit command, you can refer to the usage manual of fsdbedit, which will not be elaborated here.

[0114] For example, when extracting the waveform sub-file corresponding to the second instance B', the associated waveform B corresponding to the first instance B can be extracted first, and then the associated waveforms corresponding to the first instance D and the first instance F in the associated waveform B are extracted, and the remaining part is inserted into the new layer M2, thereby obtaining the waveform sub-file corresponding to the second instance B'. At the same time, since the relative relationship between the second instance B' and the second instance E' remains unchanged, the waveform sub-file corresponding to the second instance E' is also obtained.

[0115] After that, in step S30, first, the multiple waveform sub-files are combined according to the hierarchical relationship of each waveform sub-file corresponding to the second instance in the second hierarchical structure to obtain an intermediate waveform file.

[0116] For example, in step S20, the waveform sub-files A.fsdb and D.fsdb corresponding to the second instance A' and the second instance D' are obtained respectively. Execute the following command to merge the waveform sub-file A.fsdb and the waveform sub-file D.fsdb to obtain the waveform sub-file M1.fsdb corresponding to the third instance M1:

[0117] fsdbmerge A.fsdb D.fsdb–o M1.fsdb

[0118] Here, fsdbmerge represents the waveform merging command. For the specific parameters of the fsdbmerge command, you can refer to the usage manual of fsdbmerge, which will not be elaborated here.

[0119] After obtaining the intermediate waveform file, establish the state element mapping relationship for the third instance M1, the third instance M2, and the third instance M3.

[0120] For example, taking the third instance M1 as an example, first read the second synthesis file to obtain all the input ports (input pins) of the second instance A' and the second instance D'; then, read the first synthesis file to find the pins of the fan-in corresponding to all the input ports of the second instance A' and the second instance D'; match the fan-in pins with all the input ports of the second instance A' and the second instance D one by one, thereby establishing the mapping relationship between the fan-in and all the input ports of the second instance A' and the second instance D, that is, establishing the state element mapping relationship for the third instance M1.

[0121] Finally, based on the intermediate waveform file and the state element mapping relationships of the third instance M1, the third instance M2, and the third instance M3, obtain the second waveform file corresponding to the second synthesis file.

[0122] The design method of the digital circuit provided by at least one embodiment of the present disclosure can also be used for power consumption analysis using the waveforms of pre-simulation. As mentioned above, since the hierarchical relationship of the gate-level netlist has changed, the mapping relationship between the register transfer level description file and the front-end netlist cannot be determined, and power consumption analysis cannot be directly performed.

[0123] For example, when both the first synthesis file and the second synthesis file are front-end netlists, the design method of the digital circuit provided by at least one embodiment of the present disclosure may further include: obtaining the register transfer level description file corresponding to the second synthesis file; based on the register transfer level description file corresponding to the second synthesis file, the second synthesis file, and the second waveform file, performing gate-level power consumption analysis on the digital circuit.

[0124] Of course, as before, the first synthesis file may also be a register transfer level description file, and the second synthesis file is a front-end netlist. At this time, the above steps of gate-level power consumption analysis can also be executed.

[0125] For example, performing gate-level power consumption analysis on the digital circuit based on the register transfer level description file corresponding to the second synthesis file, the second synthesis file, and the second waveform file may include: performing one-to-one mapping between the register transfer level description file corresponding to the second synthesis file and the timing devices in the second synthesis file to obtain a mapping relationship; according to the second waveform file and the mapping relationship, performing parallel simulation analysis on the combinational logic between the timing devices to obtain the gate-level power consumption analysis result of the digital circuit.

[0126] Therefore, the design method of the digital circuit provided by at least one embodiment of the present disclosure does not require relevant designers to verify the relevant functions based on two sets of netlists (the front-end netlist before re-partitioning processing and the front-end netlist after re-partitioning processing). The synthesis team can also re-group according to the actual needs of physical design, and finally jointly promote the progress of the project quickly.

[0127] Corresponding to the above analysis method of the digital circuit, at least one embodiment of the present disclosure further provides an analysis device for a digital circuit. Figure 5 It is a schematic block diagram of an analysis device for a digital circuit provided by at least one embodiment of the present disclosure.

[0128] For example, as Figure 5 shown, the analysis device 500 of the digital circuit includes: a processing unit 501, an extraction unit 502, and an integration unit 503.

[0129] The processing unit 501 is configured to process the first synthesis file corresponding to the digital circuit to obtain a second synthesis file, where the first synthesis file includes a plurality of first instances, the second synthesis file includes a plurality of second instances, and the processing includes performing re-partitioning processing on the plurality of first instances to obtain a plurality of second instances.

[0130] The extraction unit 502 is configured to extract multiple waveform sub-files corresponding to multiple second instances respectively from the first waveform file corresponding to the first integrated file.

[0131] The integration unit 503 is configured to integrate multiple waveform sub-files based on the second-level structure to obtain a second waveform file corresponding to the second integrated file.

[0132] For example, the re-partitioning process includes a combination operation and an un-partitioning operation. When the processing unit 501 performs a re-partitioning process on multiple first instances to obtain multiple second instances, the following operations are included: performing a combination operation on at least one first instance to obtain a third instance; or, performing an un-partitioning operation on a first instance to obtain at least two second instances.

[0133] For example, when the extraction unit 502 performs the extraction of multiple waveform sub-files corresponding to multiple second instances respectively from the first waveform file corresponding to the first integrated file, the following operations are included: determining the correspondence relationship of multiple second instances in the first integrated file; based on the correspondence relationship, extracting multiple waveform sub-files corresponding to multiple second instances respectively from the first waveform file.

[0134] For example, when the extraction unit 502 performs the extraction of multiple waveform sub-files corresponding to multiple second instances respectively from the first waveform file based on the correspondence relationship, the following operations are included: for each second instance among multiple second instances: based on the correspondence relationship, determining the first instance corresponding to the second instance; extracting the associated waveform corresponding to the first instance from the first waveform file; according to the hierarchical relationship of the second instance in the second-level structure, adjusting the hierarchical relationship of the associated waveform to obtain the waveform sub-file corresponding to the second instance, where the hierarchical relationship of the waveform sub-file is the same as the hierarchical relationship of the second instance in the second-level structure.

[0135] For example, when the integration unit 503 performs the integration of multiple waveform sub-files based on the second-level structure to obtain a second waveform file corresponding to the second integrated file, the following operations are included: combining multiple waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to the second instance in the second-level structure to obtain an intermediate waveform file; according to the second-level structure, establishing a state element mapping relationship for the instance to be adjusted, where the instance to be adjusted includes at least one third instance or M second instances obtained by an un-partitioning operation, and M is a positive integer greater than 1; based on the intermediate waveform file and the state element mapping relationship, obtaining the second waveform file.

[0136] For example, when the instance to be adjusted includes at least one third instance, when the integration unit 503 establishes a state element mapping relationship for the instance to be adjusted according to the second hierarchy, the following operations are included: determining at least one second instance that constitutes at least one third instance according to the hierarchical relationship of at least one third instance in the second hierarchy; obtaining all state elements of at least one second instance according to the second comprehensive document; and establishing a state element mapping relationship for at least one third instance according to the first comprehensive document and all state elements of at least one second instance.

[0137] For example, when the instance to be adjusted includes M second instances, when the integration unit 503 establishes a state element mapping relationship for the instance to be adjusted according to the second hierarchy, the following operations are included: obtaining all state elements of M second instances according to the second comprehensive document; and establishing a state element mapping relationship for M second instances according to the first comprehensive document and all state elements of M second instances.

[0138] For example, when both the first comprehensive document and the second comprehensive document are front-end netlists, the digital circuit design device 500 further includes a power consumption analysis unit (not shown).

[0139] For example, the power consumption analysis unit is configured to: obtain a register transfer level description file corresponding to the second comprehensive document; and perform gate-level power consumption analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive document, the second comprehensive document, and the second waveform file.

[0140] For example, when the power consumption analysis unit performs gate-level power consumption analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive document, the second comprehensive document, and the second waveform file, the following operations are included: performing a one-to-one mapping between the register transfer level description file corresponding to the second comprehensive document and the timing devices in the second comprehensive document to obtain a mapping relationship; and performing parallel simulation analysis on the combinational logic between the timing devices according to the second waveform file and the mapping relationship to obtain the gate-level power consumption analysis result of the digital circuit.

[0141] For example, the processing unit 501, the extraction unit 502, and the integration unit 503 include code and programs stored in a memory; the processor can execute the code and programs to implement some or all of the functions of the processing unit 501, the extraction unit 502, and the integration unit 503 as described above. For example, the processing unit 501, the extraction unit 502, and the integration unit 503 can be dedicated hardware devices for implementing some or all of the functions of the processing unit 501, the extraction unit 502, and the integration unit 503 as described above. For example, the processing unit 501, the extraction unit 502, and the integration unit 503 can be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiments of the present application, the combination of the one circuit board or multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memory and executable by the processors.

[0142] It should be noted that the processing unit 501 is used to implement Figure 2 the step S10 shown, the extraction unit 502 is used to implement Figure 2 the step S20 shown, and the integration unit 503 is used to implement Figure 2 the step S30 shown. Therefore, the specific description of the processing unit 501 can refer to the relevant description of the step S10 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown, the specific description of the extraction unit 502 can refer to the relevant description of the step S20 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown, and the specific description of the integration unit 503 can refer to the relevant description of the step S30 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown.

[0143] In addition, the analysis device of the digital circuit can achieve technical effects similar to those of the foregoing analysis method of the digital circuit, which will not be elaborated herein.

[0144] At least one embodiment of the present disclosure further provides an electronic device, Figure 6 which is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0145] For example, as Figure 6 shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004, and components such as the processor 1001, the communication interface 1002, and the memory 1003 can also communicate through a network connection. The present disclosure does not limit the type and function of the network herein.

[0146] For example, the memory 1003 is used to non-transiently store computer-executable instructions. When the processor 1001 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 1001, implement the analysis method of the digital circuit according to any of the foregoing embodiments. For the specific implementation and related explanatory content of each step of the analysis method of the digital circuit, reference may be made to the embodiments of the analysis method of the digital circuit above, which will not be elaborated here.

[0147] For example, the implementation manner in which the processor 1001 executes the program stored on the memory 1003 to implement the analysis method of the digital circuit is the same as the implementation manner mentioned in the embodiment part of the foregoing analysis method of the digital circuit, and will not be elaborated here either.

[0148] For example, the communication bus 1004 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of easy representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0149] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0150] For example, the processor 1001 can control other components in the electronic device to perform desired functions. The processor 1001 may be a Central Processing Unit (CPU), a Network Processor (NP), etc., and may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The Central Processing Unit (CPU) may be of the X86 or ARM architecture, etc.

[0151] For example, the memory 1003 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may, for example, include Random Access Memory (RAM) and / or cache memory, etc. Non-volatile memory may, for example, include Read Only Memory (ROM), hard disk, Erasable Programmable Read Only Memory (EPROM), Portable Compact Disc Read Only Memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage media, and the processor 1001 may run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data, etc. may also be stored in the storage media.

[0152] For example, for a detailed description of the process of an electronic device performing the analysis of a digital circuit, reference may be made to the relevant descriptions in the embodiments of the method for analyzing a digital circuit, and repeated parts will not be elaborated herein.

[0153] Figure 7 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 7 shown, one or more computer-executable instructions 1101 can be non-temporarily stored on the storage medium 1100. For example, when the computer-executable instructions 1101 are executed by a processor, one or more steps in the method for analyzing a digital circuit described above can be executed.

[0154] For example, the storage medium 1100 can be applied to the above-mentioned electronic device and / or the analysis device 500 of the digital circuit. For example, the storage medium 1100 can include the memory 1003 in the electronic device.

[0155] For example, for the description of the storage medium 1100, reference may be made to the description of the memory in the embodiments of the electronic device, and repeated parts will not be elaborated herein.

[0156] For the present disclosure, the following points need to be noted:

[0157] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0158] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness and size of layers or structures are enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intermediate elements.

[0159] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0160] The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for analyzing a digital circuit, comprising: Processing a first synthesis file corresponding to the digital circuit to obtain a second synthesis file, wherein the first synthesis file includes a plurality of first instances, the second synthesis file includes a plurality of second instances, and the processing includes re - partitioning the plurality of first instances to obtain the plurality of second instances; Extracting a plurality of waveform sub - files respectively corresponding to the plurality of second instances from a first waveform file corresponding to the first synthesis file; Integrating the plurality of waveform sub - files based on a second hierarchical structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file.

2. The analysis method according to claim 1, wherein A first hierarchical structure of the first synthesis file is different from the second hierarchical structure of the second synthesis file.

3. The analysis method according to claim 1 or 2, wherein The first synthesis file includes a register transfer level description file or a front - end netlist, and the second synthesis file includes a register transfer level description file, a front - end netlist, or a back - end netlist.

4. The analysis method according to claim 1 or 2, wherein Each second instance has a corresponding first instance. Extracting a plurality of waveform sub - files respectively corresponding to the plurality of second instances from a first waveform file corresponding to the first synthesis file includes: Determining a correspondence of the plurality of second instances in the first synthesis file; Based on the correspondence, extracting a plurality of waveform sub - files respectively corresponding to the plurality of second instances from the first waveform file.

5. The analysis method according to claim 4, wherein Based on the correspondence, extracting a plurality of waveform sub - files respectively corresponding to the plurality of second instances from the first waveform file includes: For each of the plurality of second instances: Based on the correspondence, determining a first instance corresponding to the second instance; Extracting an associated waveform corresponding to the first instance from the first waveform file; Adjusting a hierarchical relationship of the associated waveform according to a hierarchical relationship of the second instance in the second hierarchical structure to obtain a waveform sub - file corresponding to the second instance, wherein a hierarchical relationship of the waveform sub - file is the same as a hierarchical relationship of the second instance in the second hierarchical structure.

6. The analysis method according to claim 1 or 2, wherein Integrating the plurality of waveform sub - files based on a second hierarchical structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file includes: Combining the plurality of waveform sub - files according to a hierarchical relationship of each waveform sub - file corresponding to a second instance in the second hierarchical structure to obtain the second waveform file, wherein a hierarchical structure of the second waveform file is the same as the second hierarchical structure.

7. The analysis method according to claim 1 or 2, wherein, The re - partitioning process includes a combination operation and an un - partitioning operation. The second synthesis file further includes at least one third instance. Processing the plurality of first instances to re - partition them to obtain the plurality of second instances includes: Performing the combination operation on at least one first instance to obtain one third instance; or, Performing the un - partitioning operation on one first instance to obtain at least two second instances.

8. The analysis method according to claim 7, wherein, Integrating the plurality of waveform sub - files based on a second hierarchical structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file includes: Combining the multiple waveform sub-files according to the hierarchical relationship of each waveform sub-file corresponding to the second instance in the second hierarchy to obtain an intermediate waveform file; Establishing a state element mapping relationship for the instance to be adjusted according to the second hierarchy, where the instance to be adjusted includes the at least one third instance or the M second instances obtained by the cancellation division operation, and M is a positive integer greater than 1; Obtaining the second waveform file based on the intermediate waveform file and the state element mapping relationship.

9. The analysis method according to claim 8, wherein, Establishing a state element mapping relationship for the instance to be adjusted according to the second hierarchy, including: Determining at least one second instance that constitutes the at least one third instance according to the hierarchical relationship of the at least one third instance in the second hierarchy; Obtaining all state elements of the at least one second instance according to the second comprehensive file; Establishing a state element mapping relationship for the at least one third instance according to the first comprehensive file and all state elements of the at least one second instance.

10. The analysis method according to claim 8, wherein, Establishing a state element mapping relationship for the instance to be adjusted according to the second hierarchy, including: Obtaining all state elements of the M second instances according to the second comprehensive file; Establishing a state element mapping relationship for the M second instances according to the first comprehensive file and all state elements of the M second instances.

11. The analysis method according to claim 9, wherein, The state element includes an input port. Establishing a state element mapping relationship for the at least one third instance according to the first comprehensive file and all state elements of the at least one second instance, including: For each third instance in the at least one third instance, determining N second instances that constitute the third instance, where N is a positive integer; Determining the fan-in corresponding to all input ports of the N second instances according to the first comprehensive file; Establishing a mapping relationship between the fan-in and all input ports of the N second instances to establish a state element mapping relationship for the third instance.

12. The analysis method according to claim 3, wherein When both the first comprehensive file and the second comprehensive file are front-end netlists, the analysis method further includes: Obtaining a register transfer level description file corresponding to the second comprehensive file; Performing gate-level power analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive file, the second comprehensive file, and the second waveform file.

13. The analysis method according to claim 12, wherein, Performing gate-level power analysis on the digital circuit based on the register transfer level description file corresponding to the second comprehensive file, the second comprehensive file, and the second waveform file, including: Performing a one-to-one mapping between the register transfer level description file corresponding to the second comprehensive file and the timing devices in the second comprehensive file to obtain a mapping relationship; Performing a simulation analysis on the combinational logic between the timing devices in parallel according to the second waveform file and the mapping relationship to obtain the gate-level power analysis result of the digital circuit.

14. An analysis device for a digital circuit, including: A processing unit, configured to process a first synthesis file corresponding to the digital circuit to obtain a second synthesis file, where the first synthesis file includes a plurality of first instances, the second synthesis file includes a plurality of second instances, and the processing includes performing a re-partitioning process on the plurality of first instances to obtain the plurality of second instances; An extraction unit, configured to extract a plurality of waveform sub-files respectively corresponding to the plurality of second instances from a first waveform file corresponding to the first synthesis file; An integration unit, configured to integrate the plurality of waveform sub-files based on a second hierarchical structure of the second synthesis file to obtain a second waveform file corresponding to the second synthesis file.

15. An electronic device, comprising: A memory that non-transiently stores computer-executable instructions; A processor, configured to run the computer-executable instructions, wherein when the computer-executable instructions are run by the processor, a design method of the digital circuit according to any one of claims 1-13 is implemented.

16. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, a design method of the digital circuit according to any one of claims 1-13 is implemented.

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