Memory system

Abstract

A memory system includes a nonvolatile memory, a controller configured to control the nonvolatile memory, a connector capable of electrically connecting the controller with a host, a first rigid substrate on which the nonvolatile memory and the controller are mounted, a second rigid substrate on which the connector is mounted, and a flexible substrate that is flexible and electrically connects the first rigid substrate with the second rigid substrate, wherein a thickness of the first rigid substrate is smaller than a thickness of the second rigid substrate.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-007161, filed January 20, 2021, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments described herein generally relate to a memory system. BACKGROUND

[0004] A memory system includes a connector portion for connecting to a host via a socket, and a component mounting portion on which a non-volatile memory and a controller are mounted. When the memory system is used, the memory system is mounted on a mother substrate with the connector portion inserted into a socket on the mother substrate. The thickness of a substrate including the connector portion and the component mounting portion is determined by a standard, and the socket is fabricated assuming that the thickness of the substrate is determined by the standard. For example, according to the standard PCI_Express_M.2_Specification, the thickness of the substrate is 0.8 mm. Since the mounting space of the memory system is limited, it is desirable to reduce the overall thickness when the memory system is mounted on the mother substrate. SUMMARY

[0005] Embodiments provide a memory system having a substrate thickness determined by a standard and a reduced overall thickness when mounted on a mother substrate.

[0006] An embodiment provides,

[0007] A memory system includes:

[0008] a non-volatile memory;

[0009] a controller configured to control the non-volatile memory;

[0010] a connector configured to electrically connect the controller with a host;

[0011] a first rigid substrate on which the non-volatile memory and the controller are mounted;

[0012] a second rigid substrate on which the connector is mounted; and

[0013] a flexible substrate that is flexible and electrically connects the first rigid substrate with the second rigid substrate, wherein

[0014] a thickness of the first rigid substrate is smaller than a thickness of the second rigid substrate.

[0015] Further, one embodiment provides,

[0016] An information processing system including:

[0017] a host including a socket and a mother substrate on which the socket is mounted; and

[0018] a memory system mounted on the mother substrate, wherein the memory system includes: a nonvolatile memory; a controller configured to control the nonvolatile memory; a connector configured to electrically connect the controller with the host through the socket; a first rigid substrate on which the nonvolatile memory and the controller are mounted; a second rigid substrate on which the connector is mounted; and a flexible substrate that is flexible and electrically connects the first rigid substrate with the second rigid substrate, wherein a thickness of the first rigid substrate is smaller than a thickness of the second rigid substrate. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a view schematically showing a part of a configuration of an information processing system including a memory system according to a first embodiment.

[0020] Figure 2 is a plan view of a memory system according to the first embodiment.

[0021] Figure 3 is a cross-sectional view of a memory system according to the first embodiment.

[0022] Figure 4 is a cross-sectional view showing a part of a configuration of an information processing system, in which a memory system according to the first embodiment is mounted on a mother substrate.

[0023] Figure 5 is a cross-sectional view of a connecting portion between a first rigid substrate and a flexible substrate of a memory system according to the first embodiment.

[0024] Figure 6 is a cross-sectional view of a connecting portion between a second rigid substrate and a flexible substrate of a memory system according to the first embodiment.

[0025] Figure 7A and 7B is a cross-sectional view of a modified memory system according to the first embodiment.

[0026] Figure 8 is a cross-sectional view of a memory system according to a second embodiment.

[0027] Figure 9 is a plan view of a memory system according to a third embodiment.

[0028] Figure 10 is a cross-sectional view showing a partial configuration of an information processing system in which a memory system according to a third embodiment is mounted on a mother substrate.

[0029] Figure 11 is a cross-sectional view showing a partial configuration of an information processing system in which a memory system according to a fourth embodiment is disposed on a mother substrate.

[0030] Figure 12 is a cross-sectional view of a memory system according to a fifth embodiment. DETAILED DESCRIPTION

[0031] Embodiments provide a memory system having a substrate thickness determined by a standard and a reduced overall thickness when mounted on a mother substrate.

[0032] Generally, according to one embodiment, a memory system includes a nonvolatile memory, a controller configured to control the nonvolatile memory, a connector capable of electrically connecting the controller with a host, a first rigid substrate on which the nonvolatile memory and the controller are mounted, a second rigid substrate on which the connector is mounted, and a flexible substrate that is flexible and electrically connects the first rigid substrate with the second rigid substrate, wherein a thickness of the first rigid substrate is smaller than a thickness of the second rigid substrate.

[0033] Hereinafter, embodiments of the present disclosure will be described.

[0034] In this specification, a variety of expressions are given to a plurality of elements as examples. The examples are not limited and other expressions can be given to the elements. Further, another expression can be given to an element to which a variety of expressions are not given.

[0035] The drawings are schematic, and the relationship between the thickness and the planar dimension, the proportion of the thickness of each layer, and the like can differ from the actual situation. In addition, there can be parts in which the dimensional relationship and the proportion differ in the drawings.

[0036] (First Embodiment)

[0037] Figures 1 to 6 A memory system according to the first embodiment is shown. The memory system 1 is an example of a semiconductor device. This memory system 1 is mounted on an electronic device such as a personal computer (PC) or a mobile phone and used as a storage device of the electronic device. The electronic device is also called a host.

[0038] Next, the configuration of the memory system 1 will be described.

[0039] Figure 1 is a block diagram showing an example of the configuration of an information processing system 110. The information processing system 110 includes the memory system 1 and a host 13.

[0040] The memory system 1 includes a controller 11 and a nonvolatile memory 12. In addition to these, the memory system 1 includes, for example, a DRAM, a host interface (host I / F), and an electrically erasable and programmable ROM (EEPROM), but these are not shown here.

[0041] The controller 11 is a semiconductor integrated circuit that controls the operation of the nonvolatile memory 12.

[0042] The nonvolatile memory 12 is, for example, a NAND-type flash memory chip (NAND). The nonvolatile memory 12 is capable of holding data therein when power is not supplied.

[0043] The controller 11 and the nonvolatile memory 12 are each a chip or a package.

[0044] The substrate on which the controller 11 and the nonvolatile memory 12 are mounted is connected to the connector 5 via the flexible substrate 4. The host 13 is provided with the socket 6. By connecting the socket 6 and the connector 5, the memory system 1 is connected to the host 13.

[0045] For the communication interface of the host 13 and the memory system 1, standards such as Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), and Peripheral Component Interconnect Express (PCIe) can be used.

[0046] Next, the structure of the memory system 1 according to the first embodiment will be described. Figure 2 is a plan view of the memory system, and Figure 3 is a cross-sectional view of the memory system 1.

[0047] As shown in Figure 2 , the memory system 1 includes a first rigid substrate 2, a second rigid substrate 3, and a flexible substrate 4. The first rigid substrate 2 and the second rigid substrate 3 each include a hard insulator and a conductive pattern provided on the insulator. The first rigid substrate 2 and the second rigid substrate 3 in the present embodiment are composed of a single-layer substrate, but can be composed of a multi-layer substrate.

[0048] The first rigid substrate 2 and the second rigid substrate 3 are disposed such that their main surfaces are substantially parallel to each other. The second rigid substrate 3 faces the first rigid substrate 2 in the X direction. The first rigid substrate 2 and the second rigid substrate 3 are connected with the flexible substrate 4. The flexible substrate 4 is a flexible printed circuit (FPC). The flexible substrate 4 includes, for example, a flexible insulating film and a conductive pattern covered with the insulating film.

[0049] Figure 3 is a cross-sectional view as viewed from the dotted line A-A' of Figure 2 . In Figure 3 ​The diagram illustrates the +X, -X, +Z, and -Z directions. The +X direction is parallel to the main surface of the mother substrate 8, described later, and is the direction from the non-volatile memory 12 toward the controller 11. The -X direction is opposite to the +X direction. When not distinguishing between the +X and -X directions, this direction is simply referred to as the "X direction." The +Y direction is parallel to the main surface of the mother substrate 8 and intersects the X direction (for example, substantially orthogonal to the X direction). The -Y direction is opposite to the +Y direction. When not distinguishing between the +Y and -Y directions, this direction is simply referred to as the "Y direction." The +Z direction is perpendicular to the main surfaces of the first rigid substrate 2 and the second rigid substrate 3, intersects the X and Y directions (for example, substantially orthogonal to each other), and is the direction along which the controller 11 is spaced from the mother substrate 8. The -Z direction is opposite to the +Z direction. When not distinguishing between the +Z and -Z directions, this direction is simply referred to as the "Z direction." For example, the Z direction is the thickness direction of the mother substrate 8. The directions described above will be described later. Figures 4 to 6 The same applies to 8 to 12.

[0050] Furthermore, the first rigid substrate 2 includes a first main surface S1, a second main surface S2, a third surface S3, and a fourth surface S4. The first main surface S1 is a surface parallel to the X-direction and facing the inner surface of the housing. For example, a semiconductor assembly including a controller 11 and a non-volatile memory 12 is mounted on the first main surface S1 using a ball grid array (BGA). The second main surface S2 is located on the opposite side of the first main surface S1 and faces the mother substrate 8. The mother substrate 8 is the substrate of the host 13, on which the memory system 1 is mounted. The third surface S3 is a surface perpendicular to the first main surface S1 and the second main surface S2 and parallel to the Z-direction. The third surface S3 is the surface to which the flexible substrate 4 is connected. The third surface S3 includes a connection portion 21 to which the flexible substrate 4 is connected. For example, the connection portion 21 is disposed at an end portion of the first rigid substrate 2 on the +X direction side. The fourth surface S4 is the surface opposite to the third surface S3. The thickness of the first rigid substrate 2 is thinner than the thickness of the second rigid substrate 3.

[0051] Furthermore, the second rigid substrate 3 includes a fifth main surface S5, a sixth main surface S6, a seventh surface S7, and an eighth surface S8. The fifth main surface S5 is parallel to the X-direction and faces the inner surface of the outer casing. The sixth main surface S6 is located on the opposite side of the fifth main surface S5 and faces the mother substrate 8. The fifth and sixth main surfaces S5 and S6 include connectors 5, which are connection portions connected to the host 13. The seventh surface S7 is the surface to which the flexible substrate 4 is connected, and includes a connection portion 31 to which the flexible substrate 4 is connected. For example, the connection portion 31 is disposed at the end portion of the second rigid substrate 3 on the -X direction side. The eighth surface S8 is located on the opposite side of the seventh surface S7. For example, the thickness of the second rigid substrate 3 is 0.8 mm. For example, components such as the controller 11 and the non-volatile memory 12 are not mounted on the second rigid substrate.

[0052] Next, the structure of the information processing system in which the memory system according to the first embodiment is mounted on the mother substrate will be described. Figure 4 This is a cross-sectional view showing a portion of the configuration of the information processing system 110, wherein the memory system of an embodiment of the present invention is mounted on a mother substrate.

[0053] like Figure 4 As shown, the memory system 1 is inserted into the socket 6 and mounted on the mother substrate 8, and the information processing system 110 includes the memory system 1, the socket 6, and the mother substrate 8. The memory system 1 is disposed on a spacer 82 disposed on the mother substrate 8. The flexible substrate 4 includes Figure 5 The first end portion 41a shown in the figure and Figure 6 The second end portion 41b is shown in the diagram. The first end portion 41a is fixed to the connection portion 21 on the third surface S3 (side surface of the first rigid substrate 2) of the first rigid substrate 2. The second end portion 41b is fixed to the connection portion 31 on the seventh surface S7 (side surface of the second rigid substrate 3) of the second rigid substrate 3. The flexible substrate 4 is flexible. The flexible substrate 4 connects the first rigid substrate 2 and the second rigid substrate 3 when in a twisted (e.g., bent) posture (for example). The first rigid substrate 2 and the second rigid substrate 3 are electrically connected to each other via the flexible substrate 4. The flexible substrate 4 is an example of a "connecting substrate". The structure of the flexible substrate 4 fixed to the first rigid substrate 2 and the second rigid substrate 3 will be described later. The second rigid substrate 3 is inserted into the socket 6 of the host 13 in the X direction. The host 13 and the memory system 1 are electrically connected through the contact between the metal terminals (not shown) in the socket 6 and the connector 5. The seventh surface S7 is a surface perpendicular to the fifth main surface S5 and the sixth main surface S6 and parallel to the Z direction. The eighth surface S8 is the surface that will be inserted into the socket 6.

[0054] When the memory system 1 is mounted on the mother substrate 8, the position of the first main surface S1 of the first rigid substrate is lower than the position of the fifth main surface S5 of the second rigid substrate. Furthermore, the positions of the upper surfaces of the controller 11 and the non-volatile memory 12 are lower than the positions of the upper surface of the socket 6.

[0055] Figure 5 This is a cross-sectional view showing the connection portion 21 between the flexible substrate 4 and the first rigid substrate 2. Figure 6 This is a cross-sectional view showing the connection portion 31 between the flexible substrate 4 and the second rigid substrate 3.

[0056] Reference Figure 5 The connection between the first rigid substrate 2 and the flexible substrate 4 is described. The connection portion 21 of the first rigid substrate 2 is recessed toward the center of the substrate. A conductive portion 22 is disposed along the recessed portion. The flexible substrate 4 is connected to a portion of the conductive portion 22 that is substantially parallel to the Z direction (e.g., substantially perpendicular). The region of the connection portion 21 between the flexible substrate 4 and the conductive portion 22 is filled with an insulating member 26.

[0057] The flexible substrate 4 is situated in a state where conductive layers 43 and insulating layers 42 are alternately stacked. The outer side of the flexible substrate 4 is covered by an insulating layer 44, which acts as a cover. The insulating layer 44 is attached to the conductive layer 43 by means of an adhesive component 45.

[0058] Wiring 23, resist 24, controller 11, and non-volatile memory 12 are disposed on the first main surface S1 of the first rigid substrate 2. Semiconductor components such as controller 11, non-volatile memory 12, and wiring 23 located on the first main surface S1 are electrically connected. Resist 24 covers wiring 23. Alternatively, wiring 23 and resist 24 may be similarly disposed on the second main surface S2 of the first rigid substrate 2.

[0059] The via 25 is configured to extend in the Z direction from the wiring 23 toward the conductive portion 22 and electrically connect the wiring 23 on the first main surface S1 and the second main surface S2 to the conductive portion 22. Through the via 25, the semiconductor component is electrically connected to the flexible substrate 4.

[0060] Reference Figure 6 The connection between the second rigid substrate 3 and the flexible substrate 4 is described. The connection portion 31 of the second rigid substrate 3 is recessed toward the center of the substrate, similar to the first rigid substrate 2. A conductive portion 32 is provided along the recessed portion. The flexible substrate 4 is connected to a portion of the conductive portion 32 that is substantially parallel to the Z direction (e.g., substantially perpendicular). The region of the connection portion 31 between the flexible substrate 4 and the conductive portion 32 is filled with an insulating portion 36.

[0061] Wiring 33, resist 34, and connector 5 are disposed on the fifth main surface S5 of the second rigid substrate 3. Resist 34 covers wiring 33. Connector 5 is a metal terminal and is referred to as a gold finger. The second rigid substrate 3 is inserted into the socket 6 of the host 13 in the X direction. The host 13 and the memory system 1 are electrically connected via contact between the metal terminal (not shown) in the socket 6 and connector 5. Connector 5 on the fifth main surface S5 is electrically connected to wiring 33. Furthermore, wiring 33 and resist 34 can similarly be disposed on the sixth main surface S6 of the second rigid substrate 3.

[0062] The through-hole 35 is configured to extend in the Z direction from the wiring 33 toward the conductive portion 32 and electrically connect the wiring 33 on the fifth main surface S5 and the sixth main surface S6 to the conductive portion 32. Through the through-hole 35, the connector 5 is electrically connected to the flexible substrate 4.

[0063] According to an embodiment of the present invention, the memory system 1 achieves a thickness value (0.8 mm for an M.2 module) set by a standard for the second rigid substrate 3 by physically and electrically connecting a first rigid substrate 2 and a second rigid substrate 3 with a different thickness using a flexible substrate 4. Furthermore, the thickness of the first rigid substrate 2 on which components are mounted can be thinner than the standard thickness value, and the overall thickness of the memory system 1 when mounted on the mother substrate 8 can be thinner. Because the flexible substrate 4 is flexible, excessive load is avoided, and it is possible to reliably physically and electrically connect the first rigid substrate 2 and the second rigid substrate 3.

[0064] (Revise)

[0065] Next, modifications to the memory system according to the first embodiment will be described.

[0066] Figure 7A and 7B This is a cross-sectional view of the first rigid substrate 2 of the modified memory system. In the first embodiment, as... Figure 7A As shown, semiconductor components 101 (e.g., controller 11 and non-volatile memory 12) are mounted on the first rigid substrate 2 using a BGA. In modifications, such as... Figure 7B As shown, the semiconductor component 101 is mounted on the first rigid substrate 2 using a pad grid array (LGA). While a BGA uses solder balls to attach the bottom surface of the semiconductor component 101 to the first rigid substrate 2, an LGA uses solder paste to attach the bottom surface of the semiconductor component 101 to the first rigid substrate 2. Compared to a BGA, an LGA has a smaller gap between the semiconductor component 101 and the first rigid substrate 2. This allows for further reduction in the thickness of the memory system 1 through modifications.

[0067] (Second Embodiment)

[0068] Next, the structure of the memory system according to the second embodiment will be described.

[0069] Figure 8 This is a cross-sectional view showing a portion of the configuration of the information processing system 110 according to an embodiment of the present invention.

[0070] For each part of the memory system 1 of the second embodiment, the parts that are the same as each part of the memory system 1 of the first embodiment are indicated by the same reference numerals. For example... Figure 8 As shown, the memory system 1 according to the second embodiment differs from the first embodiment in that the semiconductor package 7 is mounted on the first main surface S1 of the first rigid substrate 2. The semiconductor package 7 is an example of a semiconductor component. In the semiconductor package 7 according to an embodiment of the present invention, the controller 11 is integrated with at least one non-volatile memory 12 into a single package. The semiconductor package 7 is mounted on the first rigid substrate 2 in the form of a BGA (for example).

[0071] The controller 11 and at least one non-volatile memory 12 are interconnected via wiring in the semiconductor package 7. Therefore, it is unnecessary to provide wiring on the first rigid substrate 2 for connecting the controller 11 and the at least one non-volatile memory 12. By mounting the semiconductor package 7 on the first rigid substrate 2 instead of mounting the controller 11 and at least one non-volatile memory 12 on the first rigid substrate 2, the wiring of the first rigid substrate 2 is simplified. Therefore, the thickness of the first rigid substrate 2 can be reduced, and the thickness of the memory system 1 can also be reduced.

[0072] (Third Embodiment)

[0073] Next, the structure of the memory system according to the third embodiment will be described.

[0074] Figure 9 This is a top view of the memory system 1 according to the third embodiment. Figure 10 This is a cross-sectional view showing a portion of the configuration of the information processing system 110, wherein the memory system of an embodiment of the present invention is mounted on a mother substrate.

[0075] For each part of the memory system 1 of the third embodiment, the parts that are the same as each part of the memory system 1 of the first embodiment are indicated by the same reference numerals. The memory system 1 according to the third embodiment differs from that of the first embodiment in that screws 9A to 9D are used as components for fixing the first rigid substrate 2 to the mother substrate 8 on which the memory system 1 is mounted.

[0076] In the third embodiment, four screw holes are located at the four corners of the mother substrate 8. Figure 10The image shows two of the four screw holes: screw holes 81A and 81D. For example... Figure 9 As shown, through holes 26A to 26D are located at the four corners of the first rigid substrate 2. Screws 9A can be inserted into the through holes 26A. Screws 9A to 9D are made of metal, and the thermal conductivity of screws 9A to 9D is higher than that of the first rigid substrate 2.

[0077] Figure 10 From Figure 9 The cross-sectional view viewed through the dashed line B-B'. (See figure.) Figure 10 As shown, memory system 1 is mounted on spacer 82, which is disposed on the ninth main surface S9 of the mother substrate 8, and the height of the spacer is defined by the M.2 standard. Controller 11 and non-volatile memory 12 are disposed on the first main surface S1 of the first rigid substrate 2. Screw 9A penetrates the first rigid substrate 2 in the Z direction, reaches the mother substrate 8, and is attached to a screw hole 81A disposed in the mother substrate 8. Screw 9A can be inserted into and engages with screw hole 81A. Screw 9B is inserted into and engages with screw hole 26B through through hole 26B. Screw 9C is inserted into and engages with screw hole 26C through through hole 26C. Screw 9D is inserted into and engages with screw hole 81D through through hole 26D.

[0078] A gap is formed between the first rigid substrate 2 and the mother substrate 8 by spacer 82. Heat generated by the controller 11 and non-volatile memory 12 on the first rigid substrate 2 is not directly transferred from the first rigid substrate 2 to the mother substrate 8. By securing the first rigid substrate 2 with screws 9, heat generated by the controller 11 and non-volatile memory 12 is sequentially transferred to the first rigid substrate 2, screws 9, and mother substrate 8, and then released. This prevents an increase in the temperature of the first rigid substrate 2. The number of screws 9 is not limited to four, and three or more screws may be provided.

[0079] (Fourth Embodiment)

[0080] Next, the structure of the memory system according to the fourth embodiment will be described.

[0081] Figure 11 This is a cross-sectional view showing a portion of the configuration of the information processing system 110, wherein the memory system of an embodiment of the present invention is mounted on a mother substrate.

[0082] For each part of the memory system 1 of the fourth embodiment, the parts that are the same as those of the memory system of the third embodiment are indicated by the same reference numerals. The memory system 1 according to the fourth embodiment differs from that of the third embodiment in that a thermal interface material (TIM) is used as a component for fixing the first rigid substrate 2 to the mother substrate 8 on which the memory system 1 is mounted.

[0083] The controller 11 and the non-volatile memory 12 are disposed on the first main surface S1 of the first rigid substrate 2. The TIM 10 is disposed between the second main surface S2 of the first rigid substrate 2 and the ninth main surface S9 of the mother substrate 8. That is, the first rigid substrate 2 and the mother substrate 8 are bonded together by the TIM 10. The TIM 10 is a heat dissipation material with high thermal conductivity and may be made of grease, elastomer sheets, room temperature vulcanization (RTV), gel, etc. For example, the TIM 10 is a plate-shaped heat dissipation component.

[0084] The heat generated by the controller 11 and the non-volatile memory 12 on the first rigid substrate 2 is sequentially transferred to the first rigid substrate 2, the TIM 10, and the mother substrate 8 and then released. Therefore, it is possible to efficiently transfer heat from the first rigid substrate 2 and prevent an increase in its temperature. Furthermore, by using a first rigid substrate 2 with a reduced thickness in a combined manner, even with the TIM 10 provided, the total thickness of the first rigid substrate 2 and the TIM 10 does not exceed the thickness of the second rigid substrate 3. That is, the position of the first main surface S1 of the first rigid substrate is not higher than the position of the fifth main surface S5 of the second rigid substrate. It is possible to efficiently dissipate heat from the controller 11 and the non-volatile memory 12 while reducing the thickness of the memory system 1.

[0085] (Fifth Embodiment)

[0086] Next, the structure of the memory system according to the fifth embodiment will be described. Electromagnetic waves generated from the semiconductor component 101 mounted on the memory system 1 can cause the electronic device to malfunction. The memory system 1 mounted on the electronic device needs to have the characteristic of emitting as few electromagnetic waves as possible. In addition, the memory system 1 also needs to have the characteristic of not malfunctioning due to the influence of electromagnetic waves from other components mounted on the electronic device.

[0087] Figure 12 This is a cross-sectional view of the memory system 1 according to the fifth embodiment. For each part of the memory system 1 of the fifth embodiment, the same parts as each part of the memory system 1 of the first embodiment are indicated by the same reference numerals. The memory system 1 according to the fifth embodiment differs from that of the first embodiment in that the TIM 10 is disposed above the semiconductor assembly 101 mounted on the first rigid substrate 2, and the housing 111 covers the semiconductor assembly 101 and the TIM 10.

[0088] Semiconductor component 101 is disposed on the first main surface S1 of the first rigid substrate 2. Of the two main surfaces of semiconductor component 101, the surface opposite to the surface in contact with the first main surface S1 of the first rigid substrate 2 is designated as the tenth main surface S10. The tenth main surface S10 contacts TIM 10. The length of TIM 10 in the X direction is the same as the length of the tenth main surface S10 of semiconductor component 101 in the X direction. The length of TIM 10 in the Y direction is the same as the length of the tenth main surface S10 of semiconductor component 101 in the Y direction. Pad 112 is disposed on the first rigid substrate 2 to surround semiconductor component 101. Pad 112 is a conductor. Furthermore, housing 111 covers TIM 10 and semiconductor component 101. Housing 111 consists of a top plate 113 and four side plates 114. Side plates 114 are connected to the top plate 113. Side plates 114 have one end in contact with the top plate 113 in the +Z direction and another end in contact with pad 112 in the -Z direction. The height of the side plate 114 in the Z direction is greater than the thickness of the semiconductor component 101 in the Z direction. The length of the top plate 113 in the X direction is greater than the length of the tenth main surface of the semiconductor component 101 in the X direction. The length of the top plate 113 in the Y direction is greater than the length of the tenth main surface S10 of the semiconductor component 101 in the Y direction. The TIM 10 is disposed between the housing 111 and the semiconductor component 101. The TIM 10 fills the space between the semiconductor component 101 and the housing 111. The housing 111 is made of, for example, metal, ceramic, or plastic.

[0089] By providing a housing 111 to cover the semiconductor component 101, electromagnetic waves generated from the semiconductor component 101 are less likely to propagate to other electronic components. Furthermore, it is less susceptible to interference from electromagnetic waves from other components mounted on the electronic device. This allows for improved quality of the information processing system.

[0090] Furthermore, the heat generated by the semiconductor component 101 on the first rigid substrate 2 is sequentially transferred to the TIM 10 and the housing 111 and then released into the air. Alternatively, the generated heat is sequentially transferred to the TIM 10, the housing 111, the pad 112, and the mother substrate 8 and then released. Therefore, it is possible to efficiently transfer the heat from the first rigid substrate 2 and prevent the temperature of the first rigid substrate 2 from increasing. In addition, by using a first rigid substrate 2 with a reduced thickness in a combined manner, even with the TIM 10 provided, the total thickness of the first rigid substrate 2, TIM 10, semiconductor component 101, pad 112, and top plate 113 does not exceed the thickness of the socket 6. For example, the position of the first main surface S1 of the first rigid substrate is not higher than the position of the fifth main surface S5 of the second rigid substrate. For example, the position of the top plate 113 is not higher than the position of the upper surface of the socket 6. It is possible to efficiently dissipate the heat from the semiconductor component while reducing the thickness of the memory system 1.

[0091] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A memory system comprising: Non-volatile memory; A controller configured to control the non-volatile memory; A connector configured to electrically connect the controller to the host computer; A first rigid substrate on which the non-volatile memory and the controller are mounted; A second rigid substrate on which the connector is mounted; and A flexible substrate, which is flexible and electrically connects the first rigid substrate and the second rigid substrate, wherein... The thickness of the first rigid substrate is less than the thickness of the second rigid substrate. When the connector is inserted into the socket mounted on the mother substrate and the first rigid substrate is mounted on the mother substrate. The flexible substrate is curved, and the upper surface of the first rigid substrate is at a lower height from the surface of the parent substrate compared to the upper surface of the second rigid substrate. Compared to the upper surface of the socket, the upper surface of the first rigid substrate is at a lower height from the surface of the mother substrate. Compared to the upper surface of the socket, the upper surface of the second rigid substrate is at a lower height from the surface of the mother substrate.

2. The memory system according to claim 1, wherein The connector is disposed at one end of the second rigid substrate to connect with the socket mounted on the mother substrate.

3. The memory system according to claim 1, wherein No semiconductor components are mounted on the second rigid substrate.

4. The memory system according to claim 1, wherein The thickness of the second rigid substrate is defined by a predetermined form factor standard suitable for the memory system connected to the host.

5. The memory system according to claim 1, wherein The controller and the non-volatile memory are sealed in a single package.

6. The memory system according to claim 5, wherein The total thickness of the first rigid substrate and the package is less than the thickness of the socket to which the connector is connected.

7. The memory system according to claim 1, wherein The controller and the non-volatile memory are mounted on the first rigid substrate via a pad grid array (LGA).

8. The memory system according to claim 1, wherein The first rigid substrate has at least one screw hole, and the first rigid substrate can be attached to the mother substrate by using at least one screw inserted into and engaging the screw hole.

9. The memory system according to claim 1, further comprising: Plate-shaped heat dissipation components, among which The first rigid substrate is mounted on the heat dissipation component to contact it.

10. The memory system of claim 9, wherein The total thickness of the heat dissipation component and the first rigid substrate is less than the thickness of the second rigid substrate.

11. The memory system of claim 1, wherein The first rigid substrate and the electronic components mounted on the first rigid substrate are sealed by a housing.

12. An information processing system, comprising: The main unit includes a socket and a mother substrate on which the socket is mounted; and A memory system mounted on the mother substrate, wherein the memory system includes: non-volatile memory; A controller configured to control the non-volatile memory; A connector configured to electrically connect the controller to the host computer via the socket; a first rigid substrate on which the non-volatile memory and the controller are mounted; a second rigid substrate on which the connector is mounted; and a flexible substrate that is flexible and electrically connects the first rigid substrate and the second rigid substrate, wherein the thickness of the first rigid substrate is less than the thickness of the second rigid substrate. The flexible substrate is curved, and the upper surface of the first rigid substrate is at a lower height from the surface of the parent substrate compared to the upper surface of the second rigid substrate. Compared to the upper surface of the socket, the upper surface of the first rigid substrate is at a lower height from the surface of the mother substrate. Compared to the upper surface of the socket, the upper surface of the second rigid substrate is at a lower height from the surface of the mother substrate.

13. The information processing system according to claim 12, wherein... The controller and the non-volatile memory are sealed in a single package.

14. The information processing system according to claim 13, wherein... The total thickness of the first rigid substrate and the package is less than the thickness of the socket to which the connector is connected.

15. The information processing system according to claim 12, wherein... The controller and the non-volatile memory are mounted on the first rigid substrate via a pad grid array (LGA).

16. The information processing system according to claim 12, wherein The first rigid substrate has at least one screw hole, and the first rigid substrate is attached to the mother substrate by using at least one screw inserted into and engaging the screw hole.

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