Flash memory storage device and biasing method thereof

Abstract

A flash memory device includes an array of memory cells and a voltage generating circuit. The array of memory cells includes at least one string of memory cells. The string of memory cells is coupled between a bit line and a source line. The string of memory cells includes a plurality of memory cells, and each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the array of memory cells. The voltage generating circuit is configured to output a bias voltage to the word lines. A selected word line among the word lines is applied with a first voltage. Unselected word lines include a second word line and a third word line, which are applied with a second voltage and a third voltage, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the selected word line, respectively. In addition, a biasing method for a flash memory device is also provided.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory storage device and an operating method thereof, and more particularly to a flash memory storage device and a biasing method thereof. BACKGROUND

[0002] With the evolution of electronic technology, electronic devices have become essential tools in people's lives. Flash memory has become an important data storage medium by providing long-term and large-capacity data storage functions. A flash memory includes a plurality of memory cell strings. As the demand for data storage increases, the number of memory cells included in the memory cell strings also increases. However, during programming, gate-induced drain leakage (GIDL) affects the data state stored in the memory cells, reducing the reliability of the memory cells. SUMMARY

[0003] The present application provides a flash memory storage device and a biasing method thereof, which can reduce gate-induced drain leakage and improve the reliability of memory cells.

[0004] The flash memory storage device of the present application includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string. The memory cell string is coupled between a bit line and a source line. The memory cell string includes a plurality of memory cells, and each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array. The voltage generating circuit is used to output a bias voltage to the word line. A first word line selected among the word lines is applied with a first voltage. Unselected word lines include a second word line and a third word line, which are applied with a second voltage and a third voltage, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on both sides of the first word line, respectively.

[0005] In an embodiment of the present application, the second word line described above is located in a source side region between the first word line and the source line. The third word line is located in a drain side region between the first word line and the bit line.

[0006] In an embodiment of the present application, the second word line described above is the unselected word line closest to the first word line in the source side region, and the second word line is applied with the second voltage. The remaining unselected word lines in the source side region are all applied with a fourth voltage. The fourth voltage is less than the second voltage and greater than the third voltage.

[0007] In an embodiment of the present application, the third word line closest to the first word line in the drain side region is an unselected word line, and the third word line is applied with the third voltage. The remaining unselected word lines in the drain side region are applied with the fourth voltage. The fourth voltage is less than the second voltage and greater than the third voltage.

[0008] In an embodiment of the present application, the third word line closest to the first word line in the drain side region and the remaining unselected word lines are applied with the third voltage.

[0009] In an embodiment of the present application, the bit line and the source line are applied with a system voltage.

[0010] In an embodiment of the present application, the flash memory device is a NAND type flash memory.

[0011] A biasing method of a flash memory device of the present application includes applying a first voltage to a selected first word line among word lines, and applying a second voltage to an unselected second word line and a third voltage to an unselected third word line among the word lines. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on both sides of the first word line, respectively.

[0012] In an embodiment of the present application, the second word line is located in a source side region between the first word line and the source line. The third word line is located in a drain side region between the first word line and the bit line.

[0013] In an embodiment of the present application, the source side region includes a plurality of unselected word lines, and the second word line closest to the first word line is applied with the second voltage.

[0014] In an embodiment of the present application, the biasing method of the flash memory device further includes applying a fourth voltage to the remaining unselected word lines in the source side region except the second word line. The fourth voltage is less than the second voltage and greater than the third voltage.

[0015] In an embodiment of the present application, the drain side region includes a plurality of unselected word lines, and the third word line closest to the first word line is applied with the third voltage.

[0016] In an embodiment of the present application, the biasing method of the flash memory device further includes applying a fourth voltage to the remaining unselected word lines in the drain side region except the third word line. The fourth voltage is less than the second voltage and greater than the third voltage.

[0017] In one embodiment of the present application, the drain side region includes a plurality of unselected word lines, and a third voltage is applied to a third word line closest to the first word line and the remaining unselected word lines.

[0018] In one embodiment of the present application, the biasing method of the flash memory device further includes applying a system voltage to the bit lines and the source lines.

[0019] Based on the above, in one embodiment of the present application, the voltage generating circuit applies bias voltages of different magnitudes to the word lines, which can reduce gate-induced drain leakage current and improve the reliability of the memory cells.

[0020] In order to make the features and advantages of the present application more apparent, specific embodiments will be described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of a flash memory device according to one embodiment of the present application is shown.

[0022] Figure 2 A schematic diagram of a memory cell string according to one embodiment of the present application is shown. Figure 1

[0023] Figure 3 A schematic diagram of bias voltages applied to various drive lines in a memory cell array according to one embodiment of the present application is shown.

[0024] Figure 4 A schematic diagram of bias voltages applied to various drive lines in a memory cell array according to another embodiment of the present application is shown.

[0025] Figure 5 A flowchart of the steps of a biasing method of a flash memory device according to one embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] Figure 1 A schematic diagram of a flash memory device according to one embodiment of the present application is shown. Figure 2 A schematic diagram of a memory cell string according to one embodiment of the present application is shown. Please refer to Figure 1 Figure 1 and Figure 2 The flash memory device 100 according to the present embodiment includes a memory cell array 110 and a voltage generating circuit 120. The voltage generating circuit 120 is coupled to the memory cell array 110. In the present embodiment, the flash memory device 100 is, for example, a NAND-type flash memory. The voltage generating circuit 120 can be designed in a manner known to those skilled in the art.

[0027] ​​The memory cell array 110 includes bit lines BL, source lines SL, and word lines WL0 to WL31. The memory cell array 110 also includes at least one memory cell string 122. The memory cell string 122 is coupled between a bit line BL and a source line SL. The memory cell string 122 includes a plurality of memory cells M0 to M30, M31. The memory cells M0 to M30, M31 are coupled to corresponding word lines WL0 to WL30, WL31. For example, the memory cell M31 is coupled to the word line WL31, and the memory cell M0 is coupled to the word line WL0. The coupling relationship of other memory cells and their corresponding word lines can be derived by Figure 2 By analogy, the above is not repeated here. In addition, the number of memory cell strings, memory cells, and word lines is not intended to limit the present application.

[0028] In the present embodiment, the memory cell array 110 also includes selection transistors 121, 123, which are coupled to corresponding selection lines SGD, SGS, respectively. The memory cell string 122 is coupled between the selection transistors 121, 123. The selection transistors 121, 123 are used to select the memory cell string to be programmed during programming. In the present embodiment, the memory cell array 110 also includes dummy memory cells 125, 127, which are coupled to corresponding dummy word lines DWL, respectively. In one embodiment, the memory cell array 110 can also not include dummy memory cells and dummy word lines.

[0029] Figure 3 A schematic diagram illustrating the bias voltages applied to the drive lines in the memory cell array according to one embodiment of the present application is shown. Referring to Figures 1 to 3 The voltage generation circuit 120 is used to output bias voltages V to the word lines WL0 to WL31 during programming. The bias voltages V include a first voltage Vww, a second voltage Vpass_s, a third voltage Vpass_d, and a fourth voltage Vpass. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. The fourth voltage Vpass is less than the second voltage Vpass_s, and greater than the third voltage Vpass_d. In the present embodiment, the selected word line WL28 (the first word line) among the word lines WL0 to WL31 is applied with the first voltage Vww, and the unselected word lines WL27, WL29 to WL31 are applied with the second voltage Vpass_s and the third voltage Vpass_d. In Figure 3 In the histogram, the height in the vertical direction represents the magnitude of the voltage applied to the drive lines.

[0030] Specifically, among the word lines WL0 to WL31, the word line WL28 is, for example, a selected word line. The remaining word lines WL0 to WL27 (second word lines) and the word lines WL29 to WL31 (third word lines) are unselected word lines. In the present embodiment, with respect to the first word line WL28, the second word lines WL0 to WL27 are word lines closer to the source line SL, in which the WL27 is the word line closest to the first word line WL28. With respect to the first word line WL28, the third word lines WL29 to WL31 are word lines closer to the bit line BL, in which the WL29 is the word line closest to the first word line WL28.

[0031] In the present embodiment, the second word line WL27 closest to the first word line WL28 is applied with the second voltage Vpass_s, and the remaining second word lines WL0 to WL26 are applied with the fourth voltage Vpass, and the fourth voltage Vpass is smaller than the second voltage Vpass_s. In the present embodiment, since the voltage generation circuit 120 applies the second voltage Vpass_s, which is higher than the fourth voltage Vpass, to the single second word line WL27 closest to the first word line WL28 in the source side area, the speed of programming can be improved. In the present embodiment, only the single second word line WL27 closest to the first word line WL28 is applied with the second voltage Vpass_s, but the present application is not limited thereto. In an embodiment, the voltage generation circuit 120 can also apply the second voltage Vpass_s to one or more second word lines between the source line SL and the first word line WL28.

[0032] On the other hand, in the present embodiment, the third word lines WL29 to WL31 between the bit line BL and the first word line WL28 are all applied with the third voltage Vpass_d. In the present embodiment, since the voltage generation circuit 120 applies the third voltage Vpass_d to all of the third word lines WL29 to WL31 in the drain side area, the gate-induced drain leakage current of the drain side area can be reduced.

[0033] Furthermore, in the present embodiment, during programming, the bit line BL, the source line SL, and the select line SGD are applied with the system voltage VCC, the select line SGS is applied with the ground voltage GND, and the dummy word line DWL is applied with the dummy voltage VDWL. In the present embodiment, the system voltage VCC is equal to the dummy voltage VDWL, and the system voltage VCC is smaller than the third voltage Vpass_d. The system voltage VCC and the dummy voltage VDWL can be provided by the voltage generation circuit 120 or other circuits within the device.

[0034] In the present embodiment, the third voltages Vpass_d are applied to all of the third word lines WL29 to WL31 between the bit line BL and the first word line WL28, but the present application is not limited to this. In an embodiment, the voltage generating circuit 120 can also apply the third voltage Vpass_d to only at least one of the third word lines.

[0035] Figure 4 A schematic diagram illustrating the bias voltages applied to the driving lines in the array of memory cells in another embodiment of the present application is shown. Referring to Figure 1 , Figure 2 and Figure 4 In the present embodiment, the third word line WL29 closest to the first word line WL28 is applied with the third voltage Vpass_d, and the remaining third word lines WL30 and WL31 are applied with the fourth voltage Vpass, so as to reduce the gate-induced drain leakage current of the drain side region.

[0036] Figure 5 A flowchart illustrating the steps of the biasing method of the flash memory device in an embodiment of the present application is shown. Referring to Figures 1 to 3 and Figure 5 The operation method of the present embodiment is applicable to at least the flash memory device 100 shown in Figure 1 , but the present application is not limited to this. Taking the flash memory device 100 shown in Figure 1 as an example, in step S100, the voltage generating circuit 120 applies the first voltage Vww to the selected first word line WL28 among the word lines. In step S110, the voltage generating circuit 120 applies the second voltage Vpass_s to the unselected second word line WL27 among the word lines and the third voltage Vpass_d to the unselected third word lines WL29 to WL31. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. In addition, the biasing method of the present embodiment can be sufficiently taught, suggested and implemented by the description of the Figures 1 to 4 embodiment.

[0037] In summary, in the embodiments of the present application, the voltage generating circuit outputs asymmetric bias voltages to the unselected word lines on both sides of the selected word line during programming, which not only reduces the gate-induced drain leakage current and improves the reliability of the memory cells, but also improves the programming speed.

[0038] Although the present application has been disclosed with reference to the embodiments above, it is not intended to limit the present application, and anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, so the protection scope of the present application shall be defined by the appended claims.

[0039] SYMBOL DESCRIPTION

[0040] 100: flash memory device

[0041] 110: memory cell array

[0042] 120: voltage generating circuit

[0043] 121, 123: selection transistor

[0044] 125, 127: dummy memory cell

[0045] BL: bit line

[0046] DWL: dummy word line

[0047] GND: ground voltage

[0048] M0, M30, M31: memory cell

[0049] S100, S110: step

[0050] SGD, SGS: selection line

[0051] SL: source line

[0052] V: bias voltage

[0053] VCC: system voltage

[0054] VDWL: dummy voltage

[0055] Vpass_s: second voltage

[0056] Vpass_d: third voltage

[0057] Vpass: fourth voltage

[0058] Vww: first voltage

[0059] WL0, WL26, WL27, WL28, WL29, WL30, WL31: word line

Claims

1. A flash memory device, comprising: a memory cell array including at least one memory cell string coupled between a bit line and a source line, wherein the memory cell string includes a plurality of memory cells, and each of the memory cells is coupled to a corresponding word line; and a voltage generating circuit coupled to the memory cell array to output program bias voltages to the word lines, wherein a first word line selected among the word lines is applied with a first voltage, unselected word lines including a second word line and a third word line are applied with a second voltage and a third voltage respectively, and the first voltage is greater than the second voltage, the second voltage is greater than the third voltage, wherein the second word line and the third word line are located at two sides of the first word line respectively; wherein the second word line is located at a source side region between the first word line and the source line, and the third word line is located at a drain side region between the first word line and the bit line; wherein the second word line is an unselected word line closest to the first word line in the source side region, and the second word line is applied with the second voltage, and the rest of the unselected word lines in the source side region are applied with a fourth voltage, wherein the fourth voltage is less than the second voltage and greater than the third voltage.

2. The flash memory device of claim 1, wherein the third word line is an unselected word line closest to the first word line in the drain side region, and the third word line is applied with the third voltage, and the rest of the unselected word lines in the drain side region are applied with the fourth voltage.

3. The flash memory device of claim 1, wherein the third word line and the rest of the unselected word lines closest to the first word line in the drain side region are applied with the third voltage.

4. The flash memory device of claim 1, wherein the bit line and the source line are applied with a system voltage.

5. The flash memory device of claim 1, wherein the flash memory device is a NAND type flash memory.

6. A bias method for a flash memory device, wherein the flash memory device includes a memory cell array including at least one memory cell string coupled between a bit line and a source line, the memory cell string including a plurality of memory cells, and each of the memory cells is coupled to a corresponding word line, the memory cell array is coupled to a voltage generating circuit to output program bias voltages to the word lines, the bias method comprising: applying a first voltage to a first word line selected among the word lines; and applying a second voltage to a second word line unselected among the word lines and a third voltage to a third word line unselected among the word lines, wherein the first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the second word line and the third word line are located at two sides of the first word line respectively; wherein the second word line is located at a source side region between the first word line and the source line, and the third word line is located at a drain side region between the first word line and the bit line; ​ wherein the source side region includes a plurality of unselected word lines, and the second voltage is applied to the second word line closest to the first word line; a fourth voltage is applied to the remaining unselected word lines in the source side region other than the second word line, wherein the fourth voltage is less than the second voltage and greater than the third voltage.

7. The biasing method of a flash memory device of claim 6, wherein the drain side region includes a plurality of unselected word lines, and the third voltage is applied to the third word line closest to the first word line.

8. The biasing method of a flash memory device of claim 7, further comprising: the fourth voltage is applied to the remaining unselected word lines in the drain side region other than the third word line.

9. The biasing method of a flash memory device of claim 6, wherein the drain side region includes a plurality of unselected word lines, and the third voltage is applied to the third word line closest to the first word line and the remaining unselected word lines.

10. The biasing method of a flash memory device of claim 6, further comprising: a system voltage is applied to the bit line and the source line.

11. The biasing method of a flash memory device of claim 6, wherein the flash memory device is a NAND type flash memory.

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