An eFuse read / write circuit

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an eFuse read-write circuit, wherein the eFuse read-write circuit includes three parts: a control logic, a programming circuit, and a reading circuit. The control logic is used to control the circuit to switch between a programming state and a reading state as needed. By separating the read and write operations, the selection of the programming voltage can be made more flexible, and the optimal programming voltage of the eFuse can be found in a larger range, while the voltage required for the reading operation can be reduced. The programming circuit is used to burn the eFuse fuse; and the reading circuit is used to output a current signal that can reflect the resistance value of the fuse. The eFuse read-write circuit of the present invention can estimate the resistance magnitude of the fuse after programming by reading the output current value of the circuit, thereby determining the programming effect, and can more efficiently find the optimal conditions for programming the fuse.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an eFuse read-write circuit. Background Art

[0002] As semiconductor technology continues to advance in accordance with Moore's Law, chip integration is becoming increasingly dense, and the number of transistors accommodated on a single chip is increasing. However, the miniaturization of semiconductor devices and the increasing complexity of chips make the chip production process more susceptible to various defects and impurities, further exacerbating the problem of reduced chip production yield.

[0003] Electrically programmable fuses (eFuse) are non-volatile memories that can be programmed once. Once programmed, the information in an eFuse is not lost even if the system loses power. Compared to earlier laser fuses used for redundancy, eFuse fuses have a smaller structure and are fully compatible with existing CMOS processes, without incurring additional costs.

[0004] Using eFuses as redundant structures in integrated circuits, when a circuit is defective, the eFuses can be programmed to replace the defective circuit and repair the chip. Therefore, eFuses are widely used in various chips, allowing the circuit structure to be modified after the chip is manufactured. This can prevent the failure of a chip component from causing the entire circuit to fail, significantly reducing testing and chip repair costs and improving the yield rate of integrated circuits.

[0005] However, the programming effect of eFuse fuses is not only affected by the process, but also by the programming environment. When the programming signal deviates, the programming effect of the eFuse fuse will also change accordingly. Therefore, it is necessary to find the optimal eFuse programming conditions and a method to efficiently determine the eFuse programming effect. Summary of the Invention

[0006] In response to the problems existing in the prior art, the present invention provides an eFuse read-write circuit that can efficiently determine the programming effect of the eFuse fuse and simultaneously find the optimal programming conditions of the eFuse fuse in a larger range.

[0007] The technical solution of the present invention is: an eFuse read / write circuit, comprising: control logic, a programming circuit, and a reading circuit; the programming circuit is externally applied with a programming voltage, and its output terminal is connected to the reading circuit; the reading circuit is externally applied with a reading voltage, and its output terminal is an output voltage; the control logic generates an output control signal based on an input control signal;

[0008] The control logic is used to control the circuit to switch between programming mode and reading mode: the programming mode only supplies power to the programming circuit, and the reading mode only supplies power to the reading circuit; by distinguishing between the two modes, the voltage value of the programming circuit can be selected more freely, and the optimal programming condition can be found in a wider range;

[0009] The control logic is implemented using a combinational logic circuit.

[0010] The programming circuit is used to burn the eFuse fuse and includes two symmetrical programming branches;

[0011] The reading circuit is used to output the current flowing through the eFuse through a current mirror structure, so as to determine the magnitude of the fuse resistance by the magnitude of the output current. It includes: a bias branch and two reading branches.

[0012] Furthermore, the control logic input control signals include: an enable signal EN and a programming control signal Vp; the output control signals include: a read circuit switch signal Switch, and programming transistor control signals Vp1 and Vp2; the Switch signal is derived from the EN signal through an inverter; the EN and Vp signals are input to a NAND gate, then pass through an inverter to perform an AND operation on the two signals, outputting the Vp1 signal; the Vp signal is input to one end of the NAND gate after passing through an inverter, and the EN signal is input to the other input of the NAND gate; the resulting signal is then input to an inverter to generate the Vp2 signal. When the system operates in programming mode, EN = 1, and Vp1 and Vp2 select the programming branch; when the system operates in read mode, EN = 0, and Switch = 1 enables the read branch.

[0013] Furthermore, each programming branch includes: an eFuse and a programming transistor; one end of the eFuse is connected to the programming power supply voltage Vpro, and the other end is connected to the drain of the programming transistor, the gate of the programming transistor is connected to the control signal output by the control logic, and the source of the programming transistor is connected to the ground Vss; the eFuse and the programming transistor together form a loop from the power supply to the ground; the control signals of the two branches are Vp1 and Vp2, respectively, for selecting which programming branch to program, wherein Vp1 and Vp2 are not enabled at the same time; the drain voltages of the programming transistors are Vi1 and Vi2, respectively;

[0014] The selection range of the power supply voltage for normal operation of the programming branch is relatively wide, and the programming part adopts an independent power supply voltage Vpro, which is more conducive to finding the optimal programming voltage condition.

[0015] Furthermore, the programming transistor has a size of 600nm*105um and can carry a large programming current.

[0016] Furthermore, the reading branch includes an input branch and an output branch; the two reading branches are symmetrical structures;

[0017] The bias branch is used to provide a suitable DC bias for the reading circuit, and includes: a first bias transistor (M1), a second bias transistor (M3), a third transistor (M4), an enable transistor (M2), a first resistor (R1) and a second resistor (R2);

[0018] The first resistor is connected to the read voltage VDD and the source of the first bias transistor;

[0019] The drain of the first bias transistor is connected to the drain of the enable transistor and the source of the second bias transistor;

[0020] The gate of the first bias transistor is connected to the source of the enable transistor;

[0021] The gates of the first bias transistor and the second bias transistor are connected to Vb1 and Vb2 respectively;

[0022] The gate of the enable transistor is connected to an enable signal EN;

[0023] The gate and drain of the second bias transistor are connected and connected to the drain of the third transistor through a second resistor;

[0024] The drain and gate of the third transistor are connected;

[0025] The source of the third transistor is connected to Vss.

[0026] The input branch and the output branch of the reading branch form a self-biased current mirror structure, which is used to achieve accurate replication of the input current by the output current. Therefore, the two input branches and the two output branches form a set of symmetrical self-biased current mirror structures to achieve accurate output of the currents of the two programming branches.

[0027] The reading branch includes: a fourth bias transistor (M6), a fifth bias transistor (M7), a first input transistor (M8), a second input transistor (M9), a first output transistor (M11), a second output transistor (M10), an input branch resistor (R3), and an output branch resistor (R5); the source of the fourth bias transistor is connected to Vi1, the drain of the fourth bias transistor is connected to the source of the fifth bias transistor, and the gates of the fourth bias transistor and the fifth bias transistor are connected to Vb1 and Vb2, respectively;

[0028] The drain of the fifth bias transistor is connected to the gates of the first input transistor and the first output transistor, and is connected to one end of the input branch resistor; the other end of the input branch resistor is connected to the gates of the second input transistor and the second output transistor, and the drain of the first input transistor;

[0029] The source of the first input transistor is connected to the drain of the second input transistor;

[0030] The source of the first output transistor is connected to the drain of the second output transistor;

[0031] The source of the second input transistor is connected to the source of the second output transistor and is also connected to Vss;

[0032] The drain of the first output transistor is connected to the output branch resistor and is connected to the output voltage (Vo1 or Vo2);

[0033] By taking the difference between the output currents of the two output branches of the reading circuit, the change in the fuse resistance before and after programming can be more accurately seen.

[0034] Specifically, by providing appropriate bias voltages Vb1 and Vb2, when all transistors operate in the saturation region, the output terminal Vo1 will reflect the magnitude of the current flowing through the eFuse, thereby determining the resistance value of the programmed fuse.

[0035] By using the same bias for branches Vi1 and Vi2 in the read circuit, the voltage drops across the two fuses are essentially the same. Furthermore, the symmetrical circuit structure minimizes mismatches during circuit manufacturing, ensuring that the difference in output current between the two branches is solely due to the change in eFuse resistance before and after programming. This ensures that the output current more accurately reflects the change in eFuse resistance before and after programming.

[0036] The use of self-biasing technology in the cascode current mirror structure can make the output swing of the output branch larger, expand the current variation range caused by the change of fuse resistance, and make the output current reflect the change of resistance value more accurately.

[0037] Beneficial effects

[0038] With this design, the eFuse resistance determines the output current, which is reflected in the output voltage Vo. This allows eFuse resistance to be estimated simply by measuring the circuit's output voltage Vo, without the need to directly measure the eFuse resistance. This greatly facilitates evaluating eFuse programming performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the structure of the eFuse read / write circuit in this embodiment.

[0040] Figure 2 This is the control logic circuit diagram of this embodiment

[0041] Figure 3 This is the programming circuit diagram of this embodiment

[0042] Figure 4 Read the circuit diagram for this embodiment

[0043] Figure 5 This is the programming branch and output branch current curve diagram of this embodiment

[0044] Figure 6 This is a Monte Carlo simulation diagram of the difference between the two output branch currents in this embodiment. DETAILED DESCRIPTION

[0045] The technical solution provided by this application will be further described below in conjunction with specific embodiments and accompanying drawings. The advantages and features of this application will become more apparent with reference to the following description.

[0046] like Figure 1 FIG2 shows a schematic diagram of the structure of the eFuse read / write circuit of this embodiment. The eFuse read / write circuit is divided into three parts: control logic, programming circuit and reading circuit.

[0047] Figure 2 The control logic circuit diagram of the eFuse read-write circuit of this embodiment is shown. In the figure, INV represents an inverter, and NAND represents a NAND gate. The Switch signal is obtained by the EN signal through an inverter; after the EN and Vp signals are input into the NAND gate, they pass through an inverter to realize the AND operation of the two signals and output the Vp1 signal; the Vp signal passes through an inverter and inputs one end of the NAND gate, and the EN signal is input into the other input end of the NAND gate. The obtained signal is then input into the inverter to obtain the Vp2 signal. In this embodiment, the control logic controls the circuit to operate in programming mode or reading mode through the input signal EN. When EN=0, the eFuse fuse system operates in reading mode and Vp is invalid; when EN=1, the eFuse fuse system operates in programming mode, at this time Vp is valid, and the value of Vp at this time determines which branch of the eFuse fuse is burned. The output signals Vp1 and Vp2 of the control logic are connected to programming transistor 1 and programming transistor 2 respectively. If Vp=1, then Vp1=1, the programming transistor of branch 1 is turned on, and the fuse of branch 1 is programmed; if Vp=0, then Vp2=1, the programming transistor of branch 2 is turned on, and the fuse of branch 2 is programmed.

[0048] Figure 3The circuit diagram of the programming portion of the eFuse read / write circuit of this embodiment is shown. The broken line in the figure represents the eFuse, one end of which is connected to the programming supply voltage and the other end to the drain of the programming transistor. Together with the programming transistor, they form a loop from power to ground. The gates of the two programming transistors are connected to the Vp1 and Vp2 signals output by the control logic, respectively, to select the programming of the two fuses. In this embodiment, the programming portion comprises two symmetrical branches, each containing an eFuse and a programming transistor. When a given Vp signal is applied, only one of the eFuse fuses is programmed. The difference in resistance between the two fuses is the same as the difference in resistance before and after programming a single fuse. Therefore, the change in resistance before and after programming can be estimated by the difference in current between the two output branches. When the programming transistor is turned on, the programming voltage Vpro is applied to the fuse, and a large programming current flows through the eFuse fuse. Due to the electron migration effect, the silicide is pushed to one end by electrons, causing the resistance of the fuse connection to increase, which is reflected as a change in current at the output end.

[0049] Figure 4 The circuit diagram of the reading part of the eFuse read-write circuit of the present invention is shown. VDD represents the power supply voltage of the reading circuit, EN and Switch signals are control signals generated by the control logic, respectively connected to the gates of the M2 tube and the M5 tube, Vi1 and Vi2 signals are output signals of the programming branch, connected to the source of the M6 and M12 tubes, Vo1 and Vo2 are the output ends of the reading branch for outputting current. In this embodiment, the reading part includes a bias branch, two input branches and two output branches, and the two input branches and the two output branches are symmetrical structures. When the system operates in programming mode, EN=1, the M2 transistor is turned off, and the gate-drain of the M1 tube is disconnected to prevent unnecessary leakage in the bias branch in programming mode. When Switch = 0, transistor M5 turns on, pulling the gates of transistors M6 and M12 to VDD. These transistors then turn off, disabling the two input branches of the read circuit. When the system is in read mode, EN = 0, Switch = 1, transistor M2 turns on, M5 turns off, and M1 is connected to a diode. Since transistors M3, M7, and M13 are of the same size and have their gates connected together, their source voltages are the same, ensuring that current changes in the two read branches are completely driven by changes in the fuse resistance. This improves the accuracy of estimating the fuse resistance from the output current. M8, M9, M10, M11, and R3 form a self-biased cascode current mirror structure, mirroring the current in the input branch of the read circuit to the output branch. The use of self-biasing also increases the accuracy of the output current's response to resistance changes.

[0050] Figure 5 The two curves shown are the current curves of the programming branch and the output branch respectively. Figure 6 The figure shows a Monte Carlo simulation of the difference in output current between the two output branches when the resistance of the two fuse resistors is 44 Ohm. It can be seen that when the fuse resistance increases 10 times, that is, to 440 Ohm, the branch current change caused by the change is greater than the current fluctuation caused by the process deviation. Therefore, this circuit can distinguish a 10-fold change in resistance when the change in fuse resistance is small. Figure 5 and Figure 6 It can be seen that when the change in fuse resistance is small, the change in output current can distinguish 10 times the change in fuse resistance. When the change in fuse resistance is large, the change in output current can be distinguished based on the change in output current. Figure 5 The resistance value of the fuse can be estimated from the current curve.

[0051] In summary, the eFuse reading circuit of this embodiment can reflect the change in fuse resistance through the difference in output currents of the two output branches, thereby intuitively and efficiently judging the effect of fuse programming and facilitating the search for optimal fuse programming conditions.

[0052] The above description is only a description of the preferred embodiments of the present application and does not limit the scope of the present application. Any changes or modifications made by any person skilled in the art based on the above disclosed technical content should be regarded as equivalent valid embodiments and fall within the scope of protection of the technical solution of the present application.

Claims

1. An eFuse read / write circuit, characterized in that: include: control logic, programming circuits, and reading circuits; The programming circuit applies a programming voltage, and its output terminal is connected to the reading circuit; the reading circuit applies a reading voltage, and its output terminal is an output voltage; the control logic generates an output control signal according to the input control signal; The control logic is used to control the circuit to switch between programming mode and reading mode: the programming mode only supplies power to the programming circuit, and the reading mode only supplies power to the reading circuit; by distinguishing between the two modes, the voltage value of the programming circuit can be freely selected, and the optimal programming condition can be found in a wide range; The programming circuit is used to burn the eFuse fuse and includes two symmetrical programming branches; The reading circuit is used to output the current flowing through the eFuse fuse through the current mirror structure, thereby judging the magnitude of the fuse resistance by the output current, comprising: a bias branch and two read branches; The control logic is implemented using a combinational logic circuit; the control logic input control signals include: an enable signal EN and a programming control signal Vp; the output control signals include: a read circuit switch signal Switch, and programming transistor control signals Vp1 and Vp2; when the system operates in programming mode, EN=1, Vp1 and Vp2 select the programming branch; when the system operates in read mode, EN=0, Switch=1 turns on the read branch.

2. The eFuse read / write circuit according to claim 1, wherein: The Switch signal is obtained by passing the EN signal through an inverter; after the EN and Vp signals are input into the NAND gate, they pass through an inverter to perform the AND operation of the two signals and output the Vp1 signal; the Vp signal passes through an inverter and inputs one end of the NAND gate, and the EN signal is input into the other input end of the NAND gate. The obtained signal is then input into the inverter to obtain the Vp2 signal.

3. The eFuse read / write circuit according to claim 1, wherein: Each programming branch includes: an eFuse and a programming transistor; one end of the eFuse is connected to the programming power supply voltage Vpro, and the other end is connected to the drain of the programming transistor, the gate of the programming transistor is connected to the control signal output by the control logic, and the source of the programming transistor is connected to the ground Vss; the eFuse and the programming transistor together form a loop from the power supply to the ground; the control signals of the two branches are Vp1 and Vp2, respectively, which are used to select which programming branch to program, wherein Vp1 and Vp2 are not enabled at the same time; the drain voltages of the programming transistors are Vi1 and Vi2, respectively; The selection range of the power supply voltage for normal operation of the programming branch is relatively wide, and the programming part adopts an independent power supply voltage Vpro, which is more conducive to finding the optimal programming voltage condition.

4. The eFuse read / write circuit according to claim 3, wherein: The programming transistor has a size of 600nm*105um and can carry a large programming current.

5. The eFuse read / write circuit according to claim 1, wherein: The bias branch is used to provide a suitable DC bias for the reading circuit, and includes: a first bias transistor, a second bias transistor, a third transistor, an enable transistor, a first resistor, and a second resistor; The first resistor is connected to the read voltage VDD and the source of the first bias transistor; The drain of the first bias transistor is connected to the drain of the enable transistor and the source of the second bias transistor; The gate of the first bias transistor is connected to the source of the enable transistor; The gates of the first bias transistor and the second bias transistor are connected to Vb1 and Vb2 respectively; The gate of the enable transistor is connected to an enable signal EN; The gate and drain of the second bias transistor are connected and connected to the drain of the third transistor through a second resistor; The drain and gate of the third transistor are connected; The source of the third transistor is connected to Vss.

6. The eFuse read / write circuit according to claim 1, wherein: The reading branch includes an input branch and an output branch; the two reading branches are symmetrical structures; The input branch and the output branch of the reading branch form a self-biased current mirror structure, which is used to achieve accurate replication of the input current by the output current. Therefore, the two input branches and the two output branches form a set of symmetrical self-biased current mirror structures to achieve accurate output of the currents of the two programming branches. The reading branch includes: a fourth bias transistor, a fifth bias transistor, a first input transistor, a second input transistor, a first output transistor, a second output transistor, an input branch resistor, and an output branch resistor; the source of the fourth bias transistor is connected to Vi1 or Vi2, the drain of the fourth bias transistor is connected to the source of the fifth bias transistor, and the gates of the fourth bias transistor and the fifth bias transistor are connected to Vb1 and Vb2, respectively; The drain of the fifth bias transistor is connected to the gates of the first input transistor and the first output transistor, and is connected to one end of the input branch resistor; the other end of the input branch resistor is connected to the gates of the second input transistor and the second output transistor, and the drain of the first input transistor; The source of the first input transistor is connected to the drain of the second input transistor; The source of the first output transistor is connected to the drain of the second output transistor; The source of the second input transistor is connected to the source of the second output transistor and is also connected to Vss; The drain of the first output transistor is connected to the output branch resistor and is connected to the output voltage Vo1 or Vo2; By taking the difference between the output currents of the two output branches of the reading circuit, the change in the fuse resistance before and after programming can be more accurately seen; Specifically, by providing appropriate bias voltages Vb1 and Vb2, when all transistors operate in the saturation region, the output terminal Vo1 will reflect the current flowing through the eFuse, thereby determining the resistance value of the programmed fuse. By using the same bias for branches Vi1 and Vi2 in the read circuit, the voltage drops across the two fuses are essentially the same. Furthermore, the symmetrical circuit structure minimizes mismatches during circuit manufacturing, ensuring that the difference in output current between the two branches is solely due to the change in eFuse resistance before and after programming. This allows the output current to more accurately reflect the change in eFuse resistance before and after programming. The self-biasing technology is used in the cascode current mirror structure to make the output swing of the output branch larger, so that the current variation range caused by the change of the fuse resistance is larger, and the output current accurately reflects the change of the resistance value.

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